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SN54LV74A, SN74LV74A
SCLS381M – AUGUST 1997 – REVISED MARCH 2015

SNx4LV74A Dual Positive-Edge-Triggered D-Type Flip-Flops

1 Features 3 Description
•
1 2-V to 5.5-V VCC Operation These dual positive-edge-triggered D-type flip-flops
are designed for 2-V to 5.5-V VCC operation.
• Maximum tpd of 8.5 ns at 5 V
• Typical VOLP (Output Ground Bounce) Device Information(1)
< 0.8 V at VCC = 3.3 V, TA = 25°C PART NUMBER PACKAGE BODY SIZE (NOM)
• Typical VOHV (Output VOH Undershoot) VQFN (14) 3.50 mm × 3.50 mm
> 2.3 V at VCC = 3.3 V, TA = 25°C SOIC (14) 8.65 mm × 3.91 mm
• Support Mixed-Mode Voltage Operation on SN74LV74A SOP (14) 10.30 mm × 5.30 mm
All Ports SSOP (14) 6.20 mm × 5.30 mm
• Ioff Supports Partial-Power-Down TSSOP (14) 5.00 mm × 4.40 mm
Mode Operation
(1) For all available packages, see the orderable addendum at
• Latch-up Performance Exceeds 250 mA the end of the data sheet.
Per JESD 17
• ESD Protection Exceeds JESD 22 Logic Diagram, Each Flip-Flop
(Positive Logic)
– 2000-V Human-Body Model (A114-A) PRE

– 500-V Charged-Device Model (C101) CLK C C

C
Q
2 Applications TG

C C C
• Programmable Logic Controller (PLC) C

• DCS and PAC: Analog Input Module D TG TG TG

• AV Receiver Q
C C C
• Server PSU CLR

• STB, DVR, and Streaming Media (Withdraw)

• Server Motherboard

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
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Table of Contents
1 Features .................................................................. 1 7 Parameter Measurement Information .................. 9
2 Applications ........................................................... 1 8 Detailed Description ............................................ 10
3 Description ............................................................. 1 8.1 Overview ................................................................. 10
4 Revision History..................................................... 2 8.2 Functional Block Diagram ....................................... 10
5 Pin Configuration and Functions ......................... 3 8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 11
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4 9 Application and Implementation ........................ 12
6.2 ESD Ratings.............................................................. 4 9.1 Application Information............................................ 12
6.3 Recommended Operating Conditions....................... 5 9.2 Typical Application ................................................. 12
6.4 Electrical Characteristics........................................... 5 10 Power Supply Recommendations ..................... 14
6.5 Switching Characteristics: VCC = 2.5 V ± 0.2 V ........ 6 11 Layout................................................................... 14
6.6 Switching Characteristics: VCC = 3.3 V ± 0.3 V ........ 6 11.1 Layout Guidelines ................................................. 14
6.7 Switching Characteristics: VCC = 5 V ± 0.5 V ........... 6 11.2 Layout Example .................................................... 14
6.8 Timing Requirements: VCC = 2.5 V ± 0.2 V .............. 6 12 Device and Documentation Support ................. 15
6.9 Timing Requirements: VCC = 3.3 V ± 0.3 V .............. 7 12.1 Documentation Support ........................................ 15
6.10 Timing Requirements: VCC = 5 V ± 0.5 V ............... 7 12.2 Trademarks ........................................................... 15
6.11 Noise Characteristics .............................................. 7 12.3 Electrostatic Discharge Caution ............................ 15
6.12 Operating Characteristics........................................ 7 12.4 Glossary ................................................................ 15
6.13 Typical Characteristics ............................................ 8 13 Mechanical, Packaging, and Orderable
Information ........................................................... 15

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision L (April 2005) to Revision M Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
• Removed Ordering Information table. .................................................................................................................................... 1

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5 Pin Configuration and Functions

D, DGV, NS, or PW Package

14-PIN SOIC, SOP, SSOP, or TSSOP
Top View

1CLR 1 14 VCC
1D 2 13 2CLR
1CLK 3 12 2D
1PRE 4 11 2CLK
1Q 5 10 2PRE
1Q 6 9 2Q
GND 7 8 2Q

RGY Package
14-PIN VQFN
Top View

1CLR

VCC
1 14
1D 2 13 2CLR
1CLK 3 12 2D
1PRE 4 11 2CLK
1Q 5 10 2PRE
1Q 6 9 2Q
7 8
GND

2Q

Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
1 1CLR I 1 clear
2 1D I 1D input
3 1CLK I 1 clock
4 1PRE I 1 preset
5 1Q O 1Q output
6 1Q O 1Q output
7 GND – GND
8 2Q O 2Q output
9 2Q O 2Q output
10 2PRE I 2 preset
11 2CLK I 2 clock
12 2D I 2D input
13 2CLR I 2 clear
14 Vcc – Supply voltage input

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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
(2)
VI Input voltage –0.5 7 V
VO Voltage applied to any output in the high-impedance or power-off state (2) –0.5 7 V
VO Output voltage (2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –20 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current VO = 0 to VCC ±25 mA
Continuous current through VCC or GND ±50 mA
D package (4) 86
DB package (4) 96
DGV package (4) 127
θJA Package thermal impedance °C/W
NS package (4) 76
PW package (4) 113
RGY package (5) 47
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 5.5 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) The package thermal impedance is calculated in accordance with JESD 51-5.

6.2 ESD Ratings

VALUE UNIT
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- 500 V
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
SN54LV74A (2) SN74LV74A
UNIT
MIN MAX MIN MAX
VCC Supply voltage 2 5.5 2 5.5 V
VCC = 2 V 1.5
VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7
VIH High-level input voltage V
VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7
VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7
VCC = 2 V 0.5 0.5
VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3
VIL Low-level input voltage V
VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3
VCC = 4.5 V to 5.5 V VCC × 0.3 VCC × 0.3
VI Input voltage 0 5.5 0 5.5 V
VO Output voltage 0 VCC 0 VCC V
VCC = 2 V –50 –50 µA
VCC = 2.3 V to 2.7 V –2 –2
IOH High-level output current
VCC = 3 V to 3.6 V –6 –6 mA
VCC = 4.5 V to 5.5 V –12 –12
VCC = 2 V 50 50 µA
VCC = 2.3 V to 2.7 V 2 2
IOL Low-level output current
VCC = 3 V to 3.6 V 6 6 mA
VCC = 4.5 V to 5.5 V 12 12
VCC = 2.3 V to 2.7 V 200 200
Δt/Δv Input transition rise or fall rate VCC = 3 V to 3.6 V 100 100 ns/V
VCC = 4.5 V to 5.5 V 20 20
TA Operating free-air temperature –55 125 –40 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
(2) Product Preview

6.4 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
SN74LV74A SN74LV74A
SN54LV74A (1)
PARAMETER TEST CONDITIONS VCC –40°C to 85°C –40°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
VCC–0.
IOH = –50 µA 2 V to 5.5 V VCC–0.1 VCC–0.1
1

VOH IOH = –2 mA 2.3 V 2 2 2 V

IOH = –6 mA 3V 2.48 2.48 2.48
IOH = –12 mA 4.5 V 3.8 3.8 3.8
IOL = 50 µA 2 V to 5.5 V 0.1 0.1 0.1
IOL = 2 mA 2.3 V 0.4 0.4 0.4
VOL V
IOL = 6 mA 3V 0.44 0.44 0.44
IOL = 12 mA 4.5 V 0.55 0.55 0.55
II VI = 5.5 V or GND 0 to 5.5 V ±1 ±1 ±1 µA
ICC VI = VCC or GND, IO = 0 5.5 V 20 20 20 µA
Ioff VI or VO = 5.5 V 0 5 5 5 µA
3.3 V 2 2 2
Ci VI = VCC or GND pF
5V 2 2 2

(1) Product Preview

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6.5 Switching Characteristics: VCC = 2.5 V ± 0.2 V

over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 3)
SN74LV74A SN74LV74A
FROM TO LOAD TA = 25°C SN54LV74A (1)
PARAMETER –40°C to 85°C –40°C to 125°C UNIT
(INPUT) (OUTPUT) CAPACITANCE
MIN TYP MAX MIN MAX MIN MAX MIN MAX
CL = 15 pF 50 (2) 100 (2) 40 (2) 40 40
fmax MHz
CL = 50 pF 30 70 25 25 25
(2) (2) (2) (2)
PRE or CLR 9.8 14.8 1 17 1 17 1 18
tpd Q or Q CL = 15 pF ns
CLK 11.1 (2) 16.4 (2) 1 (2) 19 (2) 1 19 1 20
PRE or CLR 13 17.4 1 20 1 20 1 21
tpd Q or Q CL = 50 pF ns
CLK 14.2 20 1 23 1 23 1 24

(1) Product Preview

(2) On products compliant to MIL-PRF-38535, this parameter is not production tested.

6.6 Switching Characteristics: VCC = 3.3 V ± 0.3 V

over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 3)
SN74LV74A SN74LV74A
FROM TO LOAD TA = 25°C SN54LV74A (1)
PARAMETER –40°C to 85°C –40°C to 125°C UNIT
(INPUT) (OUTPUT) CAPACITANCE
MIN TYP MAX MIN MAX MIN MAX MIN MAX
CL = 15 pF 80 (2) 140 (2) 70 (2) 70 70
fmax MHz
CL = 50 pF 50 90 45 45 45
PRE or CLR 6.9 (2) 12.3 (2) 1 (2) 14.5 (2) 1 14.5 1 15.5
tpd Q or Q CL = 15 pF (2) (2) (2)
ns
CLK 7.9 11.9 1 14 (2) 1 14 1 15
PRE or CLR 9.2 15.8 1 18 1 18 1 19
tpd Q or Q CL = 50 pF ns
CLK 10.2 15.4 1 17.5 1 17.5 1 18.5

(1) Product Preview

(2) On products compliant to MIL-PRF-38535, this parameter is not production tested.

6.7 Switching Characteristics: VCC = 5 V ± 0.5 V

over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 3)
SN74LV74A SN74LV74A
FROM TO LOAD TA = 25°C SN54LV74A (1)
PARAMETER –40°C to 85°C –40°C to 125°C UNIT
(INPUT) (OUTPUT) CAPACITANCE
MIN TYP MAX MIN MAX MIN MAX MIN MAX
CL = 15 pF 130 (2) 180 (2) 110 (2) 110 110
fmax MHz
CL = 50 pF 90 140 75 75 75
PRE or CLR 5 (2) 7.7 (2) 1 (2) 9 (2) 1 9 1 10
tpd Q or Q CL = 15 pF (2) (2) (2) (2)
ns
CLK 5.6 7.3 1 8.5 1 8.5 1 9.5
PRE or CLR 6.6 9.7 1 11 1 11 1 12
tpd Q or Q CL = 50 pF ns
CLK 7.2 9.3 1 10.5 1 10.5 1 11.5

(1) Product Preview

(2) On products compliant to MIL-PRF-38535, this parameter is not production tested.

6.8 Timing Requirements: VCC = 2.5 V ± 0.2 V

over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 3)
SN74LV74A SN74LV74A
TA = 25°C SN54LV74A (1)
–40°C to 85°C –40°C to 125°C UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
PRE or CLR low 8 9 9 9
tw Pulse duration ns
CLK 8 9 9 9
Data 8 9 9 9
tsu Setup time before CLK↑ ns
PRE or CLR inactive 7 7 7 7
th Hold time, data after CLK↑ 0.5 0.5 0.5 0.5 ns

(1) Product Preview

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6.9 Timing Requirements: VCC = 3.3 V ± 0.3 V

over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 3)
SN74LV74A SN74LV74A
TA = 25°C SN54LV74A (1)
–40°C to 85°C –40°C to 125°C UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
PRE or CLR low 6 7 7 7
tw Pulse duration ns
CLK 6 7 7 7
Data 6 7 7 7
tsu Setup time before CLK↑ ns
PRE or CLR inactive 5 5 5 5
th Hold time, data after CLK↑ 0.5 0.5 0.5 0.5 ns

(1) Product Preview

6.10 Timing Requirements: VCC = 5 V ± 0.5 V

over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 3)
SN74LV74A SN74LV74A
TA = 25°C SN54LV74A (1)
–40°C to 85°C –40°C to 125°C UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
PRE or CLR low 5 5 5 5
tw Pulse duration ns
CLK 5 5 5 5
Data 5 5 5 5
tsu Setup time before CLK↑ ns
PRE or CLR inactive 3 3 3 3
th Hold time, data after CLK↑ 0.5 0.5 0.5 0.5 ns

(1) Product Preview

6.11 Noise Characteristics (1)

VCC = 3.3 V, CL = 50 pF, TA = 25°C
SN74LV74A
PARAMETER UNIT
MIN TYP MAX
VOL(P) Quiet output, maximum dynamic VOL 0.1 0.8 V
VOL(V) Quiet output, minimum dynamic VOL 0 –0.8 V
VOH(V) Quiet output, minimum dynamic VOH 3.2 V
VIH(D) High-level dynamic input voltage 2.31 V
VIL(D) Low-level dynamic input voltage 0.99 V

(1) Characteristics are for surface-mount packages only.

6.12 Operating Characteristics

TA = 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
3.3 V 21
Cpd Power dissipation capacitance CL = 50 pF f = 10 MHz pF
5V 23

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6.13 Typical Characteristics

8 12

7
10
6
8
5

TPD (ns)
TPD (ns)

4 6

3
4
2
2
1

0 0
-100 -50 0 50 100 150 0 1 2 3 4 5 6
Temperature D001
VCC D002
Figure 1. TPD vs. Temperature at 3.3 V Figure 2. TPD vs. VCC at 25°C

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7 Parameter Measurement Information

VCC
RL = 1 kΩ S1 Open
From Output Test From Output TEST S1
Under Test Point Under Test GND tPLH/tPHL Open
CL CL tPLZ/tPZL VCC
(see Note A) (see Note A) tPHZ/tPZH GND
Open Drain VCC

LOAD CIRCUIT FOR LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS 3-STATE AND OPEN-DRAIN OUTPUTS

VCC
Timing Input 50% VCC
tw 0V
th
VCC tsu
VCC
Input 50% VCC 50% VCC
Data Input 50% VCC 50% VCC
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VCC VCC
Output
Input 50% VCC 50% VCC 50% VCC 50% VCC
Control
0V 0V

tPLH tPHL tPZL tPLZ

VOH Output ≈VCC
In-Phase 50% VCC 50% VCC Waveform 1 50% VCC
Output S1 at VCC VOL + 0.3 V
VOL VOL
(see Note B)
tPHL tPLH tPZH tPHZ
VOH Output
VOH
Out-of-Phase Waveform 2 VOH − 0.3 V
50% VCC 50% VCC 50% VCC
Output S1 at GND
VOL ≈0 V
(see Note B)
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 3. Load Circuit and Voltage Waveforms

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8 Detailed Description

8.1 Overview
These dual positive-edge-triggered D-type flip-flops are designed for 2-V to 5.5-V VCC operation.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs. The state of the output upon
power-up is not known until the first valid clock edge has occurred while VCC is within Recommended Operating
Conditions.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.

8.2 Functional Block Diagram

PRE

CLK C C

C
Q
TG

C C C
C

D TG TG TG

Q
C C C
CLR

Figure 4. Logic Diagram, Each Flip-Flop (Positive Logic)

8.3 Feature Description

The device’s wide operating range allows it to be used in a variety of systems that use different logic levels. The
low propagation delay allows fast switching and higher speeds of operation. In addition, the low ground bounce
stabilizes the performance of non-switching outputs while another output is switching.

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8.4 Device Functional Modes

Table 1. Function Table

INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
H L X X L H
L L X X H (1) H (1)
H H ↑ H H L
H H ↑ L L H
H H L X Q0 Q0

(1) This configuration is nonstable; that is, it does not persist when PRE
or CLR returns to its inactive (high) level.

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The SN74LV74A is a Low drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The inputs can accept voltages to 5.5 V at any valid VCC making it Ideal for down translation.

9.2 Typical Application

Figure 5. Typical Application Schematic

9.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads
so consider routing and load conditions to prevent ringing.

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Typical Application (continued)

9.2.2 Detailed Design Procedure
• Recommended input conditions:
– Specified High and low levels. See (VIH and VIL) in Recommended Operating Conditions.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
• Recommended output conditions:
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.

9.2.3 Application Curves

Figure 6. Switching Characteristics Comparison

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10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, TI recommends a 0.1-μF capacitor and if there are multiple VCC terminals then TI recommends a 0.01-μF
or 0.022-μF capacitor for each power terminal. Multiple bypass capacitors can be paralleled to reject different
frequencies of noise. Frequencies of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor
should be installed as close as possible to the power terminal for best results.

11 Layout

11.1 Layout Guidelines

When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only three of the four buffer gates are used. Such input pins should
not be left unconnected because the undefined voltages at the outside connections result in undefined
operational states. Specified below are the rules that must be observed under all circumstances. All unused
inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic
level that should be applied to any particular unused input depends on the function of the device. Generally they
will be tied to GND or VCC whichever make more sense or is more convenient. Floating outputs is generally
acceptable, unless the part is a transceiver. If the transceiver has an output enable pin it will disable the outputs
section of the part when asserted. This will not disable the input section of the I.O’s so they also cannot float
when disabled.

11.2 Layout Example

Figure 7. Layout Recommendation

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004

12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN74LV74AD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV74A
& no Sb/Br)
SN74LV74ADBR ACTIVE SSOP DB 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV74A
& no Sb/Br)
SN74LV74ADGVR ACTIVE TVSOP DGV 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV74A
& no Sb/Br)
SN74LV74ADR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV74A
& no Sb/Br)
SN74LV74ANSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 74LV74A
& no Sb/Br)
SN74LV74APW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV74A
& no Sb/Br)
SN74LV74APWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LV74A
& no Sb/Br)
SN74LV74APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV74A
& no Sb/Br)
SN74LV74APWT ACTIVE TSSOP PW 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV74A
& no Sb/Br)
SN74LV74ARGYR ACTIVE VQFN RGY 14 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 LV74A
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LV74A :

• Automotive: SN74LV74A-Q1
• Enhanced Product: SN74LV74A-EP

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jul-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LV74ADGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74LV74ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LV74APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV74APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV74APWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV74APWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV74ARGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jul-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LV74ADGVR TVSOP DGV 14 2000 367.0 367.0 35.0
SN74LV74ADR SOIC D 14 2500 367.0 367.0 38.0
SN74LV74APWR TSSOP PW 14 2000 367.0 367.0 35.0
SN74LV74APWR TSSOP PW 14 2000 364.0 364.0 27.0
SN74LV74APWRG4 TSSOP PW 14 2000 367.0 367.0 35.0
SN74LV74APWT TSSOP PW 14 250 367.0 367.0 35.0
SN74LV74ARGYR VQFN RGY 14 3000 367.0 367.0 35.0

Pack Materials-Page 2
 MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23
0,40 0,07 M
0,13
24 13

0,16 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25

0°–
8°
0,75
1 12
0,50
A

Seating Plane

0,15
1,20 MAX 0,08
0,05

PINS **
14 16 20 24 38 48 56
DIM

A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40

A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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