Product Sample & Technical Tools & Support &

Folder Buy Documents Software Community

SN74LVC1G126
SCES224R – APRIL 1999 – REVISED JANUARY 2015

SN74LVC1G126 Single Bus Buffer Gate With 3-State Output

1 Features 2 Applications
1• Available in the Texas Instruments • Cable Modem Termination Systems
NanoFree™ Package • High-Speed Data Acquisition and Generation
• Supports 5-V VCC Operation • Military: Radars and Sonars
• Inputs Accept Voltages to 5.5 V • Motor Controls: High-Voltage
• Provides Down Translation to VCC • Power Line Communication Modems
• Max tpd of 3.7 ns at 3.3 V • SSDs: Internal or External
• Low Power Consumption, 10-μA Max ICC • Video Broadcasting and Infrastructure: Scalable
• ±24-mA Output Drive at 3.3 V Platforms
• Ioff Supports Live Insertion, Partial-Power-Down • Video Broadcasting: IP-Based Multi-Format
Mode, and Back Drive Protection Transcoders
• Latch-Up Performance Exceeds 100 mA • Video Communication Systems
Per JESD 78, Class II
• ESD Protection Exceeds JESD 22 3 Description
– 2000-V Human-Body Model This single buffer is designed for 1.65-V to 3.6-V VCC
operation. The LVC1G126 device is a single line
– 200-V Machine Model driver with 3-state output. The output is disabled
– 1000-V Charged-Device Model when the output-enable input is low.

Device Information(1)
PART NUMBER PACKAGE (PIN) BODY SIZE
SOT-23 (5) 2.90 mm × 1.60 mm
SC70 (5) 2.00 mm × 1.25 mm
SN74LVC1G126 SOT (5) 1.60 mm × 1.20 mm
SON (6) 1.00 mm × 1.00 mm
XBGA (5) 1.40 mm × 0.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

4 Simplified Schematic
1
OE

2 4
A Y

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G126
SCES224R – APRIL 1999 – REVISED JANUARY 2015 www.ti.com

Table of Contents
1 Features .................................................................. 1 9 Detailed Description ............................................ 10
2 Applications ........................................................... 1 9.1 Overview ................................................................. 10
3 Description ............................................................. 1 9.2 Functional Block Diagram ....................................... 10
4 Simplified Schematic............................................. 1 9.3 Feature Description................................................. 10
9.4 Device Functional Modes........................................ 10
5 Revision History..................................................... 2
6 Pin Configuration and Functions ......................... 3 10 Application and Implementation........................ 11
10.1 Application Information.......................................... 11
7 Specifications......................................................... 4
10.2 Typical Application ............................................... 11
7.1 Absolute Maximum Ratings ..................................... 4
7.2 ESD Ratings.............................................................. 4 11 Power Supply Recommendations ..................... 12
7.3 Recommended Operating Conditions ...................... 5 12 Layout................................................................... 12
7.4 Thermal Information .................................................. 5 12.1 Layout Guidelines ................................................. 12
7.5 Electrical Characteristics........................................... 6 12.2 Layout Example .................................................... 12
7.6 Switching Characteristics, CL = 15 pF ...................... 6 13 Device and Documentation Support ................. 13
7.7 Switching Characteristics, –40°C to 85°C................. 6 13.1 Trademarks ........................................................... 13
7.8 Switching Characteristics, –40°C to 125°C............... 7 13.2 Electrostatic Discharge Caution ............................ 13
7.9 Operating Characteristics ........................................ 7 13.3 Glossary ................................................................ 13
7.10 Typical Characteristics ............................................ 7 14 Mechanical, Packaging, and Orderable
8 Parameter Measurement Information .................. 8 Information ........................................................... 13

5 Revision History
Changes from Revision Q (December 2013) to Revision R Page

• Added Applications, Device Information table, Handling Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ..... 1

Changes from Revision P (November 2012) to Revision Q Page

• Updated document to new TI data sheet format. ................................................................................................................... 1

• Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 5
• Added ESD warning. ............................................................................................................................................................ 13

Changes from Revision O (March 2011) to Revision P Page

• Removed Ordering Information table. .................................................................................................................................... 1

Changes from Revision N (February 2007) to Revision O Page

• Added DSF package option to the data sheet. ...................................................................................................................... 3

2 Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated

Product Folder Links: SN74LVC1G126

 SN74LVC1G126
www.ti.com SCES224R – APRIL 1999 – REVISED JANUARY 2015

6 Pin Configuration and Functions

DBV PACKAGE DCK PACKAGE DRL PACKAGE
(TOP VIEW) (TOP VIEW) (TOP VIEW)

OE 1 5 VCC OE 1 5 VCC
OE 1 5 VCC
A 2
A 2
A 2 GND 3 4 Y
GND 3 4 Y

GND 3 4 Y

DRY PACKAGE DSF PACKAGE YZP PACKAGE

(TOP VIEW) (TOP VIEW) (BOTTOM VIEW)

OE 1 6 VCC OE 1 6 VCC GND C1 3 4 C2 Y

A 2 5 N.C. A B1 2
A 2 5 N.C.
GND 3 4 Y OE A1 1 5 A2 VCC
GND 3 4 Y

See mechanical drawings for dimensions.

Pin Functions
PIN
SN74LVC1G126
TYPE DESCRIPTION
NAME DBV, DCK,
DRY, DSF
DRL, YZP
A 2 2 I A Input
GND 3 3 — Ground Pin
NC — 5 — Do not connect
OE 1 1 I OE Enable/Input
VCC 5 6 — Power Pin
Y 4 4 O Y Output

Copyright © 1999–2015, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Links: SN74LVC1G126
SN74LVC1G126
SCES224R – APRIL 1999 – REVISED JANUARY 2015 www.ti.com

7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 V
(2)
VI Input voltage range –0.5 6.5 V
VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V
VO Voltage range applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.

7.2 ESD Ratings

PARAMETER DEFINITION VALUE UNIT
Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 2000
V(ESD) V
discharge Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4 Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated

Product Folder Links: SN74LVC1G126

 SN74LVC1G126
www.ti.com SCES224R – APRIL 1999 – REVISED JANUARY 2015

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Operating 1.65 5.5
VCC Supply voltage V
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC
VCC = 2.3 V to 2.7 V 1.7
VIH High-level input voltage V
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × VCC
VCC = 1.65 V to 1.95 V 0.35 × VCC
VCC = 2.3 V to 2.7 V 0.7
VIL Low-level input voltage V
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × VCC
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current –16 mA
VCC = 3 V
–24
VCC = 4.5 V –32
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current 16 mA
VCC = 3 V
24
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
Δt/Δv Input transition rise or fall rate VCC = 3.3 V ± 0.3 V 10 ns/V
VCC = 5 V ± 0.5 V 5
TA Operating free-air temperature –40 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

7.4 Thermal Information

SN74LVC1G126
(1)
THERMAL METRIC DBV DCK DRL DRY YZP UNIT
5 PINS 5 PINS 5 PINS 6 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 206 252 142 234 132 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

Copyright © 1999–2015, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Links: SN74LVC1G126
SN74LVC1G126
SCES224R – APRIL 1999 – REVISED JANUARY 2015 www.ti.com

7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
–40°C to 85°C –40°C to 125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP (1) MAX MIN TYP (1) MAX
VCC –
IOH = –100 μA 1.65 V to 5.5 V VCC – 0.1
0.1
IOH = –4 mA 1.65 V 1.2 1.2

VOH IOH = –8 mA 2.3 V 1.9 1.9 V

IOH = –16 mA 2.4 2.4
3V
IOH = –24 mA 2.3 2.3
IOH = –32 mA 4.5 V 3.8 3.8
IOL = 100 μA 1.65 V to 5.5 V 0.1 0.1
IOL = 4 mA 1.65 V 0.45 0.45
IOL = 8 mA 2.3 V 0.3 0.3
VOL V
IOL = 16 mA 0.4 0.4
3V
IOL = 24 mA 0.55 0.55
IOL = 32 mA 4.5 V 0.55 0.55
A or OE
II VI = 5.5 V or GND 0 to 5.5 V ±5 ±5 μA
inputs
Ioff VI or VO = 5.5 V 0 ±10 ±10 μA
IOZ VO = 0 to 5.5 V 3.6 V 10 10 μA
ICC VI = 5.5 V or GND IO = 0 1.65 V to 5.5 V 10 10 μA
One input at VCC – 0.6 V,
ΔICC 3 V to 5.5 V 500 500 μA
Other inputs at VCC or GND
Ci VI = VCC or GND 3.3 V 4 4 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

7.6 Switching Characteristics, CL = 15 pF

over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3)
–40°C to 85°C
FROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A Y 1.7 6.9 0.6 4.6 0.6 3.7 0.5 3.4 ns

7.7 Switching Characteristics, –40°C to 85°C

over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 4)
–40°C to 85°C
FROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A Y 2.6 8 1.1 5.5 1 4.5 1 4 ns
ten OE Y 2.8 9.4 1.3 6.6 1.2 5.3 1 5 ns
tdis OE Y 1.6 9.8 1 5.5 1 5.5 1 4.2 ns

6 Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated

Product Folder Links: SN74LVC1G126

 SN74LVC1G126
www.ti.com SCES224R – APRIL 1999 – REVISED JANUARY 2015

7.8 Switching Characteristics, –40°C to 125°C

over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 4)
–40°C to 125°C
FROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A Y 2.6 9 1.1 5.7 1 4.7 1 4.2 ns
ten OE Y 2.8 9.6 1.3 6.8 1.2 5.5 1 5.2 ns
tdis OE Y 1.6 10 1 5.7 1 5.7 1 4.4 ns

7.9 Operating Characteristics

TA = 25°C
TEST VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
CONDITIONS TYP TYP TYP TYP

Power dissipation Outputs enabled 19 19 19 21

Cpd f = 10 MHz pF
capacitance Outputs disabled 2 2 3 4

7.10 Typical Characteristics

14 10
VCC = 3 V, VCC = 3 V,
TA = 25°C TA = 25°C
12
tpd – Propagation Delay Time – ns
tpd – Propagation Delay Time – ns

One Output Switching One Output Switching

8

10

8 6

6
4
4

2 2
0 50 100 150 200 250 300 0 50 100 150 200 250 300
CL – Load Capacitance – pF CL – Load Capacitance – pF
Figure 1. Propagation Delay (Low to High Transition) Figure 2. Propagation Delay (High to Low Transition)
vs Load Capacitance vs Load Capacitance

Copyright © 1999–2015, Texas Instruments Incorporated Submit Documentation Feedback 7

Product Folder Links: SN74LVC1G126
SN74LVC1G126
SCES224R – APRIL 1999 – REVISED JANUARY 2015 www.ti.com

8 Parameter Measurement Information

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
RL tPLZ/tPZL VLOAD
(see Note A)
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL V∆
VI tr/tf
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 15 pF 1 MΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 15 pF 1 MΩ 0.15 V
3.3 V ± 0.3 V 3V ≤2.5 ns 1.5 V 6V 15 pF 1 MΩ 0.3 V
5 V ± 0.5 V VCC ≤2.5 ns VCC/2 2 × VCC 15 pF 1 MΩ 0.3 V

VI
Timing Input VM
0V
tw

VI tsu th
VI
Input VM VM
Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
Output
VOH VLOAD/2
Waveform 1
Output VM VM VM
S1 at VLOAD VOL + V∆
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
VOH Output
VOH
VM VM Waveform 2 VOH − V∆
Output VM
S1 at GND
VOL ≈0 V
(see Note B)
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 3. Load Circuit and Voltage Waveforms

8 Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated

Product Folder Links: SN74LVC1G126

 SN74LVC1G126
www.ti.com SCES224R – APRIL 1999 – REVISED JANUARY 2015

Parameter Measurement Information (continued)

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
RL tPLZ/tPZL VLOAD
(see Note A)
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL V∆
VI tr/tf
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V
3.3 V ± 0.3 V 3V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V
5 V ± 0.5 V VCC ≤2.5 ns VCC/2 2 × VCC 50 pF 500 Ω 0.3 V

VI
Timing Input VM
0V
tw

VI tsu th
VI
Input VM VM
Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
Output
VOH VLOAD/2
Waveform 1
Output VM VM VM
S1 at VLOAD VOL + V∆
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
VOH Output
VOH
VM VM Waveform 2 VOH − V∆
Output VM
S1 at GND
VOL ≈0 V
(see Note B)
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 4. Load Circuit and Voltage Waveforms

Copyright © 1999–2015, Texas Instruments Incorporated Submit Documentation Feedback 9

Product Folder Links: SN74LVC1G126
SN74LVC1G126
SCES224R – APRIL 1999 – REVISED JANUARY 2015 www.ti.com

9 Detailed Description

9.1 Overview
The SN74LVC1G126 device contains a dual buffer gate with output enable control and performs the Boolean
function Y = A.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pull-
down resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

9.2 Functional Block Diagram

1
OE

2 4
A Y

9.3 Feature Description

• 1.65 V to 5.5 V operating voltage range
• Allows down voltage translation
– 5 V to 3.3 V
– 5 V or 3.3 V to 1.8 V
• Inputs accept voltages to 5.5 V
– 5.5-V tolerance on input pin when VCC = 0 V
• Ioff feature
– Allows voltage on the inputs and outputs when VCC is 0 V
– Able to reduce leakage when VCC is 0 V

9.4 Device Functional Modes

Table 1. Function Table

INPUTS OUTPUT
OE A Y
H H H
H L L
L X Z

10 Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated

Product Folder Links: SN74LVC1G126

 SN74LVC1G126
www.ti.com SCES224R – APRIL 1999 – REVISED JANUARY 2015

10 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

10.1 Application Information

The SN74LVC1G126 device is a high-drive CMOS device that can be used as an output enabled buffer with a
high output drive, such as an LED application. It can produce 24 mA of drive current at 3.3 V, making it ideal for
driving multiple outputs and good for high speed applications up to 100 MHz. The inputs are 5.5-V tolerant
allowing it to translate down to VCC.

10.2 Typical Application

1.65 V to 5 V

SN74LVC1G126
0.1 PF
OE VCC
Input signal 1
from system A
Output 1 to long
GND Y PCB trace or
high-Z logic input
Figure 5. Application Schematic

10.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. Outputs can be combined to
produce higher drive but the high drive will also create faster edges into light loads, so routing and load
conditions should be considered to prevent ringing.

10.2.2 Detailed Design Procedure

1. Recommended Input Conditions:
– For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table.
– For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions:
– Load currents should not exceed 50 mA per output and 100 mA total for the part.

Copyright © 1999–2015, Texas Instruments Incorporated Submit Documentation Feedback 11

Product Folder Links: SN74LVC1G126
SN74LVC1G126
SCES224R – APRIL 1999 – REVISED JANUARY 2015 www.ti.com

Typical Application (continued)

10.2.3 Application Curves

10
VCC 1.8 V
9 VCC 2.5 V
8 VCC 3.3 V
VCC 5V
7
6

ICC (mA) 5
4
3
2
1
0
0 20 40 60 80
Frequency (MHz) D003

Figure 6. ICC vs Frequency

11 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF capacitor is recommended. If there are multiple VCC terminals, then 0.01-μF or 0.022-μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of
noise. The bypass capacitor should be installed as close to the power terminal as possible for the best results.

12 Layout

12.1 Layout Guidelines

When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when
asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.

12.2 Layout Example

Vcc
Input

Unused Input Output Output

Unused Input

Input

Figure 7. Layout Diagram

12 Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated

Product Folder Links: SN74LVC1G126

 SN74LVC1G126
www.ti.com SCES224R – APRIL 1999 – REVISED JANUARY 2015

13 Device and Documentation Support

13.1 Trademarks
NanoFree is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.

13.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.

Copyright © 1999–2015, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Links: SN74LVC1G126
 PACKAGE OPTION ADDENDUM

www.ti.com 4-Jun-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

74LVC1G126DBVRE4 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 C26F
74LVC1G126DBVRG4 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 C26F
74LVC1G126DBVRG4.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 C26F
74LVC1G126DBVRG4.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 C26F
74LVC1G126DBVTE4 Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 C26F
74LVC1G126DBVTG4 Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 C26F
74LVC1G126DBVTG4.B Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 C26F
74LVC1G126DCKRE4 Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CN5
74LVC1G126DCKRG4 Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CN5
74LVC1G126DCKRG4.A Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CN5
74LVC1G126DCKRG4.B Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CN5
74LVC1G126DCKTG4 Active Production SC70 (DCK) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CN5
74LVC1G126DCKTG4.B Active Production SC70 (DCK) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CN5
SN74LVC1G126DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN | NIPDAU Level-1-260C-UNLIM -40 to 125 (C265, C26F, C26J,
C26K, C26R, C
26T)
SN74LVC1G126DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (C265, C26F, C26J,
C26K, C26R, C
26T)
SN74LVC1G126DBVR.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (C265, C26F, C26J,
C26K, C26R, C
26T)
SN74LVC1G126DBVRG4.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 C26J
SN74LVC1G126DBVRG4.B Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 C26J
SN74LVC1G126DBVT Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU | SN | NIPDAU Level-1-260C-UNLIM -40 to 125 (C265, C26F, C26J,
C26K, C26R)
SN74LVC1G126DBVT.B Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 (C265, C26F, C26J,
C26K, C26R)
SN74LVC1G126DCKR Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes NIPDAU | SN | NIPDAU Level-1-260C-UNLIM -40 to 125 (CN5, CNF, CNJ, CN
K, CNR, CNT)
SN74LVC1G126DCKR.A Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 (CN5, CNF, CNJ, CN
K, CNR, CNT)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 4-Jun-2025

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

SN74LVC1G126DCKR.B Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 (CN5, CNF, CNJ, CN
K, CNR, CNT)
SN74LVC1G126DCKT Active Production SC70 (DCK) | 5 250 | SMALL T&R Yes NIPDAU | SN | NIPDAU Level-1-260C-UNLIM -40 to 125 (CN5, CNF, CNJ, CN
K, CNR)
SN74LVC1G126DCKT.B Active Production SC70 (DCK) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (CN5, CNF, CNJ, CN
K, CNR)
SN74LVC1G126DCKTG4.B Active Production SC70 (DCK) | 5 250 | SMALL T&R - Call TI Call TI -40 to 125
SN74LVC1G126DRLR Active Production SOT-5X3 (DRL) | 5 4000 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 (CN7, CNR)
SN74LVC1G126DRLR.A Active Production SOT-5X3 (DRL) | 5 4000 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 (CN7, CNR)
SN74LVC1G126DRLR.B Active Production SOT-5X3 (DRL) | 5 4000 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 (CN7, CNR)
SN74LVC1G126DRYR Active Production SON (DRY) | 6 5000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CN
SN74LVC1G126DRYR.B Active Production SON (DRY) | 6 5000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CN
SN74LVC1G126DRYRG4.B Active Production SON (DRY) | 6 5000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CN
SN74LVC1G126DSFR Active Production SON (DSF) | 6 5000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CN
SN74LVC1G126DSFR.B Active Production SON (DSF) | 6 5000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CN
SN74LVC1G126DSFRG4.B Active Production SON (DSF) | 6 5000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CN
SN74LVC1G126YZPR Active Production DSBGA (YZP) | 5 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 (CN7, CNN)
SN74LVC1G126YZPR.B Active Production DSBGA (YZP) | 5 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 (CN7, CNN)

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 4-Jun-2025

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC1G126 :

• Automotive : SN74LVC1G126-Q1
• Enhanced Product : SN74LVC1G126-EP

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 23-May-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
74LVC1G126DBVRG4 SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
74LVC1G126DBVTG4 SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
74LVC1G126DCKRG4 SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
74LVC1G126DCKTG4 SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G126DBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
SN74LVC1G126DBVT SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
SN74LVC1G126DBVT SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
SN74LVC1G126DCKR SC70 DCK 5 3000 180.0 8.4 2.3 2.5 1.2 4.0 8.0 Q3
SN74LVC1G126DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G126DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G126DCKT SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G126DCKT SC70 DCK 5 250 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3
SN74LVC1G126DRLR SOT-5X3 DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
SN74LVC1G126DRYR SON DRY 6 5000 180.0 9.5 1.2 1.65 0.7 4.0 8.0 Q1
SN74LVC1G126DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
SN74LVC1G126YZPR DSBGA YZP 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 23-May-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
74LVC1G126DBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0
74LVC1G126DBVTG4 SOT-23 DBV 5 250 180.0 180.0 18.0
74LVC1G126DCKRG4 SC70 DCK 5 3000 180.0 180.0 18.0
74LVC1G126DCKTG4 SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G126DBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
SN74LVC1G126DBVT SOT-23 DBV 5 250 210.0 185.0 35.0
SN74LVC1G126DBVT SOT-23 DBV 5 250 210.0 185.0 35.0
SN74LVC1G126DCKR SC70 DCK 5 3000 210.0 185.0 35.0
SN74LVC1G126DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74LVC1G126DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G126DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G126DCKT SC70 DCK 5 250 202.0 201.0 28.0
SN74LVC1G126DRLR SOT-5X3 DRL 5 4000 202.0 201.0 28.0
SN74LVC1G126DRYR SON DRY 6 5000 189.0 185.0 36.0
SN74LVC1G126DSFR SON DSF 6 5000 184.0 184.0 19.0
SN74LVC1G126YZPR DSBGA YZP 5 3000 220.0 220.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
YZP0005 SCALE 8.000
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

B E A

BALL A1
CORNER

C
0.5 MAX

SEATING PLANE
0.19
0.15 0.05 C
BALL TYP

0.5 TYP

SYMM
1
TYP
B D: Max = 1.44 mm, Min = 1.38 mm
0.5
TYP E: Max = 0.94 mm, Min = 0.88 mm
A

0.25
5X 1 2
0.21
0.015 C A B
SYMM

4219492/A 05/2017
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
YZP0005 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP
5X ( 0.23)
1 2

(0.5) TYP

SYMM
B

SYMM

LAND PATTERN EXAMPLE

SCALE:40X

SOLDER MASK 0.05 MAX 0.05 MIN ( 0.23)

OPENING SOLDER MASK
OPENING

( 0.23)
METAL METAL UNDER
SOLDER MASK
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4219492/A 05/2017

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com
 EXAMPLE STENCIL DESIGN
YZP0005 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP

5X ( 0.25)
(R0.05) TYP
1 2

(0.5)
TYP

B SYMM

METAL SYMM
TYP

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:40X

4219492/A 05/2017

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com
 PACKAGE OUTLINE
DCK0005A SCALE 5.600
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

C
2.4
1.8 0.1 C
1.4
B A 1.1 MAX
PIN 1 1.1
INDEX AREA

1 5

2X 0.65 NOTE 4

2.15
1.3 (0.15) 1.3
2 1.85

(0.1)

4
0.33 3
5X
0.15
0.1 C A B 4X 0 -12 0.1
(0.9) TYP
NOTE 5 0.0

4X 4 -15

0.15
GAGE PLANE 0.22
TYP
0.08

8 0.46
TYP TYP
0 0.26
SEATING PLANE

4214834/G 11/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
5. Lead width does not comply with JEDEC.
6. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.25mm per side

www.ti.com
 EXAMPLE BOARD LAYOUT
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
5X (0.95)

1
5
5X (0.4)

SYMM
(1.3)
2
2X (0.65)

3 4

(R0.05) TYP (2.2)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:18X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214834/G 11/2024

NOTES: (continued)

7. Publication IPC-7351 may have alternate designs.

8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
5X (0.95)
1
5
5X (0.4)

SYMM
(1.3)
2
2X(0.65)

3 4

(R0.05) TYP
(2.2)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL
SCALE:18X

4214834/G 11/2024

NOTES: (continued)

9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
10. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1 5

2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)

4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 4X 0 -15 (1.1) TYP
0.00
1.45
0.90
4X 4 -15

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/K 08/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/K 08/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/K 08/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 GENERIC PACKAGE VIEW
DRY 6 USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4207181/G
 PACKAGE OUTLINE
DRY0006B SCALE 8.500
USON - 0.55 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

1.05 A
B
0.95

PIN 1 INDEX AREA

1.5
1.4

0.55 MAX C

SEATING PLANE
0.05
0.00 0.08 C

3X 0.6
SYMM
(0.127) TYP
(0.05) TYP

3
4
4X
0.5
SYMM
2X
1

6
1
0.25
6X
0.15
PIN 1 ID 0.1 C A B
(OPTIONAL)
0.05 C
0.35
6X
0.25
4222207/B 02/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
DRY0006B USON - 0.55 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

SYMM
6X (0.3)
1

6X (0.2)

SYMM

4X (0.5)

4
3

(R0.05) TYP
(0.6)

LAND PATTERN EXAMPLE

1:1 RATIO WITH PKG SOLDER PADS
SCALE:40X

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
DEFINED SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4222207/B 02/2016
NOTES: (continued)

3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).

www.ti.com
 EXAMPLE STENCIL DESIGN
DRY0006B USON - 0.55 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

SYMM
6X (0.3)
1

6X (0.2)

SYMM

4X (0.5)

4
3

(R0.05) TYP (0.6)

SOLDER PASTE EXAMPLE

BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X

4222207/B 02/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
DSF0006A SCALE 10.000
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

1.05
B A
0.95

PIN 1 INDEX AREA

1.05
0.95

0.4 MAX C

SEATING PLANE

0.05 C

(0.11) TYP
SYMM 0.05
0.00

3
4

2X SYMM
0.7
4X
0.35
6
1
0.22
6X
0.12
(0.1)
PIN 1 ID 0.45 0.07 C B A
6X
0.35 0.05 C

4220597/B 06/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MO-287, variation X2AAF.

www.ti.com
 EXAMPLE BOARD LAYOUT
DSF0006A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

6X (0.6)
(R0.05) TYP
1
6X (0.17) 6

SYMM

4X (0.35)

4
3

SYMM

(0.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:40X

0.07 MIN
0.07 MAX EXPOSED METAL ALL AROUND
ALL AROUND

EXPOSED METAL

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220597/B 06/2022

NOTES: (continued)

4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com
 EXAMPLE STENCIL DESIGN
DSF0006A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

6X (0.6)
(R0.05) TYP
1
6X (0.15) 6

SYMM

4X (0.35)

4
3

SYMM

(0.8)

SOLDER PASTE EXAMPLE

BASED ON 0.09 mm THICK STENCIL

PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:40X

4220597/B 06/2022

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
DRL0005A SCALE 8.000
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

1.7
1.5
PIN 1 A
ID AREA

1
5

2X 0.5

1.7
2X 1
1.5
NOTE 3

4 2X 0 -10
3

1.3 0.3 0.05

B 5X TYP
1.1 0.1 0.00

2X 4 -15

0.6 MAX C

SEATING PLANE
0.18
5X 0.05 C
0.08
SYMM

SYMM

0.27
5X
0.15
0.4 0.1 C A B
5X
0.2 0.05 C
4220753/E 11/2024
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD-1

www.ti.com
 EXAMPLE BOARD LAYOUT
DRL0005A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

5X (0.67) SYMM
1
5
5X (0.3)

SYMM
(1)

2X (0.5)

3 4

(R0.05) TYP
(1.48)

LAND PATTERN EXAMPLE

SCALE:30X

0.05 MAX 0.05 MIN

AROUND AROUND

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDERMASK DETAILS

4220753/E 11/2024

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DRL0005A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

5X (0.67)
SYMM
1
5
5X (0.3)

SYMM
(1)

2X (0.5)

3 4

(R0.05) TYP
(1.48)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:30X

4220753/E 11/2024

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2025, Texas Instruments Incorporated