SN74LVC1G00

www.ti.com SCES212V – APRIL 1999 – REVISED FEBRUARY 2010

SINGLE 2-INPUT POSITIVE-NAND GATE

Check for Samples: SN74LVC1G00

1FEATURES
• Available in the Texas Instruments NanoStar™ • Ioff Supports Partial-Power-Down Mode
Package Operation
• Supports 5-V VCC Operation • Latch-Up Performance Exceeds 100 mA Per
• Inputs Accept Voltages to 5.5 V JESD 78, Class II
• Max tpd of 3.8 ns at 3.3 V • ESD Protection Exceeds JESD 22
• Low Power Consumption, 10-mA Max ICC – 2000-V Human-Body Model (A114-A)
• ±24-mA Output Drive at 3.3 V – 1000-V Charged-Device Model (C101)

DBV PACKAGE DCK PACKAGE DRL PACKAGE YZP PACKAGE

(TOP VIEW) (TOP VIEW) (TOP VIEW) (BOTTOM VIEW)

A 1 5 VCC A 1 5 VCC GND 3 4 Y

A 1 5 VCC
B 2 B 2

B 2
VCC
A 1 5
GND 3 4 Y
B 2
GND 3 4 Y

GND 3 4 Y

See mechanical drawings for dimensions.

DESCRIPTION/ORDERING INFORMATION
This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G00 performs the Boolean function Y = A ● B or Y = A + B in positive logic.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION (1)

(2)
TA PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING (3)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP SN74LVC1G00YZPR _ _ _ CA_
(Pb-free)
Reel of 3000 SN74LVC1G00DBVR
SOT (SOT-23) – DBV C00_
–40°C to 85°C Reel of 250 SN74LVC1G00DBVT
Reel of 3000 SN74LVC1G00DCKR
SOT (SC-70) – DCK
Reel of 250 SN74LVC1G00DCKT CA_
SOT (SOT-553) – DRL Reel of 4000 SN74LVC1G00DRLR

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ● = Pb-free).
1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 1999–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVC1G00
SCES212V – APRIL 1999 – REVISED FEBRUARY 2010 www.ti.com

FUNCTION TABLE
INPUTS OUTPUT
A B Y
H H L
L X H
X L H

LOGIC DIAGRAM (POSITIVE LOGIC)

ABSOLUTE MAXIMUM RATINGS (1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 V
VI Input voltage range –0.5 6.5 V
VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V
VO Voltage range applied to any output in the high or low state (2) (3)
–0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
DBV package 206
DCK package 252
qJA Package thermal impedance (4) °C/W
DRL package 142
YZP package 132
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.

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 SN74LVC1G00
www.ti.com SCES212V – APRIL 1999 – REVISED FEBRUARY 2010

RECOMMENDED OPERATING CONDITIONS (1)

MIN MAX UNIT
Operating 1.65 5.5
VCC Supply voltage V
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC
VCC = 2.3 V to 2.7 V 1.7
VIH High-level input voltage V
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × VCC
VCC = 1.65 V to 1.95 V 0.35 × VCC
VCC = 2.3 V to 2.7 V 0.7
VIL Low-level input voltage V
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × VCC
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current –16 mA
VCC = 3 V
–24
VCC = 4.5 V –32
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current 16 mA
VCC = 3 V
24
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
Δt/Δv Input transition rise or fall rate VCC = 3.3 V ± 0.3 V 10 ns/V
VCC = 5 V ± 0.5 V 5
TA Operating free-air temperature –40 85 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

Copyright © 1999–2010, Texas Instruments Incorporated Submit Documentation Feedback 3

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SN74LVC1G00
SCES212V – APRIL 1999 – REVISED FEBRUARY 2010 www.ti.com

ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP (1) MAX UNIT
IOH = –100 mA 1.65 V to 5.5 V VCC – 0.1
IOH = –4 mA 1.65 V 1.2
IOH = –8 mA 2.3 V 1.9
VOH V
IOH = –16 mA 2.4
3V
IOH = –24 mA 2.3
IOH = –32 mA 4.5 V 3.8
IOL = 100 mA 1.65 V to 5.5 V 0.1
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.3
VOL V
IOL = 16 mA 0.4
3V
IOL = 24 mA 0.55
IOL = 32 mA 4.5 V 0.55
A or B
II VI = 5.5 V or GND 0 to 5.5 V ±5 mA
inputs
Ioff VI or VO = 5.5 V 0 ±10 mA
ICC VI = 5.5 V or GND IO = 0 1.65 V to 5.5 V 10 mA
ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500 mA
Ci VI = VCC or GND 3.3 V 4 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1)
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
FROM TO ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
PARAMETER UNIT
(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A or B Y 2.2 7.2 0.9 4.4 0.8 3.8 0.8 3.4 ns

SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2)
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
FROM TO ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
PARAMETER UNIT
(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A or B Y 3.1 9 1.3 5.5 1 4.7 1 4 ns

OPERATING CHARACTERISTICS
TA = 25°C
TEST VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
CONDITIONS TYP TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 22 22 23 25 pF

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 SN74LVC1G00
www.ti.com SCES212V – APRIL 1999 – REVISED FEBRUARY 2010

PARAMETER MEASUREMENT INFORMATION

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
(see Note A) RL tPLZ/tPZL VLOAD
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL VD
VI tr/tf
1.8 V ± 0.15 V VCC £2 ns VCC/2 2 × VCC 15 pF 1 MW 0.15 V
2.5 V ± 0.2 V VCC £2 ns VCC/2 2 × VCC 15 pF 1 MW 0.15 V
3.3 V ± 0.3 V 3V £2.5 ns 1.5 V 6V 15 pF 1 MW 0.3 V
5 V ± 0.5 V VCC £2.5 ns VCC/2 2 × VCC 15 pF 1 MW 0.3 V

VI
Timing Input VM
0V
tW

VI tsu th
VI
Input VM VM Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
VOH Output VLOAD/2
VM VM Waveform 1
Output VM
S1 at VLOAD VOL + VD
VOL VOL
(see Note B)
tPHL tPLH tPZH tPHZ
VOH Output VOH
Waveform 2 VOH – VD
Output VM VM VM
VOL S1 at GND
(see Note B) »0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

Copyright © 1999–2010, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Link(s): SN74LVC1G00
SN74LVC1G00
SCES212V – APRIL 1999 – REVISED FEBRUARY 2010 www.ti.com

PARAMETER MEASUREMENT INFORMATION (continued)

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
(see Note A) RL tPLZ/tPZL VLOAD
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL VD
VI tr/tf
1.8 V ± 0.15 V VCC £2 ns VCC/2 2 × VCC 30 pF 1 kW 0.15 V
2.5 V ± 0.2 V VCC £2 ns VCC/2 2 × VCC 30 pF 500 W 0.15 V
3.3 V ± 0.3 V 3V £2.5 ns 1.5 V 6V 50 pF 500 W 0.3 V
5 V ± 0.5 V VCC £2.5 ns VCC/2 2 × VCC 50 pF 500 W 0.3 V

VI
Timing Input VM
0V
tW

VI tsu th
VI
Input VM VM Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
VOH Output VLOAD/2
VM VM Waveform 1
Output VM
S1 at VLOAD VOL + VD
VOL VOL
(see Note B)
tPHL tPLH tPZH tPHZ
VOH Output VOH
Waveform 2 VOH – VD
Output VM VM VM
VOL S1 at GND
(see Note B) »0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 2. Load Circuit and Voltage Waveforms

6 Submit Documentation Feedback Copyright © 1999–2010, Texas Instruments Incorporated

Product Folder Link(s): SN74LVC1G00

 PACKAGE OPTION ADDENDUM

www.ti.com 4-Feb-2010

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
SN74LVC1G00DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC1G00DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC1G00DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC1G00DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC1G00DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC1G00DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC1G00DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC1G00DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC1G00DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC1G00DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC1G00DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC1G00DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC1G00DRLR ACTIVE SOT DRL 5 4000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC1G00DRLRG4 ACTIVE SOT DRL 5 4000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC1G00YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS & SNAGCU Level-1-260C-UNLIM
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 4-Feb-2010

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC1G00 :

• Enhanced Product: SN74LVC1G00-EP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 11-Aug-2010

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC1G00DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G00DBVR SOT-23 DBV 5 3000 180.0 9.2 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G00DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G00DBVT SOT-23 DBV 5 250 180.0 9.2 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G00DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G00DCKT SC70 DCK 5 250 180.0 9.2 2.24 2.34 1.22 4.0 8.0 Q3
SN74LVC1G00DRLR SOT DRL 5 4000 180.0 9.2 1.78 1.78 0.69 4.0 8.0 Q3
SN74LVC1G00YZPR DSBGA YZP 5 3000 180.0 8.4 1.02 1.52 0.63 4.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 11-Aug-2010

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G00DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LVC1G00DBVR SOT-23 DBV 5 3000 205.0 200.0 33.0
SN74LVC1G00DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74LVC1G00DBVT SOT-23 DBV 5 250 205.0 200.0 33.0
SN74LVC1G00DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G00DCKT SC70 DCK 5 250 205.0 200.0 33.0
SN74LVC1G00DRLR SOT DRL 5 4000 202.0 201.0 28.0
SN74LVC1G00YZPR DSBGA YZP 5 3000 220.0 220.0 34.0

Pack Materials-Page 2
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