SN54LVC32A, SN74LVC32A

QUADRUPLE 2-INPUT POSITIVE-OR GATES

www.ti.com SCAS286P – JANUARY 1993 – REVISED APRIL 2005

FEATURES • Typical VOHV (Output VOH Undershoot)

• Operate From 1.65 V to 3.6 V >2 V at VCC = 3.3 V, TA = 25°C
• Specified From –40°C to 85°C, • Latch-Up Performance Exceeds 250 mA Per
–40°C to 125°C, and –55°C to 125°C JESD 17
• Inputs Accept Voltages to 5.5 V • ESD Protection Exceeds JESD 22
• Max tpd of 3.8 ns at 3.3 V – 2000-V Human-Body Model (A114-A)
• Typical VOLP (Output Ground Bounce) – 200-V Machine Model (A115-A)
<0.8 V at VCC = 3.3 V, TA = 25°C – 1000-V Charged-Device Model (C101)
SN54LVC32A . . . J OR W PACKAGE SN74LVC32A . . . RGY PACKAGE SN54LVC32A . . . FK PACKAGE
SN74LVC32A . . . D, DB, NS, (TOP VIEW) (TOP VIEW)
OR PW PACKAGE

VCC
VCC

NC
1B
1A

4B
(TOP VIEW)

1A
1A 1 14 VCC 1 14 3 2 1 20 19
1B 13 4B
1Y 4 18 4A
1B 2 13 4B 2
1Y 12 4A NC 5 17 NC
1Y 3 12 4A 3
2A 6 16 4Y
2A 4 11 4Y 2A 4 11 4Y
NC 7 15 NC
2B 5 10 3B 2B 5 10 3B
2B 8 14 3B
2Y 6 9 3A 2Y 6 9 3A 9 10 11 12 13
GND 7 8 3Y 7 8

GND
NC
2Y

3Y
3A
GND

3Y

NC - No internal connection

DESCRIPTION/ORDERING INFORMATION
The SN54LVC32A quadruple 2-input positive-OR gate is designed for 2.7-V to 3.6-V VCC operation, and the
SN74LVC32A quadruple 2-input positive-OR gate is designed for 1.65-V to 3.6-V VCC operation.
The 'LVC32A devices perform the Boolean function Y  A
B or Y  A • B in positive logic.

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE (1)
PART NUMBER MARKING
–40°C to 85°C QFN – RGY Reel of 1000 SN74LVC32ARGYR LC32A
Tube of 50 SN74LVC32AD
SOIC – D Reel of 2500 SN74LVC32ADR LVC32A
Reel of 250 SN74LVC32ADT
SOP – NS Reel of 2000 SN74LVC32ANSR LVC32A
–40°C to 125°C
SSOP – DB Reel of 2000 SN74LVC32ADBR LC32A
Tube of 90 SN74LVC32APW
TSSOP – PW Reel of 2000 SN74LVC32APWR LC32A
Reel of 250 SN74LVC32APWT
CDIP – J Tube of 25 SNJ54LVC32AJ SNJ54LVC32AJ
–55°C to 125°C CFP – W Tube of 150 SNJ54LVC32AW SNJ54LVC32AW
LCCC – FK Tube of 55 SNJ54LVC32AFK SNJ54LVC32AFK

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 1993–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas On products compliant to MIL-PRF-38535, all parameters are
Instruments standard warranty. Production processing does not tested unless otherwise noted. On all other products, production
necessarily include testing of all parameters. processing does not necessarily include testing of all parameters.
SN54LVC32A, SN74LVC32A
QUADRUPLE 2-INPUT POSITIVE-OR GATES www.ti.com
SCAS286P – JANUARY 1993 – REVISED APRIL 2005

DESCRIPTION/ORDERING INFORMATION (CONTINUED)

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.

FUNCTION TABLE
(EACH GATE)
INPUTS OUTPUT
A B Y
H X H
X H H
L L L

LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)

A
Y
B

Absolute Maximum Ratings (1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 V
VI Input voltage range (2) –0.5 6.5 V
VO Output voltage range (2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
D package (4) 86
DB package (4) 96
θJA Package thermal impedance NS package (4) 76 °C/W
PW package (4) 113
RGY package (5) 47
Tstg Storage temperature range –65 150 °C
Ptot Power dissipation TA = –40°C to 125°C (6) (7) 500 mW

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) The package thermal impedance is calculated in accordance with JESD 51-5.
(6) For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K.
(7) For the DB, DGV, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5 mW/K.

2
 SN54LVC32A, SN74LVC32A
www.ti.com
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCAS286P – JANUARY 1993 – REVISED APRIL 2005
(1)
Recommended Operating Conditions
SN54LVC32A
–55 TO 125°C UNIT
MIN MAX
Operating 2 3.6
VCC Supply voltage V
Data retention only 1.5
VIH High-level input voltage VCC = 2.7 V to 3.6 V 2 V
VIL Low-level input voltage VCC = 2.7 V to 3.6 V 0.8 V
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 2.7 V –12
IOH High-level output current mA
VCC = 3 V –24
VCC = 2.7 V 12
IOL Low-level output current mA
VCC = 3 V 24
∆t/∆v Input transition rise or fall rate 7 ns/V

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

Recommended Operating Conditions (1)

SN74LVC32A
TA = 25°C –40 TO 85°C –40 TO 125°C UNIT
MIN MAX MIN MAX MIN MAX
Operating 1.65 3.6 1.65 3.6 1.65 3.6
VCC Supply voltage V
Data retention only 1.5 1.5 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC 0.65 × VCC 0.65 × VCC
High-level input
VIH VCC = 2.3 V to 2.7 V 1.7 1.7 1.7 V
voltage
VCC = 2.7 V to 3.6 V 2 2 2
VCC = 1.65 V to 1.95 V 0.35 × VCC 0.35 × VCC 0.35 × VCC
Low-level input
VIL VCC = 2.3 V to 2.7 V 0.7 0.7 0.7 V
voltage
VCC = 2.7 V to 3.6 V 0.8 0.8 0.8
VI Input voltage 0 5.5 0 5.5 0 5.5 V
VO Output voltage 0 VCC 0 VCC 0 VCC V
VCC = 1.65 V –4 –4 –4
High-level output VCC = 2.3 V –8 –8 –8
IOH mA
current VCC = 2.7 V –12 –12 –12
VCC = 3 V –24 –24 –24
VCC = 1.65 V 4 4 4
Low-level output VCC = 2.3 V 8 8 8
IOL mA
current VCC = 2.7 V 12 12 12
VCC = 3 V 24 24 24
∆t/∆v Input transition rise or fall rate 7 7 7 ns/V

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

3
SN54LVC32A, SN74LVC32A
QUADRUPLE 2-INPUT POSITIVE-OR GATES www.ti.com
SCAS286P – JANUARY 1993 – REVISED APRIL 2005

Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
SN54LVC32A
PARAMETER TEST CONDITIONS VCC –55 TO 125°C UNIT
MIN MAX
IOH = –100 µA 2.7 V to 3.6 V VCC – 0.2
2.7 V 2.2
VOH IOH = –12 mA V
3V 2.4
IOH = –24 mA 3V 2.2
IOL = 100 µA 2.7 V to 3.6 V 0.2
VOL IOL = 12 mA 2.7 V 0.4 V
IOL = 24 mA 3V 0.55
II VI = 5.5 V or GND 3.6 V ±5 µA
ICC VI = VCC or GND, IO = 0 3.6 V 10 µA
∆ICC One input at VCC – 0.6 V, Other inputs at VCC or GND 2.7 V to 3.6 V 500 µA

Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
SN74LVC32A
PARAMETER TEST CONDITIONS VCC TA = 25°C –40 TO 85°C –40 TO 125°C UNIT
MIN TYP MAX MIN MAX MIN MAX
IOH = –100 µA 1.65 V to 3.6 V VCC – 0.2 VCC – 0.2 VCC – 0.3
IOH = –4 mA 1.65 V 1.29 1.2 1.05
IOH = –8 mA 2.3 V 1.9 1.7 1.55
VOH V
2.7 V 2.2 2.2 2.05
IOH = –12 mA
3V 2.4 2.4 2.25
IOH = –24 mA 3V 2.3 2.2 2
IOL = 100 µA 1.65 V to 3.6 V 0.1 0.2 0.3
IOL = 4 mA 1.65 V 0.24 0.45 0.6
VOL IOL = 8 mA 2.3 V 0.3 0.7 0.85 V
IOL = 12 mA 2.7 V 0.4 0.4 0.6
IOL = 24 mA 3V 0.55 0.55 0.8
II VI = 5.5 V or GND 3.6 V ±1 ±5 ±20 µA
ICC VI = VCC or GND, IO = 0 3.6 V 1 10 40 µA
One input at VCC – 0.6 V,
∆ICC Other inputs at VCC or 2.7 V to 3.6 V 500 500 5000 µA
GND
Ci VI = VCC or GND 3.3 V 5 pF

Switching Characteristics
over operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN54LVC32A
FROM TO
PARAMETER VCC –55 TO 125°C UNIT
(INPUT) (OUTPUT)
MIN MAX
2.7 V 4.4
tpd A or B Y ns
3.3 V ± 0.3 V 1 3.8

4
 SN54LVC32A, SN74LVC32A
www.ti.com
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCAS286P – JANUARY 1993 – REVISED APRIL 2005

Switching Characteristics
over operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN74LVC32A
FROM TO
PARAMETER VCC TA = 25°C –40 TO 85°C –40 TO 125°C UNIT
(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
1.8 V ± 0.15 V 1 4.2 8.2 1 8.7 1 10.2
2.5 V ± 0.2 V 1 2.6 4.9 1 5.4 1 6.9
tpd A or B Y ns
2.7 V 1 3 4.2 1 4.4 1 5.5
3.3 V ± 0.3 V 1 2.5 3.6 1 3.8 1 5
tsk(o) 3.3 V ± 0.3 V 1 1.5 ns

Operating Characteristics
TA = 25°C
TEST
PARAMETER VCC TYP UNIT
CONDITIONS
1.8 V 7.5
Cpd Power dissipation capacitance per gate f = 10 MHz 2.5 V 10.6 pF
3.3 V 12.5

5
SN54LVC32A, SN74LVC32A
QUADRUPLE 2-INPUT POSITIVE-OR GATES www.ti.com
SCAS286P – JANUARY 1993 – REVISED APRIL 2005

PARAMETER MEASUREMENT INFORMATION

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
RL tPLZ/tPZL VLOAD
(see Note A)
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL V∆
VI tr/tf
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V
2.7 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V
3.3 V ± 0.3 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V

VI
Timing Input VM
0V
tw

VI tsu th
VI
Input VM VM
Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
Output
VOH VLOAD/2
Waveform 1
Output VM VM VM
S1 at VLOAD VOL + V∆
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
VOH Output
VOH
VM VM Waveform 2 VOH - V∆
Output VM
S1 at GND
VOL
(see Note B) ≈0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

6
 PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2007

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
5962-9761801Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-9761801QCA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
5962-9761801QDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
SN74LVC32AD ACTIVE SOIC D 14 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC32ADBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI
SN74LVC32ADBR ACTIVE SSOP DB 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC32ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC32ADE4 ACTIVE SOIC D 14 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC32ADR ACTIVE SOIC D 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC32ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC32ADT ACTIVE SOIC D 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC32ADTE4 ACTIVE SOIC D 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC32ANSR ACTIVE SO NS 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC32ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC32ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC32APW ACTIVE TSSOP PW 14 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC32APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC32APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC32APWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI
SN74LVC32APWR ACTIVE TSSOP PW 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC32APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC32APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC32APWT ACTIVE TSSOP PW 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC32APWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC32APWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC32ARGYR ACTIVE QFN RGY 14 1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
SN74LVC32ARGYRG4 ACTIVE QFN RGY 14 1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2007

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
SNJ54LVC32AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54LVC32AJ ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
SNJ54LVC32AW ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 2
 MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

NO. OF A B
18 17 16 15 14 13 12
TERMINALS
** MIN MAX MIN MAX

0.342 0.358 0.307 0.358

19 11 20
(8,69) (9,09) (7,80) (9,09)
20 10 0.442 0.458 0.406 0.458
28
(11,23) (11,63) (10,31) (11,63)
21 9
B SQ 0.640 0.660 0.495 0.560
22 8 44
(16,26) (16,76) (12,58) (14,22)
A SQ
23 7 0.739 0.761 0.495 0.560
52
(18,78) (19,32) (12,58) (14,22)
24 6
0.938 0.962 0.850 0.858
68
(23,83) (24,43) (21,6) (21,8)
25 5
1.141 1.165 1.047 1.063
84
(28,99) (29,59) (26,6) (27,0)
26 27 28 1 2 3 4

0.020 (0,51) 0.080 (2,03)

0.010 (0,25) 0.064 (1,63)

0.020 (0,51)
0.010 (0,25)

0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)

0.028 (0,71) 0.045 (1,14)

0.022 (0,54) 0.035 (0,89)
0.050 (1,27)

4040140 / D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30
0,65 0,10 M
0,19
14 8

0,15 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25
1 7
0°– 8°
A 0,75
0,50

Seating Plane

1,20 MAX 0,15 0,10

0,05

PINS **
8 14 16 20 24 28
DIM

A MAX 3,10 5,10 5,10 6,60 7,90 9,80

A MIN 2,90 4,90 4,90 6,40 7,70 9,60

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to
discontinue any product or service without notice. Customers should obtain the latest relevant information
before placing orders and should verify that such information is current and complete. All products are sold
subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent
TI deems necessary to support this warranty. Except where mandated by government requirements, testing
of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible
for their products and applications using TI components. To minimize the risks associated with customer
products and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent
right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine,
or process in which TI products or services are used. Information published by TI regarding third-party
products or services does not constitute a license from TI to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or
other intellectual property of the third party, or a license from TI under the patents or other intellectual
property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices.
Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not
responsible or liable for such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for
that product or service voids all express and any implied warranties for the associated TI product or service
and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:

Products Applications
Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive
DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security
Low Power Wireless www.ti.com/lpw Telephony www.ti.com/telephony
Video & Imaging www.ti.com/video
Wireless www.ti.com/wireless

Mailing Address: Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

Copyright © 2007, Texas Instruments Incorporated