SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003

D 2-V to 6-V VCC Operation SN54AC74 . . . J OR W PACKAGE

SN74AC74 . . . D, DB, N, NS, OR PW PACKAGE
D Inputs Accept Voltages to 6 V (TOP VIEW)
D Max tpd of 10 ns at 5 V
1CLR 1 14 VCC
description/ordering information 1D 2 13 2CLR
1CLK 3 12 2D
The ’AC74 devices are dual positive-edge-
1PRE 4 11 2CLK
triggered D-type flip-flops.
1Q 5 10 2PRE
A low level at the preset (PRE) or clear (CLR) input 1Q 6 9 2Q
sets or resets the outputs, regardless of the levels GND 7 8 2Q
of the other inputs. When PRE and CLR are
inactive (high), data at the data (D) input meeting
the setup-time requirements is transferred to the SN54AC74 . . . FK PACKAGE
(TOP VIEW)
outputs on the positive-going edge of the clock

1CLR

2CLR
pulse. Clock triggering occurs at a voltage level

VCC
NC
1D
and is not directly related to the rise time of the
clock pulse. Following the hold-time interval, data
at D can be changed without affecting the levels 3 2 1 20 19
1CLK 4 18 2D
at the outputs. NC NC
5 17
1PRE 6 16 2CLK
NC 7 15 NC
1Q 8 14 2PRE
9 10 11 12 13

1Q
GND

2Q
2Q
NC
NC − No internal connection

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
PDIP − N Tube SN74AC74N SN74AC74N
Tube SN74AC74D
SOIC − D AC74
Tape and reel SN74AC74DR
−40°C
−40 85°C
C to 85 C SOP − NS Tape and reel SN74AC74NSR AC74
SSOP − DB Tape and reel SN74AC74DBR AC74
Tube SN74AC74PW
TSSOP − PW AC74
Tape and reel SN74AC74PWR
CDIP − J Tube SNJ54AC74J SNJ54AC74J
−55°C
−55 125°C
C to 125 C CFP − W Tube SNJ54AC74W SNJ54AC74W
LCCC − FK Tube SNJ54AC74FK SNJ54AC74FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.


   ! " #$%! "  &$'(#! )!%* Copyright  2003, Texas Instruments Incorporated
)$#!" # ! "&%##!" &% !+% !%"  %," "!$%!"  &)$#!" #&(! ! 0121 (( &%!%" % !%"!%)
"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% $(%"" !+%-"% !%)*  (( !+% &)$#!" &)$#!
!%"!/  (( &%!%"* &#%""/ )%" ! %#%""(. #($)% !%"!/  (( &%!%"*

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1





 
    

   

SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003

FUNCTION TABLE
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
H L X X L H
L L X X H† H†
H H ↑ H H L
H H ↑ L L H
H H L X Q0 Q0
† This configuration is unstable; that is, it does not
persist when either PRE or CLR returns to its
inactive (high) level.

logic diagram, each flip-flop (positive logic)

PRE

CLK C C

C
Q
TG

C C C

D TG TG TG

Q
C C C
CLR

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265





 
    

   

SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN54AC74 SN74AC74
UNIT
MIN MAX MIN MAX
VCC Supply voltage 2 6 2 6 V
VCC = 3 V 2.1 2.1
VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V
VCC = 5.5 V 3.85 3.85
VCC = 3 V 0.9 0.9
VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 V
VCC = 5.5 V 1.65 1.65
VI Input voltage 0 VCC 0 VCC V
VO Output voltage 0 VCC 0 VCC V
VCC = 3 V −12 −12
IOH High-level output current VCC = 4.5 V −24 −24 mA
VCC = 5.5 V −24 −24
VCC = 3 V 12 12
IOL Low-level output current VCC = 4.5 V 24 24 mA
VCC = 5.5 V 24 24
∆t/∆v Input transition rise or fall rate 8 8 ns/V
TA Operating free-air temperature −55 125 −40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3





 
    

   

SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
TA = 25°C SN54AC74 SN74AC74
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
3V 2.9 4.49 2.9 2.9
IOH = −50 µA 4.5 V 4.4 5.49 4.4 4.4
5.5 V 5.4 5.49 5.4 5.4
IOH = −12 mA 3V 2.56 2.4 2.46
VOH V
4.5 V 3.86 3.7 3.76
IOH = −24 mA
5.5 V 4.86 4.7 4.76
IOH = −50 mA† 5.5 V 3.85
IOH = −75 mA† 5.5 V 3.85
3V 0.002 0.1 0.1 0.1
IOL = 50 µA 4.5 V 0.001 0.1 0.1 0.1
5.5 V 0.001 0.1 0.1 0.1
IOL = 12 mA 3V 0.36 0.5 0.44
VOL V
4.5 V 0.36 0.5 0.44
IOL = 24 mA
5.5 V 0.36 0.5 0.44
IOL = 50 mA† 5.5 V 1.65
IOL = 75 mA† 5.5 V 1.65
Data pins ±0.1 ±1 ±1
II VI = VCC or GND 5.5 V µA
A
Control pins ±0.1 ±1 ±1
ICC VI = VCC or GND, IO = 0 5.5 V 2 40 20 µA
Ci VI = VCC or GND 5V 3 pF
† Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.

timing requirements over recommended operating free-air temperature range,

VCC = 3.3 V " 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C SN54AC74 SN74AC74
UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency 100 70 95 MHz
PRE or CLR low 5.5 8 7
tw Pulse duration ns
CLK 5.5 8 7
Data 4 5 4.5
tsu Setup time, data before CLK↑ ns
PRE or CLR inactive 0 0.5 0
th Hold time, data after CLK↑ 0.5 0.5 0.5 ns

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265





 
    

   

SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003

timing requirements over recommended operating free-air temperature range,

VCC = 5 V"0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C SN54AC74 SN74AC74
UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency 140 95 125 MHz
PRE or CLR low 4.5 5.5 5
tw Pulse duration ns
CLK 4.5 5.5 5
Data 3 4 3
tsu Setup time, data before CLK↑ ns
PRE or CLR inactive 0 0.5 0
th Hold time, data after CLK↑ 0.5 0.5 0.5 ns

switching characteristics over recommended operating free-air temperature range,

VCC = 3.3 V " 0.3 V (unless otherwise noted) (see Figure 1)
FROM TO TA = 25°C SN54AC74 SN74AC74
PARAMETER UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
fmax 100 125 70 95 MHz
tPLH 3.5 8 12 1 13 2.5 13
PRE or CLR Q or Q ns
tPHL 4 10.5 12 1 14 3.5 13.5
tPLH 4.5 8 13.5 1 17.5 4 16
CLK Q or Q ns
tPHL 3.5 8 14 1 13.5 3.5 14.5

switching characteristics over recommended operating free-air temperature range,

VCC = 5 V " 0.5 V (unless otherwise noted) (see Figure 1)
FROM TO TA = 25°C SN54AC74 SN74AC74
PARAMETER UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
fmax 140 160 95 125 MHz
tPLH 2.5 6 9 1 9.5 2 10
PRE or CLR Q or Q ns
tPHL 3 8 9.5 1 10.5 2.5 10.5
tPLH 3.5 6 10 1 12 3 10.5
CLK Q or Q ns
tPHL 2.5 6 10 1 10 2.5 10.5

operating characteristics, VCC = 3.3 V, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance CL = 50 pF, f = 1 MHz 45 pF

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5





 
    

   

SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003

PARAMETER MEASUREMENT INFORMATION

2 × VCC
TEST S1
500 Ω S1
Open tPLH/tPHL Open
From Output
Under Test
CL = 50 pF 500 Ω
(see Note A)

LOAD CIRCUIT tw

VCC
Input 50% VCC 50% VCC
VCC
Input 50% VCC 50% VCC 0V
0V VOLTAGE WAVEFORMS
tPLH tPHL
VOH
In-Phase 50% VCC VCC
50% VCC
Output Timing Input 50% VCC
VOL
0V
tPHL tPLH th
tsu
VOH
Out-of-Phase VCC
50% VCC 50% VCC 50% VCC 50% VCC
Output Data Input
VOL 0V

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr v 2.5 ns, tf v 2.5 ns.
C. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
5962-88520012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-8852001CA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
5962-8852001DA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
5962-8852001VCA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
5962-8852001VDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
SN74AC74D ACTIVE SOIC D 14 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC74DBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI
SN74AC74DBR ACTIVE SSOP DB 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC74DBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC74DE4 ACTIVE SOIC D 14 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC74DG4 ACTIVE SOIC D 14 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC74DR ACTIVE SOIC D 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC74DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC74DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC74N ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
SN74AC74NE4 ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
SN74AC74NSR ACTIVE SO NS 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC74NSRE4 ACTIVE SO NS 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC74PW ACTIVE TSSOP PW 14 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC74PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC74PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI
SN74AC74PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC74PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54AC74FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54AC74J ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
SNJ54AC74W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006

OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 2
 MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

NO. OF A B
18 17 16 15 14 13 12
TERMINALS
** MIN MAX MIN MAX

0.342 0.358 0.307 0.358

19 11 20
(8,69) (9,09) (7,80) (9,09)
20 10 0.442 0.458 0.406 0.458
28
(11,23) (11,63) (10,31) (11,63)
21 9
B SQ 0.640 0.660 0.495 0.560
22 8 44
(16,26) (16,76) (12,58) (14,22)
A SQ
23 7 0.739 0.761 0.495 0.560
52
(18,78) (19,32) (12,58) (14,22)
24 6
0.938 0.962 0.850 0.858
68
(23,83) (24,43) (21,6) (21,8)
25 5
1.141 1.165 1.047 1.063
84
(28,99) (29,59) (26,6) (27,0)
26 27 28 1 2 3 4

0.020 (0,51) 0.080 (2,03)

0.010 (0,25) 0.064 (1,63)

0.020 (0,51)
0.010 (0,25)

0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)

0.028 (0,71) 0.045 (1,14)

0.022 (0,54) 0.035 (0,89)
0.050 (1,27)

4040140 / D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30
0,65 0,10 M
0,19
14 8

0,15 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25
1 7
0°– 8°
A 0,75
0,50

Seating Plane

1,20 MAX 0,15 0,10

0,05

PINS **
8 14 16 20 24 28
DIM

A MAX 3,10 5,10 5,10 6,60 7,90 9,80

A MIN 2,90 4,90 4,90 6,40 7,70 9,60

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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