SN54AHC16540, SN74AHC16540

16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS331F – MARCH 1996 – REVISED JANUARY 2000

D Members of the Texas Instruments SN54AHC16540 . . . WD PACKAGE

Widebus  Family SN74AHC16540 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
D EPIC  (Enhanced-Performance Implanted
CMOS) Process 1OE1 1 48 1OE2
D Operating Range 2-V to 5.5-V VCC 1Y1 2 47 1A1
D Distributed VCC and GND Pins Minimize 1Y2 3 46 1A2
High-Speed Switching Noise GND 4 45 GND
D Flow-Through Architecture Optimizes PCB 1Y3 5 44 1A3
1Y4 6 43 1A4
Layout
D Latch-Up Performance Exceeds 250 mA Per
VCC
1Y5
7
8
42
41
VCC
1A5
JESD 17
1Y6 9 40 1A6
D ESD Protection Exceeds 2000 V Per GND 10 39 GND
MIL-STD-883, Method 3015 1Y7 11 38 1A7
D Package Options Include Plastic Shrink 1Y8 12 37 1A8
Small-Outline (DL), Thin Shrink 2Y1 13 36 2A1
Small-Outline (DGG), and Thin Very 2Y2 14 35 2A2
Small-Outline (DGV) Packages and 380-mil GND 15 34 GND
Fine-Pitch Ceramic Flat (WD) Package 2Y3 16 33 2A3
Using 25-mil Center-to-Center Spacings 2Y4 17 32 2A4
VCC 18 31 VCC
description 2Y5 19 30 2A5
2Y6 20 29 2A6
These 16-bit buffers and bus drivers provide a
GND 21 28 GND
high-performance bus interface for wide data
2Y7 22 27 2A7
paths.
2Y8 23 26 2A8
The 3-state control gate is a 2-input AND gate with 2OE1 24 25 2OE2
active-low inputs so that if either output-enable
(OE1 or OE2) input is high, all corresponding
outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54AHC16540 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AHC16540 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE
(each 8-bit buffer/driver)
INPUTS OUTPUT
OE1 OE2 A Y

L L L H
L L H L
H X X Z
X H X Z

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION Copyright  2000, Texas Instruments Incorporated
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54AHC16540, SN74AHC16540
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS331F – MARCH 1996 – REVISED JANUARY 2000

logic symbol†
1 &
1OE1
48 EN1
1OE2
24
2OE1 &
25 EN2
2OE2

47 2
1A1 1 1 1Y1
46 3
1A2 1Y2
44 5
1A3 1Y3
43 6
1A4 1Y4
41 8
1A5 1Y5
40 9
1A6 1Y6
38 11
1A7 1Y7
37 12
1A8 1Y8
36 13
2A1 1 2 2Y1
35 14
2A2 2Y2
33 16
2A3 2Y3
32 17
2A4 2Y4
30 19
2A5 2Y5
29 20
2A6 2Y6
27 22
2A7 2Y7
26 23
2A8 2Y8

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

1 24
1OE1 2OE1
48 25
1OE2 2OE2

47 2 36 13
1A1 1Y1 2A1 2Y1

To Seven Other Channels To Seven Other Channels

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN54AHC16540, SN74AHC16540
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS331F – MARCH 1996 – REVISED JANUARY 2000

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 3)

SN54AHC16540 SN74AHC16540
UNIT
MIN MAX MIN MAX
VCC Supply voltage 2 5.5 2 5.5 V
VCC = 2 V 1.5 1.5
VIH High-level input voltage VCC = 3 V 2.1 2.1 V
VCC = 5.5 V 3.85 3.85
VCC = 2 V 0.5 0.5
VIL Low-level input voltage VCC = 3 V 0.9 0.9 V
VCC = 5.5 V 1.65 1.65
VI Input voltage 0 5.5 0 5.5 V
VO Output voltage 0 VCC 0 VCC V
VCC = 2 V –50 –50 mA
IOH High-level output current VCC = 3.3 V ± 0.3 V –4 –4
mA
VCC = 5 V ± 0.5 V –8 –8
VCC = 2 V 50 50 mA
IOL Low-level output current VCC = 3.3 V ± 0.3 V 4 4
mA
VCC = 5 V ± 0.5 V 8 8
VCC = 3.3 V ± 0.3 V 100 100
∆t/∆v Input transition rise or fall rate ns/V
VCC = 5 V ± 0.5 V 20 20
TA Operating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54AHC16540, SN74AHC16540
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS331F – MARCH 1996 – REVISED JANUARY 2000

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
TA = 25°C SN54AHC16540 SN74AHC16540
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
2V 1.9 2 1.9 1.9
IOH = –50 mA 3V 2.9 3 2.9 2.9
VOH 4.5 V 4.4 4.5 4.4 4.4 V
IOH = –4 mA 3V 2.58 2.48 2.48
IOH = –8 mA 4.5 V 3.94 3.8 3.8
2V 0.1 0.1 0.1
IOL = 50 mA 3V 0.1 0.1 0.1
VOL 4.5 V 0.1 0.1 0.1 V
IOL = 4 mA 3V 0.36 0.5 0.44
IOL = 8 mA 4.5 V 0.36 0.5 0.44
II VI = VCC or GND 0 V to 5.5 V ±0.1 ±1* ±1 mA
VO = VCC or GND,
IOZ 5.5 V ±0.25 ±2.5 ±2.5 mA
VI (OE) = VIL or VIH
ICC VI = VCC or GND, IO = 0 5.5 V 4 40 40 mA
Ci VI = VCC or GND 5V 2 10 10 pF
Co VO = VCC or GND 5V 3 pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.

switching characteristics over recommended operating free-air temperature range,

VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
FROM TO LOAD TA = 25°C SN54AHC16540 SN74AHC16540
PARAMETER UNIT
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
tPLH 4.8** 8.4** 1** 10** 1 10
A Y CL = 15 pF ns
tPHL 4.8** 8.4** 1** 10** 1 10
tPZH 6.8** 10.6** 1** 12.5** 1 12.5
OE Y CL = 15 pF ns
tPZL 6.8** 10.6** 1** 12.5** 1 12.5
tPHZ 6.8** 11.5** 1** 12.5** 1 12.5
OE Y CL = 15 pF ns
tPLZ 6.8** 11.5** 1** 12.5** 1 12.5
tPLH 7.7 11 1 12.5 1 12.5
A Y CL = 50 pF ns
tPHL 7.3 11 1 12.5 1 12.5
tPZH 9.7 14.1 1 16 1 16
OE Y CL = 50 pF ns
tPZL 7.1 14.1 1 16 1 16
tPHZ 9.4 14 1 16 1 16
OE Y CL = 50 pF ns
tPLZ 9.7 14 1 16 1 16
tsk(o) CL = 50 pF 1.5*** 1.5 ns
** On products compliant to MIL-PRF-38535, this parameter is not production tested.
*** On products compliant to MIL-PRF-38535, this parameter does not apply.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN54AHC16540, SN74AHC16540
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS331F – MARCH 1996 – REVISED JANUARY 2000

switching characteristics over recommended operating free-air temperature range,

VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
FROM TO LOAD TA = 25°C SN54AHC16540 SN74AHC16540
PARAMETER UNIT
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
tPLH 3.7* 6* 1* 7* 1 7
A Y CL = 15 pF ns
tPHL 3.7* 6* 1* 7* 1 7
tPZH 4.7* 7.3* 1* 8.5* 1 8.5
OE Y CL = 15 pF ns
tPZL 4.7* 7.3* 1* 8.5* 1 8.5
tPHZ 4.5* 7.2* 1* 8.5* 1 8.5
OE Y CL = 15 pF ns
tPLZ 4.5* 7.2* 1* 8.5* 1 8.5
tPLH 5.2 8 1 9 1 8.5
A Y CL = 50 pF ns
tPHL 5.2 8 1 9 1 8.5
tPZH 6.2 9.3 1 10.5 1 10.5
OE Y CL = 50 pF ns
tPZL 6.2 9.3 1 10.5 1 10.5
tPHZ 6 9.2 1 10.5 1 10.5
OE Y CL = 50 pF ns
tPLZ 6 9.2 1 10.5 1 10.5
tsk(o) CL = 50 pF 1** 1 ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
** On products compliant to MIL-PRF-38535, this parameter does not apply.

noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4)

SN74AHC16540
PARAMETER UNIT
MIN TYP MAX
VOL(P) Quiet output, maximum dynamic VOL 0.6 V
VOL(V) Quiet output, minimum dynamic VOL –0.3 V
VOH(V) Quiet output, minimum dynamic VOH 4.7 V
VIH(D) High-level dynamic input voltage 3.5 V
VIL(D) Low-level dynamic input voltage 1.5 V
NOTE 4: Characteristics are for surface-mount packages only.

operating characteristics, VCC = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load, f = 1 MHz 13 pF

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN54AHC16540, SN74AHC16540
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS331F – MARCH 1996 – REVISED JANUARY 2000

PARAMETER MEASUREMENT INFORMATION

VCC
RL = 1 kΩ S1 Open
From Output Test From Output TEST S1
Under Test Point Under Test GND tPLH/tPHL Open
CL CL tPLZ/tPZL VCC
(see Note A) (see Note A) tPHZ/tPZH GND
Open Drain VCC

LOAD CIRCUIT FOR LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS 3-STATE AND OPEN-DRAIN OUTPUTS

VCC
Timing Input 50% VCC
tw 0V
th
VCC tsu
VCC
Input 50% VCC 50% VCC
Data Input 50% VCC 50% VCC
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VCC VCC
Output
Input 50% VCC 50% VCC 50% VCC 50% VCC
Control
0V 0V

tPLH tPHL tPZL tPLZ

Output
VOH Waveform 1 ≈VCC
In-Phase 50% VCC 50% VCC 50% VCC
Output S1 at VCC VOL + 0.3 V
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
Output
VOH VOH
Out-of-Phase Waveform 2
50% VCC 50% VCC 50% VCC VOH – 0.3 V
Output S1 at GND
VOL (see Note B) ≈0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74AHC16540DGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AHC16540

SN74AHC16540DL ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AHC16540

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AHC16540DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AHC16540DGGR TSSOP DGG 48 2000 367.0 367.0 45.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN74AHC16540DL DL SSOP 48 25 473.7 14.24 5110 7.87

Pack Materials-Page 3
 PACKAGE OUTLINE
DGG0048A SCALE 1.350
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

C
8.3 SEATING PLANE
TYP
7.9
PIN 1 ID 0.1 C
A
AREA
46X 0.5
48
1

12.6 2X
12.4 11.5
NOTE 3

24
25
0.27
48X
6.2 0.17 1.2
B
6.0 0.08 C A B 1.0

(0.15) TYP

0.25
SEE DETAIL A GAGE PLANE

0.15
0 -8 0.75 0.05
0.50

DETAIL A
TYPICAL

4214859/B 11/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
DGG0048A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

48X (1.5) SYMM

1
48

48X (0.3)

46X (0.5)

(R0.05) SYMM
TYP

24 25

(7.5)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214859/B 11/2020

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DGG0048A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

48X (1.5) SYMM

1
48

48X (0.3)

46X (0.5)

SYMM
(R0.05) TYP

24 25

(7.5)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4214859/B 11/2020
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 MECHANICAL DATA

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998

DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,27
0,50 0,08 M
0,17
48 25

6,20 8,30
6,00 7,90 0,15 NOM

Gage Plane

0,25
1 24
0°– 8°
A 0,75
0,50

Seating Plane
0,15
1,20 MAX 0,10
0,05

PINS **
48 56 64
DIM

A MAX 12,60 14,10 17,10

A MIN 12,40 13,90 16,90

4040078 / F 12/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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