SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003

D Wide Operating Voltage Range of 2 V to 6 V SN54HC112 . . . J OR W PACKAGE

SN74HC112 . . . D OR N PACKAGE
D Outputs Can Drive Up To 10 LSTTL Loads (TOP VIEW)
D Low Power Consumption, 40-µA Max ICC
D Typical tpd = 13 ns 1CLK 1 16 VCC
1K 2 15 1CLR
D ±4-mA Output Drive at 5 V
1J 3 14 2CLR
D Low Input Current of 1 µA Max 1PRE 4 13 2CLK
1Q 5 12 2K
description/ordering information 1Q 6 11 2J
The ’HC112 devices contain two independent J-K 2Q 7 10 2PRE
negative-edge-triggered flip-flops. A low level at GND 8 9 2Q
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs, regardless of the levels of the SN54HC112 . . . FK PACKAGE
other inputs. When PRE and CLR are inactive (TOP VIEW)

1CLR
1CLK
(high), data at the J and K inputs meeting the

VCC
NC
1K
setup time requirements are transferred to the
outputs on the negative-going edge of the clock
(CLK) pulse. Clock triggering occurs at a voltage 3 2 1 20 19
1J 4 18 2CLR
level and is not directly related to the fall time of the 1PRE 2CLK
5 17
CLK pulse. Following the hold-time interval, data
NC 6 16 NC
at the J and K inputs may be changed without
1Q 7 15 2K
affecting the levels at the outputs. These versatile
1Q 8 14 2J
flip-flops perform as toggle flip-flops by tying J and 9 10 11 12 13
K high.

GND
2Q

2Q
2PRE
NC
NC − No internal connection

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
PDIP − N Tube of 25 SN74HC112N SN74HC112N
Tube of 40 SN74HC112D
−40°C to 85°C
SOIC − D Reel of 2500 SN74HC112DR HC112
Reel of 250 SN74HC112DT
CDIP − J Tube of 25 SNJ54HC112J SNJ54HC112J
−55°C
−55 C to 125
125°C
C CFP − W Tube of 150 SNJ54HC112W SNJ54HC112W
LCCC − FK Tube of 55 SNJ54HC112FK
SNJ54HC112FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

   !"#$ % &'!!($ #%  )'*+&#$ ,#$(- Copyright  2003, Texas Instruments Incorporated
!,'&$% &!" $ %)(&&#$% )(! $.( $(!"%  (/#% %$!'"($%  )!,'&$% &")+#$ $ 3454 #++ )#!#"($(!% #!( $(%$(,
%$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( '+(%% $.(!0%( $(,-  #++ $.(! )!,'&$% )!,'&$
$(%$2  #++ )#!#"($(!%- )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2  #++ )#!#"($(!%-

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1





     

    

SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003

FUNCTION TABLE
INPUTS OUTPUTS
PRE CLR CLK J K Q Q
L H X X X H L
H L X X X L H
L L X X X H† H†
H H ↓ L L Q0 Q0
H H ↓ H L H L
H H ↓ L H L H
H H ↓ H H Toggle
H H H X X Q0 Q0
† This configuration is nonstable; that is, it does not persist
when either PRE or CLR returns to its inactive (high) level.

logic diagram, each flip-flop (positive logic)

PRE

J C C

TG Q
TG

K
C C

C C
CLK C
TG TG
C

C C
Q
CLR

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265





     

    

SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003

absolute maximum ratings over operating free-air temperature range†

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN54HC112 SN74HC112
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0.5 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 V
VCC = 6 V 1.8 1.8
VI Input voltage 0 VCC 0 VCC V
VO Output voltage 0 VCC 0 VCC V
VCC = 2 V 1000 1000
tt‡ Input transition (rise and fall) time VCC = 4.5 V 500 500 ns
VCC = 6 V 400 400
TA Operating free-air temperature −55 125 −40 85 °C
‡ If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3





     

    

SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
TA = 25°C SN54HC112 SN74HC112
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
2V 1.9 1.998 1.9 1.9
IOH = −20 µA 4.5 V 4.4 4.499 4.4 4.4
VOH VI = VIH or VIL 6V 5.9 5.999 5.9 5.9 V
IOH = −4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = −5.2 mA 6V 5.48 5.8 5.2 5.34
2V 0.002 0.1 0.1 0.1
IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1
VOL VI = VIH or VIL 6V 0.001 0.1 0.1 0.1 V
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6V 0.15 0.26 0.4 0.33
II VI = VCC or 0 6V ±0.1 ±100 ±1000 ±1000 nA
ICC VI = VCC or 0, IO = 0 6V 4 80 40 µA
Ci 2 V to 6 V 3 10 10 10 pF

timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HC112 SN74HC112
VCC UNIT
MIN MAX MIN MAX MIN MAX
2V 5 3.4 4
fclock Clock frequency 4.5 V 25 17 20 MHz
6V 29 20 24
2V 100 150 125
PRE or CLR low 4.5 V 20 30 25
6V 17 25 21
tw Pulse duration ns
2V 100 150 125
CLK high or low 4.5 V 20 30 25
6V 17 25 21
2V 100 150 125
Data (J, K) 4.5 V 20 30 25
6V 17 25 21
tsu Setup time before CLK↓ ns
2V 100 150 125
PRE or CLR inactive 4.5 V 20 30 25
6V 17 25 21
2V 0 0 0
th Hold time, data after CLK↓ 4.5 V 0 0 0 ns
6V 0 0 0

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265





     

    

SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003

switching characteristics over recommended operating free-air temperature range, CL = 50 pF

(unless otherwise noted) (see Figure 1)
FROM TO TA = 25°C SN54HC112 SN74HC112
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
2V 5 10 3.4 4
fmax 4.5 V 25 50 17 20 MHz
6V 29 60 20 24
2V 54 165 245 205
PRE or CLR Q or Q 4.5 V 16 33 49 41
6V 13 28 42 35
tpd ns
2V 56 125 185 155
CLK Q or Q 4.5 V 16 25 37 31
6V 13 21 31 26
2V 29 75 110 95
tt Q or Q 4.5 V 9 15 22 19 ns
6V 8 13 19 16

operating characteristics, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load 35 pF

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5





     

    

SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003

PARAMETER MEASUREMENT INFORMATION

VCC
High-Level
50% 50%
Pulse
From Output Test 0V
Under Test Point tw
CL = 50 pF VCC
(see Note A) Low-Level
Pulse 50% 50%
0V
LOAD CIRCUIT VOLTAGE WAVEFORMS
PULSE DURATIONS

VCC
Input 50% 50%
0V
tPLH tPHL
VCC In-Phase VOH
Reference 50% 90% 90%
Output 50% 50%
Input 10% 10%
0V VOL
tr tf
tsu th
tPHL tPLH
Data VCC VOH
90% 90% Out-of-Phase 90% 90%
Input 50% 50% 50% 50%
10% 10% 0 V Output 10% 10%
VOL
tr tf tf tr

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

SETUP AND HOLD AND INPUT RISE AND FALL TIMES PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

NOTES: A. CL includes probe and test-fixture capacitance.

B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

84088012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84088012A
SNJ54HC
112FK
8408801EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8408801EA
SNJ54HC112J
8408801FA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 8408801FA
SNJ54HC112W
JM38510/65305BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
65305BEA
M38510/65305BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
65305BEA
SN54HC112J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC112J

SN74HC112D ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC112

& no Sb/Br)
SN74HC112DR ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC112
& no Sb/Br)
SN74HC112DT ACTIVE SOIC D 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC112
& no Sb/Br)
SN74HC112N ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC112N
& no Sb/Br)
SNJ54HC112FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84088012A
SNJ54HC
112FK
SNJ54HC112J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8408801EA
SNJ54HC112J
SNJ54HC112W ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 8408801FA
SNJ54HC112W

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54HC112, SN74HC112 :

• Catalog: SN74HC112
• Military: SN54HC112

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 (mm) B0 (mm) K0 (mm) P1 W Pin1
Type Drawing Diameter Width (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC112DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC112DR SOIC D 16 2500 333.2 345.9 28.6

Pack Materials-Page 2
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