SCLS584A − MAY 2004 − REVISED APRIL 2008

D Qualified for Automotive Applications D Carry Output for n-Bit Cascading

D Wide Operating Voltage Range of 2 V to 6 V D Synchronous Counting
D Outputs Can Drive Up To 10 LSTTL Loads D Synchronously Programmable
D Low Power Consumption, 80-µA Max ICC
PW PACKAGE
D Typical tpd = 14 ns (TOP VIEW)
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max CLR 1 16 VCC
CLK RCO
D Internal Look-Ahead for Fast Counting
2 15
A 3 14 QA
description/ordering information B 4 13 QB
C 5 12 QC
This synchronous, presettable counter features an 6 11 D QD
internal carry look-ahead for application in 7 10 ENP ENT
high-speed counting designs. The SN74HC163 is a 8 9 GND LOAD
4-bit binary counter. Synchronous operation is
provided by having all flip-flops clocked
simultaneously so that the outputs change coincident with each other when instructed by the count-enable
(ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally
associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on
the rising (positive-going) edge of the clock waveform.
This counter is fully programmable; that is, it can be preset to any number between 0 and 9 or 15. As presetting
is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree
with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the SN74HC163 is synchronous. A low level at the clear (CLR) input sets all four of the
flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs.
This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum
count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear
the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.

ORDERING INFORMATION{
ORDERABLE TOP-SIDE
TA PACKAGE‡
PART NUMBER MARKING
−40°C to 85°C TSSOP − PW Tape and reel SN74HC163IPWRQ1 HC163I
† For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at http://www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

     !"#   $"%&! '#( Copyright  2008 Texas Instruments Incorporated
'"! !  $#!! $# )# #  #* "#
'' +,( '"! $!#- '#  #!#&, !&"'#
#-  && $##(

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1


 
 

 
SCLS584A − MAY 2004 − REVISED APRIL 2008

description/ordering information (continued)

This counter features a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.

logic diagram (positive logic)

9
LOAD
10
ENT 15
RCO
LD†
7
ENP
CK†
2
CLK
1 CK LD
CLR
R

M1
G2
1, 2T/1C3 14
QA
G4
3
A 3D
4R

M1
G2
1, 2T/1C3 13
QB
G4
4
B 3D
4R

M1
G2
1, 2T/1C3 12
QC
G4
5
C 3D
4R

M1
G2
1, 2T/1C3 11
QD
G4
6
D 3D
4R

† For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


 
 

 
SCLS584A − MAY 2004 − REVISED APRIL 2008

logic symbol, each D/T flip-flop

LD (Load) M1

TE (Toggle Enable) G2

CK (Clock) 1, 2T/1C3 Q (Output)

G4

D (Inverted Data) 3D

R (Inverted Reset) 4R

logic diagram, each D/T flip-flop (positive logic)

CK
LD
TE

LD† TG

TG
TG Q
LD† TG

CK†
D CK†
TG TG

CK† CK†
R

† The origins of LD and CK are shown in the logic diagram of the overall device.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3


 
 

 
SCLS584A − MAY 2004 − REVISED APRIL 2008

typical clear, preset, count, and inhibit sequence

The following sequence is illustrated below:
1. Clear outputs to zero (synchronous)
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit

CLR

LOAD

B
Data
Inputs
C

CLK

ENP

ENT

QA

QB
Data
Outputs
QC

QD

RCO
12 13 14 15 0 1 2
Count Inhibit
Sync Preset
Clear

Async
Clear

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


 
 

 
SCLS584A − MAY 2004 − REVISED APRIL 2008

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

MIN NOM MAX UNIT
VCC Supply voltage 2 5 6 V
VCC = 2 V 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 V
VCC = 6 V 4.2
VCC = 2 V 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 V
VCC = 6 V 1.8
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
VCC = 2 V 1000
∆t/∆v‡ Input transition rise/fall time VCC = 4.5 V 500 ns
VCC = 6 V 400
TA Operating free-air temperature −40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
‡ If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5


 
 

 
SCLS584A − MAY 2004 − REVISED APRIL 2008

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
TA = 25°C
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
MIN TYP MAX
2V 1.9 1.998 1.9
IOH = −20 µA 4.5 V 4.4 4.499 4.4
VOH VI = VIH or VIL 6V 5.9 5.999 5.9 V
IOH = −4 mA 4.5 V 3.98 4.3 3.84
IOH = −5.2 mA 6V 5.48 5.8 5.34
2V 0.002 0.1 0.1
IOL = 20 µA 4.5 V 0.001 0.1 0.1
VOL VI = VIH or VIL 6V 0.001 0.1 0.1 V
IOL = 4 mA 4.5 V 0.17 0.26 0.33
IOL = 5.2 mA 6V 0.15 0.26 0.33
II VI = VCC or 0 6V ±0.1 ±100 ±1000 nA
ICC VI = VCC or 0, IO = 0 6V 8 80 µA
Ci 2 V to 6 V 3 10 10 pF

timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C
VCC MIN MAX UNIT
MIN MAX
2V 6 5
fclock Clock frequency 4.5 V 31 25 MHz
6V 36 29
2V 80 100
tw Pulse duration CLK high or low 4.5 V 16 20 ns
6V 14 17
2V 150 190
A, B, C, or D 4.5 V 30 38
6V 26 32
2V 135 170
LOAD low 4.5 V 27 34
6V 23 29
2V 170 215
tsu Setup time before CLK↑ ENP, ENT 4.5 V 34 43 ns
6V 29 37
2V 160 200
CLR low 4.5 V 32 40
6V 27 34
2V 160 200
CLR inactive 4.5 V 32 40
6V 27 34
2V 0 0
th Hold time, all synchronous inputs after CLK
CLK↑ 4.5 V 0 0 ns
6V 0 0

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


 
 

 
SCLS584A − MAY 2004 − REVISED APRIL 2008

switching characteristics over recommended operating free-air temperature range, CL = 50 pF

(unless otherwise noted) (see Figure 1)
FROM TO TA = 25°C
PARAMETER VCC MIN MAX UNIT
(INPUT) (OUTPUT) MIN TYP MAX
2V 6 14 5
fmax 4.5 V 31 40 25 MHz
6V 36 44 29
2V 83 215 270
RCO 4.5 V 24 43 54
6V 20 37 46
CLK
2V 80 205 255
tpd Any Q 4.5 V 25 41 51 ns
6V 21 35 43
2V 62 195 245
ENT RCO 4.5 V 17 39 49
6V 14 33 42
2V 38 75 95
tt Any 4.5 V 8 15 19 ns
6V 6 13 16

operating characteristics, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load 60 pF

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7


 
 

 
SCLS584A − MAY 2004 − REVISED APRIL 2008

PARAMETER MEASUREMENT INFORMATION

VCC
High-Level
50% 50%
Pulse
From Output Test 0V
Under Test Point tw
CL = 50 pF VCC
(see Note A) Low-Level
Pulse 50% 50%
0V
LOAD CIRCUIT VOLTAGE WAVEFORMS
PULSE DURATIONS

VCC
Input 50% 50%
0V
tPLH tPHL
VCC In-Phase VOH
Reference 50% 90% 90%
Output 50% 50%
Input 10% 10%
0V VOL
tr tf
tsu th
tPHL tPLH
Data VCC VOH
90% 90% Out-of-Phase 90% 90%
Input 50% 50% 50% 50%
10% 10% 0 V Output 10% 10%
VOL
tr tf tf tr

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

SETUP AND HOLD AND INPUT RISE AND FALL TIMES PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

NOTES: A. CL includes probe and test-fixture capacitance.

B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


 
 

 
SCLS584A − MAY 2004 − REVISED APRIL 2008

APPLICATION INFORMATION

n-bit synchronous counters

This application demonstrates how the look-ahead carry circuit can be used to implement a high-speed n-bit
counter. The SN74HC163 counts in binary. Virtually any count mode (modulo-N, N1-to-N2, N1-to-maximum) can
be used with this fast look-ahead circuit.
The application circuit shown in Figure 2 is not valid for clock frequencies above 18 MHz (at 25°C and
4.5-V VCC). The reason for this is that there is a glitch that is produced on the second stage’s RCO and every
succeeding stage’s RCO. This glitch is common to all HC vendors that Texas Instruments has evaluated, in
addition to the bipolar equivalents (LS, ALS, AS).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9


 
 

 
SCLS584A − MAY 2004 − REVISED APRIL 2008

APPLICATION INFORMATION
LSB
CLR CTR
Clear (L) CT=0
LOAD M1 RCO
Count (H)/ ENT 3CT=MAX
G3
Disable (L) ENP G4
CLK
C5/2,3,4+

Load (L) A 1,5D [1] QA

Count (H)/ B [2] QB
Disable (L) C [3] QC
D [4] QD
Clock

CTR
CLR CT=0
LOAD M1 RCO
ENT 3CT=MAX
G3
ENP
G4
CLK
C5/2,3,4+

A 1,5D [1] QA
B [2] QB
C [3] QC
D [4] QD

CTR
CLR CT=0
LOAD M1 RCO
ENT 3CT=MAX
G3
ENP
G4
CLK
C5/2,3,4+

A 1,5D [1] QA
B [2] QB
C [3] QC
D [4] QD

CLR CTR
CT=0
LOAD M1 RCO
ENT 3CT=MAX
G3
ENP G4
CLK
C5/2,3,4+

A 1,5D [1] QA
B [2] QB
C [3] QC
D [4] QD

To More-Significant Stages
Figure 2

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


 
 

 
SCLS584A − MAY 2004 − REVISED APRIL 2008

APPLICATION INFORMATION

n-bit synchronous counters (continued)

The glitch on RCO is caused because the propagation delay of the rising edge of QA of the second stage is
shorter than the propagation delay of the falling edge of ENT. RCO is the product of ENT, QA, QB, QC, and QD
(ENT × QA × QB × QC × QD). The resulting glitch is about 7 ns to 12 ns in duration. Figure 3 shows the condition
in which the glitch occurs. For simplicity, only two stages are being considered, but the results can be applied
to other stages. QB, QC, and QD of the first and second stage are at logic one, and QA of both stages are at logic
zero (1110 1110) after the first clock pulse. On the rising edge of the second clock pulse, QA and RCO of the
first stage go high. On the rising edge of the third clock pulse, QA and RCO of the first stage return to a low level,
and QA of the second stage goes to a high level. At this time, the glitch on RCO of the second stage appears
because of the race condition inside the chip.
1 2 3 4 5

CLK

ENT1

QB1, QC1, QD1

QA1

RCO1, ENT2

QB2, QC2, QD2

QA2

RCO2 Glitch (7−12 ns)

Figure 3

The glitch causes a problem in the next stage (stage three) if the glitch is still present when the next rising clock
edge appears (clock pulse 4). To ensure that this does not happen, the clock frequency must be less than the
inverse of the sum of the clock-to-RCO propagation delay and the glitch duration (tg). In other words,
fmax = 1/(tpd CLK-to-RCO + tg). For example, at 25°C at 4.5-V VCC, the clock-to-RCO propagation delay is
43 ns and the maximum duration of the glitch is 12 ns. Therefore, the maximum clock frequency that the
cascaded counters can use is 18 MHz. The following tables contain the fclock, tw, and fmax specifications for
applications that use more than two ’HC163 devices cascaded together.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11


 
 

 
SCLS584A − MAY 2004 − REVISED APRIL 2008

APPLICATION INFORMATION

n-bit synchronous counters (continued)

timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C
VCC MIN MAX UNIT
MIN MAX
2V 3.6 2.9
fclock Clock frequency 4.5 V 18 14 MHz
6V 21 17
2V 140 170
tw Pulse duration, CLK high or low 4.5 V 28 36 ns
6V 24 30

switching characteristics over recommended operating free-air temperature range, CL = 50 pF

(unless otherwise noted) (see Note 4)
FROM TO TA = 25°C
PARAMETER VCC MIN MAX UNIT
(INPUT) (OUTPUT) MIN MAX
2V 3.6 2.9
fmax 4.5 V 18 14 MHz
6V 21 17
NOTE 4: These limits apply only to applications that use more than two ’HC163 devices cascaded together.

If the SN74HC163 device is used as a single unit, or only two are cascaded together, then the maximum clock
frequency that the device can use is not limited because of the glitch. In these situations, the device can be
operated at the maximum specifications.
A glitch can appear on the RCO of a single SN74HC163 device, depending on the relationship of ENT to CLK.
Any application that uses RCO to drive any input, except an ENT of another cascaded SN74HC163 device, must
take this into consideration.

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OPTION ADDENDUM

www.ti.com 23-May-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

SN74HC163IPWRG4Q1 Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC163I
SN74HC163IPWRG4Q1.A Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC163I

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74HC163-Q1 :

• Catalog : SN74HC163

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 23-May-2025

• Military : SN54HC163

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC163IPWRG4Q1 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC163IPWRG4Q1 TSSOP PW 16 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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