SCLS542B − SEPTEMBER 2003 − REVISED JANUARY 2004

D Injection-Current Cross Coupling <1mV/mA D, DGV, N, OR PW PACKAGE

(see Figure 1) (TOP VIEW)

D Low Crosstalk Between Switches Y4 1 16 VCC

D Pin Compatible With SN74HC4051, Y6 2 15 Y2
SN74LV4051A, and CD4051B COM 3 14 Y1
D 2-V to 6-V VCC Operation Y7 4 13 Y0
D Latch-Up Performance Exceeds 100 mA Per Y5 5 12 Y3
JESD 78, Class II INH 6 11 A
NC 7 10 B
D ESD Protection Exceeds JESD 22
GND 8 9 C
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
NC − No internal connection
− 1000-V Charged-Device Model (C101)

description/ordering information
This eight-channel CMOS analog multiplexer/demultiplexer is pin compatible with the ’4051 function and,
additionally, features injection-current effect control, which has excellent value in automotive applications where
voltages in excess of normal supply voltages are common.
The injection-current effect control allows signals at disabled analog input channels to exceed the supply
voltage without affecting the signal of the enabled analog channel. This eliminates the need for external
diode/resistor networks typically used to keep the analog channel signals within the supply-voltage range.

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
PDIP − N Tube SN74HC4851N HC4851N
Tube SN74HC4851D
SOIC − D HC4851
Tape and reel SN74HC4851DR
−40°C to 125°C
Tube SN74HC4851PW
TSSOP − PW HC4851
Tape and reel SN74HC4851PWR
TVSOP − DGV Tape and reel SN74HC4851DGVR HC4851
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

  !"#$ % &'!!($ #%  )'*+&#$ ,#$(- Copyright  2004, Texas Instruments Incorporated
!,'&$% &!" $ %)(&&#$% )(! $.( $(!"%  (/#% %$!'"($%
%$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',(
$(%$2  #++ )#!#"($(!%-

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1




       
 
  
SCLS542B − SEPTEMBER 2003 − REVISED JANUARY 2004

FUNCTION TABLE
INPUTS ON
INH C B A CHANNEL
L L L L Y0
L L L H Y1
L L H L Y2
L L H H Y3
L H L L Y4
L H L H Y5
L H H L Y6
L H H H Y7
H X X X None

logic diagram (positive logic)

Injection-
3
Current COM
Control

Injection-
13
Current Y0
Control

Injection- 14
11
Current Y1
Control
A

Injection- 15
Current Y2
Control

Injection-
12 Y3
Current
10 Control
B
Injection-
1 Y4
Current
Control

Injection-
5
Current Y5
Control
9
C
Injection-
2
Current Y6
Control

Injection-
4
6 Current Y7
INH Control

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265




       
 
  
SCLS542B − SEPTEMBER 2003 − REVISED JANUARY 2004

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Switch I/O voltage range, VIO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
I/O diode current, IIOK (VIO < 0 or VIO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Switch through current, IT (VIO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 4)

MIN MAX UNIT
VCC Supply voltage 2 6 V
VCC = 2 V 1.5
VCC = 3 V 2.1
High-level input voltage,
VIH VCC = 3.3 V 2.3 V
control inputs
VCC = 4.5 V 3.15
VCC = 6 V 4.2
VCC = 2 V 0.5
VCC = 3 V 0.9
Low-level input voltage,
VIL VCC = 3.3 V 1 V
control inputs
VCC = 4.5 V 1.35
VCC = 6 V 1.8
VI Control input voltage 0 VCC V
VIO Input/output voltage 0 VCC V
VCC = 2 V 1000
VCC = 3 V 800
∆t/∆v Input transition rise or fall time VCC = 3.3 V 700 ns
VCC = 4.5 V 500
VCC = 6 V 400
TA Operating free-air temperature −40 125 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3




       
 
  
SCLS542B − SEPTEMBER 2003 − REVISED JANUARY 2004

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
TA = 25°C UP TO 85°C UP TO 125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
2.V 500 650 670 700
IT ≤ 2 mA, 3V 215 280 320 360
On-state VI = VCC to GND,
ron 3.3 V 210 270 305 345 Ω
switch resistance VINH = VIL
(see Figure 5) 4.5 V 160 210 240 270
6V 150 195 220 250
2.V 4 10 15 20

Difference in IT ≤ 2 mA, 3V 2 8 12 16
∆ron on-state resistance VI = VCC/2, 3.3 V 2 8 12 16 Ω
between switches VINH = VIL 4.5 V 2 8 12 16
6V 3 9 13 18
II Control input current VI = VCC or GND 6V ±0.1 ±0.1 ±1 µA
Off-state switch VI = VCC or GND,
leakage current VINH = VIH ±0.1 ±0.5 ±1
(any one channel) (see Figure 6)
IS(off) 6V µA
A
Off-state switch VI = VCC or GND,
leakage current VINH = VIH ±0.2 ±2 ±4
(common channel) (see Figure 7)
VI = VCC or GND,
On-state switch
IS(on) VINH = VIL 6V ±0.1 ±0.5 ±1 µA
leakage current
(see Figure 8)
ICC Supply current VI = VCC or GND 6V 2 20 40 µA
CIC Control input capacitance A, B, C, INH 3.5 10 10 10 pF
Common
CIS Switch off 22 40 40 40 pF
terminal capacitance
COS Switch terminal capacitance Switch off 6.7 15 15 15 pF

injection current coupling specifications, TA = −40°C to 125°C

PARAMETER VCC TEST CONDITIONS MIN TYP† MAX UNIT
3.3 V 0.05 1
II‡ ≤ 1 mA
5V 0.1 1
RS ≤ 3.9 kΩ
3.3 V 0.345 5
II‡ ≤ 10 mA
Maximum shift of output voltage of enabled analog 5V 0.067 5
V∆out mV
channel 3.3 V 0.05 2
II‡ ≤ 1 mA
5V 0.11 2
RS ≤ 20 kΩ
3.3 V 0.05 20
II‡ ≤ 10 mA
5V 0.024 20
† Typical values are measured at TA = 25°C.
‡ II = total current injected into all disabled channels

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265




       
 
  
SCLS542B − SEPTEMBER 2003 − REVISED JANUARY 2004

switching characteristics over recommended operating free-air temperature range,

VCC = 2 V, CL = 50 pF (unless otherwise noted) (see Figures 9−14)
FROM TO TA = 25°C UP TO 85°C UP TO 125°C
PARAMETER UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
tPLH Propagation
COM or Yn Yn or COM 19.5 25 29 32 ns
tPHL delay time
tPLH Propagation
Channel Select COM or Yn 23 30 35 40 ns
tPHL delay time
tPZH Enable
INH COM or Yn 95 105 115 ns
tPZL delay time
tPHZ Disable
INH COM or Yn 95 105 115 ns
tPLZ delay time

switching characteristics over recommended operating free-air temperature range,

VCC = 3 V, CL = 50 pF (unless otherwise noted) (see Figures 9−14)
FROM TO TA = 25°C UP TO 85°C UP TO 125°C
PARAMETER UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
tPLH Propagation
COM or Yn Yn or COM 12 15.5 17.5 19.5 ns
tPHL delay time
tPLH Propagation
Channel Select COM or Yn 13.5 17.5 20 23 ns
tPHL delay time
tPZH Enable
INH COM or Yn 90 100 110 ns
tPZL delay time
tPHZ Disable
INH COM or Yn 90 100 110 ns
tPLZ delay time

switching characteristics over recommended operating free-air temperature range,

VCC = 3.3 V, CL = 50 pF (unless otherwise noted) (see Figures 9−14)
FROM TO TA = 25°C UP TO 85°C UP TO 125°C
PARAMETER UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
tPLH Propagation
COM or Yn Yn or COM 11 14.5 16.5 18.5 ns
tPHL delay time
tPLH Propagation
Channel Select COM or Yn 12.5 16.5 19 22 ns
tPHL delay time
tPZH Enable
INH COM or Yn 85 95 105 ns
tPZL delay time
tPHZ Disable
INH COM or Yn 85 95 105 ns
tPLZ delay time

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5




       
 
  
SCLS542B − SEPTEMBER 2003 − REVISED JANUARY 2004

switching characteristics over recommended operating free-air temperature range,

VCC = 4.5 V, CL = 50 pF (unless otherwise noted) (see Figures 9−14)
FROM TO TA = 25°C UP TO 85°C UP TO 125°C
PARAMETER UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
tPLH Propagation
COM or Yn Yn or COM 8.6 11.5 12.5 13.5 ns
tPHL delay time
tPLH Propagation
Channel Select COM or Yn 10 13 15 17 ns
tPHL delay time
tPZH Enable
INH COM or Yn 80 90 100 ns
tPZL delay time
tPHZ Disable
INH COM or Yn 80 90 100 ns
tPLZ delay time

switching characteristics over recommended operating free-air temperature range,

VCC = 6 V, CL = 50 pF (unless otherwise noted) (see Figures 9−14)
FROM TO TA = 25°C UP TO 85°C UP TO 125°C
PARAMETER UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
tPLH Propagation
COM or Yn Yn or COM 8 10 11 12 ns
tPHL delay time
tPLH Propagation
Channel Select COM or Yn 9.5 12.5 14.5 16.5 ns
tPHL delay time
tPZH Enable
INH COM or Yn 78 80 80 ns
tPZL delay time
tPHZ Disable
INH COM or Yn 78 80 80 ns
tPLZ delay time

operating characteristics, TA = 25°C (see Figure 15)

PARAMETER VCC TEST CONDITIONS TYP UNIT
3.3 V 32
Cpd Power dissipation capacitance No load pF
5V 37

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265




       
 
  
SCLS542B − SEPTEMBER 2003 − REVISED JANUARY 2004

APPLICATION INFORMATION
VCC = 5 V

IIO

VIN2 < VSS or VCC < VIN2

Any Disabled Channel

VSS < VIN1 < VCC

Enabled Channel Vout = VI1 V ± V∆out

RS

Figure 1. Injection-Current Coupling Specification

5V 6V
5V VCC

VCC
’HC4051
Sensor
Channel 1

Channel 2
Channel 3 Microcontroller

Channel 4

Channel 5

Channel 6
(8× Identical Channel 7
Circuitry)
Channel 8
Common Out A/D − Input

Figure 2. Alternate Solution Requires 32 Passive Components and One Extra 6-V Regulator
to Suppress Injection Current Into a Standard ’HC4051 Multiplexer

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7




       
 
  
SCLS542B − SEPTEMBER 2003 − REVISED JANUARY 2004

APPLICATION INFORMATION

5V VCC

VCC
’HC4851
Sensor
Channel 1

Channel 2
Channel 3 Microcontroller
Channel 4

Channel 5

Channel 6
(8× Identical
Channel 7
Circuitry)
Channel 8
Common Out A/D − Input

Figure 3. Solution by Applying the ’HC4851 Multiplexer

Gate = VCC
(Disabled)
Disabled Analog Multiplex Input Common Analog Output
VIN > VCC + 0.7 V Vout > VCC

P+ P+

N − Substrate (on VCC potential)

Figure 4. Diagram of Bipolar Coupling Mechanism

(Appears if VIN Exceeds VCC, Driving Injection Current Into the Substrate)

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265




       
 
  
SCLS542B − SEPTEMBER 2003 − REVISED JANUARY 2004

PARAMETER MEASUREMENT INFORMATION

VCC
VINH = VIL

VCC
VI = VCC to GND (ON) VO
GND VI – VO
r on + W
IT

IT

V
VI − VO

Figure 5. On-State-Resistance Test Circuit

VCC

VCC
16
GND
OFF
VCC A
NC OFF Common O/I

VINH = VIH 6

Figure 6. Maximum Off-Channel Leakage Current, Any One Channel, Test Setup

VCC
VCC
VCC 16
VCC A
16
GND ON
Analog I/O
OFF NC
GND
VCC OFF Common O/I
OFF Common O/I
VCC Analog I/O

VINH =VIH 6 VINH = VIL 6

8 8

Figure 7. Maximum Off-Channel Leakage Current, Figure 8. Maximum On-Channel Leakage Current,
Common Channel, Test Setup Channel To Channel, Test Setup

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9




       
 
  
SCLS542B − SEPTEMBER 2003 − REVISED JANUARY 2004

PARAMETER MEASUREMENT INFORMATION

VCC
VCC 16

Common O/I
ON/OFF
Test
Analog I/O
OFF/ON Point
CL†
VCC
Channel
50%
Select
GND
6
tPLH tPHL
8
Analog
50%
Out
Channel Select
† Includes all probe and jig capacitance

Figure 9. Propagation Delays, Figure 10. Propagation-Delay Test Setup,

Channel Select to Analog Out Channel Select to Analog Out

VCC
16
Analog I/O Common O/I
ON Test
Point
CL†

VCC
Analog In 50%
GND
6
tPLH tPHL
8

Analog Out 50%

† Includes all probe and jig capacitance

Figure 11. Propagation Delays, Figure 12. Propagation-Delay Test Setup,

Analog In to Analog Out Analog In to Analog Out

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265




       
 
  
SCLS542B − SEPTEMBER 2003 − REVISED JANUARY 2004

PARAMETER MEASUREMENT INFORMATION

tf tf Position 1 when testing tPHZ and tPZH

VCC 1 Position 2 when testing tPLZ and tPZL
90%
Enable 50% 2
10% VCC
GND VCC 16
10 kΩ
tPZL tPLZ
Analog I/O
High 1 Test
ON/OFF
Impedance 2 Point
Analog 50 % CL
10%
Out VOL
tPZH tPHZ
Enable
VOH 6
Analog 90%
50 %
Out High 8
Impedance

Figure 13. Propagation Delays, Figure 14. Propagation-Delay Test Setup,

Enable to Analog Out Enable to Analog Out

A VCC
VCC 16

ON/OFF Common O/I

Analog I/O NC
OFF/ON

VCC
6

8 11

Channel Select

Figure 15. Power-Dissipation Capacitance Test Setup

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

 PACKAGE OPTION ADDENDUM
www.ti.com 6-Dec-2006

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
SN74HC4851D ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC4851DE4 ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC4851DGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC4851DGVRE4 ACTIVE TVSOP DGV 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC4851DR ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC4851DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC4851N ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
SN74HC4851NE4 ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
SN74HC4851PW ACTIVE TSSOP PW 16 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC4851PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC4851PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC4851PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM
www.ti.com 6-Dec-2006

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 2
 MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23
0,40 0,07 M
0,13
24 13

0,16 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25

0°–
8°
0,75
1 12
0,50
A

Seating Plane

0,15
1,20 MAX 0,08
0,05

PINS **
14 16 20 24 38 48 56
DIM

A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40

A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30
0,65 0,10 M
0,19
14 8

0,15 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25
1 7
0°– 8°
A 0,75
0,50

Seating Plane

1,20 MAX 0,15 0,10

0,05

PINS **
8 14 16 20 24 28
DIM

A MAX 3,10 5,10 5,10 6,60 7,90 9,80

A MIN 2,90 4,90 4,90 6,40 7,70 9,60

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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