CD54HC4066, CD74HC4066,

CD74HCT4066
Data sheet acquired from Harris Semiconductor
SCHS208D
High-Speed CMOS Logic
February 1998 - Revised August 2003 Quad Bilateral Switch

Features Description
• Wide Analog-Input-Voltage Range . . . . . . . . . . 0V - 10V The ’HC4066 and CD74HCT4066 contain four independent
digitally controlled analog switches that use silicon-gate
[ /Title • Low “ON” Resistance
CMOS technology to achieve operating speeds similar to
(CD74H - VCC = 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25Ω LSTTL with the low power consumption of standard CMOS
C4066, - VCC = 9V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Ω integrated circuits.
CD74H • Fast Switching and Propagation Delay Times These switches feature the characteristic linear “ON”
CT4066 resistance of the metal-gate CD4066B. Each switch is
• Low “OFF” Leakage Current
turned on by a high-level voltage on its control input.
) • Wide Operating Temperature Range . . . -55oC to 125oC
/Subject Ordering Information
• HC Types
(High-
- 2V to 10V Operation TEMP. RANGE
Speed - High Noise Immunity: NIL = 30%, NIH = 30% of VCC PART NUMBER (oC) PACKAGE
CMOS at VCC = 5V and 10V CD54HC4066F3A -55 to 125 14 Ld CERDIP
Logic
• HCT Types CD74HC4066E -55 to 125 14 Ld PDIP
Quad - Direct LSTTL Input Logic Compatibility, CD74HC4066M -55 to 125 14 Ld SOIC
VIL= 0.8V (Max), VIH = 2V (Min)
CD74HC4066MT -55 to 125 14 Ld SOIC
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
CD74HC4066M96 -55 to 125 14 Ld SOIC

CD74HC4066PW -55 to 125 14 Ld TSSOP

CD74HC4066PWR -55 to 125 14 Ld TSSOP

CD74HC4066PWT -55 to 125 14 Ld TSSOP

CD74HCT4066E -55 to 125 14 Ld PDIP

CD74HCT4066M -55 to 125 14 Ld SOIC

CD74HCT4066MT -55 to 125 14 Ld SOIC

CD74HCT4066M96 -55 to 125 14 Ld SOIC

NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.

Pinout
CD54HC4066 (CERDIP)
CD74HC4066 (PDIP, SOIC, TSSOP)
CD74HCT4066 (PDIP, SOIC)
TOP VIEW

1Y 1 14 VCC

1Z 2 13 1E

2Z 3 12 4E

2Y 4 11 4Y

2E 5 10 4Z

3E 6 9 3Z

GND 7 8 3Y

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
 CD54HC4066, CD74HC4066, CD74HCT4066

Functional Diagram
13 1
1Y
1E
2
1Z
5 4
2E 2Y
3
2Z
6 8
3E 3Y
9
3Z
12 11
4E 4Y
10
4Z
GND = 7
VCC = 14

TRUTH TABLE

INPUT
nE SWITCH

L Off

H On

H= High Level
L= Low Level

Logic Diagram

nY

p
n nZ

nE

2
 CD54HC4066, CD74HC4066, CD74HCT4066

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC Thermal Resistance (Typical, Note 2) θJA
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 80oC/W
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 10.5V M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 86oC/W
DC Input Diode Current, IIK PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . 113oC/W
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC
DC Switch Current, IO (Note 1) Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
DC Output Diode Current, IOK Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA (SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 10V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. In certain applications, the external load-resistor current may include both VCC and signal-line components. To avoid drawing VCC current
when switch current flows into the transmission gate inputs, (terminals 1, 4, 8 and 11) the voltage drop across the bidirectional switch
must not exceed 0.6V (calculated from RON values shown in the DC Electrical Specifications Table). No VCC current will flow through
RLif the switch current flows into terminals 2, 3, 9 and 10.
2. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Specifications
TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
PARAMETER SYMBOL VI (V) VIS (V) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V
Voltage
4.5 3.15 - - 3.15 - 3.15 - V
9 6.3 - - 6.3 - 6.3 - V
Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V
Voltage
4.5 - - 1.35 - 1.35 - 1.35 V
9 - - 2.7 - 2.7 - 2.7 V
Input Leakage IIL VCC or - 10 - - ±0.1 - ±1 - ±1 µA
Current GND
(Any Control)
Off-Switch Leakage IZ VIL VCC or 10 - - ±0.1 - ±1 - ±1 µA
Current GND

3
 CD54HC4066, CD74HC4066, CD74HCT4066

DC Electrical Specifications (Continued)

TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
PARAMETER SYMBOL VI (V) VIS (V) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS
“ON” Resistance RON VCC VCC or 4.5 - 25 80 - 106 - 128 Ω
IO = 1mA GND
6 - 20 75 - 94 - 113 Ω
(Figure 1)
9 - 15 60 - 78 - 95 Ω
VCC to 4.5 - 35 95 - 118 - 142 Ω
GND
6 - 24 84 - 105 - 126 Ω
9 - 16 70 - 88 - 105 Ω
“ON” Resistance ∆RON VCC - 4.5 - 1 - - - - - Ω
Between Any Two
6 - 0.75 - - - - - Ω
Switches
9 - 0.5 - - - - - Ω
Quiescent Device ICC VCC or - 6 - - 2 - 20 - 40 µA
Current GND
10 - - 16 - 160 - 320 µA
HCT TYPES
High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V
Voltage 5.5
Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V
Voltage 5.5
Input Leakage IIL VCC or - 5.5 - - ±0.1 - ±1 - ±1 µA
Current GND
(Any Control)
Off-Switch Leakage IZ VIL VCC or 5.5 - - ±0.1 - ±1 - ±1 µA
Current GND
“ON” Resistance RON VCC VCC or 4.5 - 25 80 - 106 - 128 Ω
IO = 1mA GND
(Figure 1)
VCC to 4.5 - 35 95 - 118 - 142 Ω
GND
“ON” Resistance ∆RON VCC - 4.5 - 1 - - - - - Ω
Between Any Two
Switches
Quiescent Device ICC VCC or - 5.5 - - 2 - 20 - 40 µA
Current GND
Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA
Device Current Per (Note 3) - 2.1 5.5
Input Pin: 1 Unit Load
NOTE:
3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

HCT Input Loading Table

INPUT UNIT LOADS
All 1
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifica-
tions table, e.g., 360µA max at 25oC.

4
 CD54HC4066, CD74HC4066, CD74HCT4066

Switching Specifications Input tr, tf = 6ns

25oC -40oC TO 85oC -55oC TO 125oC
TEST VCC
PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
Propagation Delay Time tPLH, tPHL CL = 50pF 2 - - 60 - 75 - 90 ns
Switch In to Out
4.5 - - 12 - 15 - 18 ns
9 - - 8 - 11 - 13 ns
CL = 15pF 5 - 4 - - - - - ns
Propagation Delay Time tPZH, tPZL CL = 50pF 2 - - 100 - 125 - 150 ns
Switch Turn On Delay
4.5 - - 20 - 25 - 30 ns
9 - - 12 - 15 - 18 ns
CL = 15pF 5 - 8 - - - - - ns
Propagation Delay Time tPHZ, tPLZ CL = 50pF 2 - - 150 - 190 - 225 ns
Switch Turn Off Delay
4.5 - - 30 - 38 - 45 ns
9 - - 24 - 30 - 36 ns
CL = 15pF 5 - 12 - - - - - ns
Input (Control) Capacitance CI - - - - 10 - 10 - 10 pF
Power Dissipation Capacitance CPD - 5 - 25 - - - - - pF
(Notes 4, 5)
HCT TYPES
Propagation Delay Time tPLH, tPHL CL = 50pF 4.5 - - 12 - 15 - 18 ns
Switch In to Out
CL = 15pF 5 - 4 - - - - - ns
Propagation Delay Time tPZH, tPZL CL = 50pF 4.5 - - 24 - 30 - 36 ns
Switch Turn On Delay
CL = 15pF 5 - 9 - - - - - ns
Propagation Delay Time tPHZ, tPLZ CL = 50pF 4.5 - - 35 - 44 - 53 ns
Switch Turn Off Delay
CL = 15pF 5 - 14 - - - - - ns
Input (Control) Capacitance CI - - - - 10 - 10 - 10 pF
Power Dissipation Capacitance CPD - 5 - 38 - - - - - pF
(Notes 4, 5)
NOTES:
4. CPD is used to determine the dynamic power consumption, per package.
5. PD = CPD VCC2 fi + Σ (CL + CS) VCC2 fo where fi = input frequency, fo = output frequency, CL = output load capacitance, CS = switch
capacitance, VCC = supply voltage.

Analog Channel Specifications TA = 25oC

PARAMETER TEST CONDITIONS VCC (V) HC4066 CD74HCT4066 UNITS

Switch Frequency Response Bandwidth at -3dB Figure 5, Notes 6, 7 4.5 200 200 MHz
Figure 2

Cross Talk Between Any Two Switches Figure 3 Figure 4, Notes 7, 8 4.5 -72 -72 dB

Total Harmonic Distortion Figure 6, 1kHz, 4.5 0.022 0.023 %

VIS = 4VP-P

Figure 6, 1kHz, 9 0.008 N/A %

VIS = 8VP-P

5
 CD54HC4066, CD74HC4066, CD74HCT4066

Analog Channel Specifications TA = 25oC (Continued)

PARAMETER TEST CONDITIONS VCC (V) HC4066 CD74HCT4066 UNITS

Control to Switch Feedthrough Noise Figure 7 4.5 200 130 mV

9 550 N/A mV

Switch “OFF” Signal Feedthrough Figure 3 Figure 8, Notes 7, 8 4.5 -72 -72 dB

Switch Input Capacitance, CS - 5 5 pF

NOTES:
6. Adjust input level for 0dBm at output, f = 1MHz.
7. VIS is centered at VCC/2.
8. Adjust input for 0dBm at VIS.

Typical Performance Curves

TA = 25oC, GND = 0V
50

CHANNEL-ON BANDWIDTH, dB
“ON” RESISTANCE, RON (Ω)

0
40
VCC = 4.5V, PIN 1 TO 2
-1
30

-2
20 VCC = 9V, PIN 1 TO 3
CL = 10pF
-3 VCC = 4.5V
10
RL = 50Ω
TA = 25oC
0 PIN 4 TO 3
0 1 2 3 4 4.5 5 6 7 8 9 10 -4
104 105 106 107 108
INPUT SIGNAL VOLTAGE, VIS (V)
FREQUENCY, f (Hz)

FIGURE 1. TYPICAL “ON” RESISTANCE vs INPUT SIGNAL FIGURE 2. SWITCH FREQUENCY RESPONSE, VCC = 4.5V
VOLTAGE

0
SWITCH-OFF SIGNAL FEEDTHROUGH, dB

CL = 10pF
VCC = 4.5V
RL = 50Ω
-20 TA = 25oC
PIN 4 TO 3
CROSSTALK, dB

-40

-60

-80

-100
104 105 106 107 108
FREQUENCY, f (Hz)

FIGURE 3. SWITCH-OFF SIGNAL FEEDTHROUGH AND CROSSTALK vs FREQUENCY, VCC = 4.5V

6
 CD54HC4066, CD74HC4066, CD74HCT4066

Analog Test Circuits

VIS VCC
VCC

0.1µF
SWITCH R VOS2
VIS VOS1 SWITCH
ON
R OFF
R C
VCC/2 R C
dB
VCC/2 METER
VCC/2
fIS = 1MHz SINEWAVE
R = 50Ω
C = 10pF

FIGURE 4. CROSSTALK BETWEEN TWO SWITCHES TEST CIRCUIT

VCC VCC

SINE VIS
0.1µF VOS WAVE 10µF VI = VIH
SWITCH SWITCH
VIS VIS ON
ON VOS
50Ω 10pF 10kΩ 50pF
dB DISTORTION
METER METER
VCC/2 VCC/2

fIS = 1kHz TO 10kHz

FIGURE 5. FREQUENCY RESPONSE TEST CIRCUIT FIGURE 6. TOTAL HARMONIC DISTORTION TEST CIRCUIT

E fIS ≥ 1MHz SINEWAVE

VCC VCC R = 50Ω
VC = VIL
VP-P C = 10pF
VOS 0.1µF
600Ω SWITCH VOS
ALTERNATING SWITCH
ON AND OFF VIS OFF
VOS
tr, tf ≤ 6ns 600Ω
VCC/2 fCONT = 1MHz 50pF R R C
50% DUTY dB
CYCLE SCOPE METER
VCC/2 VCC/2 VCC/2

FIGURE 7. CONTROL-TO-SWITCH FEEDTHROUGH NOISE FIGURE 8. SWITCH OFF SIGNAL FEEDTHROUGH

TEST CIRCUIT

Test Circuits and Waveforms

tr = 6ns tf = 6ns tr = 6ns tf = 6ns

VCC 3V
90% 2.7V
INPUT 50% INPUT 1.3V
10% GND 0.3V GND

tTHL tTLH tTHL tTLH

90% 90%
50% 1.3V
INVERTING 10% INVERTING
10%
OUTPUT OUTPUT
tPHL tPLH tPHL tPLH

FIGURE 9. HC TRANSITION TIMES AND PROPAGATION FIGURE 10. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC

7
 PACKAGE OPTION ADDENDUM

www.ti.com 2-Dec-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-8950701CA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8950701CA Samples
& Green CD54HC4066F3A
CD54HC4066F3A ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8950701CA Samples
& Green CD54HC4066F3A
CD74HC4066E LIFEBUY PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC4066E
CD74HC4066EE4 LIFEBUY PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC4066E
CD74HC4066M LIFEBUY SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4066M
CD74HC4066M96 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4066M Samples

CD74HC4066M96E4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4066M Samples

CD74HC4066ME4 LIFEBUY SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4066M
CD74HC4066MG4 LIFEBUY SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4066M
CD74HC4066MT LIFEBUY SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4066M
CD74HC4066PW LIFEBUY TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HP4066
CD74HC4066PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HP4066 Samples

CD74HC4066PWT LIFEBUY TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HP4066
CD74HCT4066E LIFEBUY PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4066E
CD74HCT4066M LIFEBUY SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4066M
CD74HCT4066M96 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4066M Samples

CD74HCT4066MT LIFEBUY SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4066M

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 2-Dec-2023

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC4066, CD74HC4066, CD74HCT4066 :

• Catalog : CD74HC4066
• Automotive : CD74HCT4066-Q1
• Military : CD54HC4066

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Military - QML certified for Military and Defense Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-Jul-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC4066M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD74HC4066MT SOIC D 14 250 180.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD74HC4066PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC4066PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HCT4066M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD74HCT4066MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-Jul-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC4066M96 SOIC D 14 2500 356.0 356.0 35.0
CD74HC4066MT SOIC D 14 250 210.0 185.0 35.0
CD74HC4066PWR TSSOP PW 14 2000 356.0 356.0 35.0
CD74HC4066PWT TSSOP PW 14 250 356.0 356.0 35.0
CD74HCT4066M96 SOIC D 14 2500 356.0 356.0 35.0
CD74HCT4066MT SOIC D 14 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-Jul-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD74HC4066E N PDIP 14 25 506 13.97 11230 4.32
CD74HC4066E N PDIP 14 25 506 13.97 11230 4.32
CD74HC4066EE4 N PDIP 14 25 506 13.97 11230 4.32
CD74HC4066EE4 N PDIP 14 25 506 13.97 11230 4.32
CD74HC4066M D SOIC 14 50 506.6 8 3940 4.32
CD74HC4066ME4 D SOIC 14 50 506.6 8 3940 4.32
CD74HC4066MG4 D SOIC 14 50 506.6 8 3940 4.32
CD74HC4066PW PW TSSOP 14 90 530 10.2 3600 3.5
CD74HCT4066E N PDIP 14 25 506 13.97 11230 4.32
CD74HCT4066E N PDIP 14 25 506 13.97 11230 4.32
CD74HCT4066M D SOIC 14 50 506.6 8 3940 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

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 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

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