CD54/74HC640,

CD54/74HCT640
Data sheet acquired from Harris Semiconductor
SCHS192A
High Speed CMOS Logic
January 1998 - Revised May 2000 Octal Three-State Bus Transceiver, Inverting

Features Description
• Buffered Inputs The ’HC640 and ’HCT640 silicon-gate CMOS three-state
bidirectional inverting and non-inverting buffers are intended
[ /Title • Three-State Outputs
for two-way asynchronous communication between data
(CD74 • Applications in Multiple-Data-Bus Architecture buses. They have high drive current outputs which enable
HC640 high-speed operation when driving large bus capacitances.
• Fanout (Over Temperature Range) These circuits possess the low power dissipation of CMOS
, - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads circuits, and have speeds comparable to low power Schottky
CD74 - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads TTL circuits. They can drive 15 LSTTL loads. The ’HC640
HCT64 • Wide Operating Temperature Range . . . -55oC to 125oC
and ’HCT640 are inverting buffers.
0) The direction of data flow (A to B, B to A) is controlled by the
• Balanced Propagation Delay and Transition Times
/Sub- DIR input.
ject • Significant Power Reduction Compared to LSTTL
Outputs are enabled by a low on the Output Enable input
Logic ICs
(High (OE); a high OE puts these devices in the high impedance
Speed • HC Types mode.

CMOS - 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC Ordering Information
at VCC = 5V
TEMP. RANGE
• HCT Types PART NUMBER (oC) PACKAGE
- 4.5V to 5.5V Operation CD54HC640F3A -55 to 125 20 Ld CERDIP
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min) CD74HC640E -55 to 125 20 Ld PDIP
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH CD54HCT640F3A -55 to 125 20 Ld CERDIP

CD74HCT640E -55 to 125 20 Ld PDIP

Pinout CD74HCT640M -55 to 125 20 Ld SOIC
CD54HC640, CD54HCT640 NOTE:
(CERDIP)
1. Wafer and die for this part number is available which meets all
CD74HC640, CD74HCT640
electrical specifications. Please contact your local TI sales office
(PDIP, SOIC)
TOP VIEW or customer service for ordering information.

DIR 1 20 VCC
A0 2 19 OE
A1 3 18 B0
A2 4 17 B1
A3 5 16 B2
A4 6 15 B3
A5 7 14 B4
A6 8 13 B5
A7 9 12 B6
GND 10 11 B7

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2000, Texas Instruments Incorporated
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 CD54/74HC640, CD54/74HCT640

Functional Diagram

A0 B0

A1 B1
THRU THRU
A6 B6

A7 B7

OE OUTPUT ENABLE AND

DIRECTION-SELECT LOGIC VCC = 20
DIR
GND = 10

TRUTH TABLE

CONTROL INPUTS DATA PORT STATUS

OE DIR An Bn

L L O I

H H Z Z

H L Z Z

L H I O

To prevent excess currents in the High-Z modes all I/O terminals

should be terminated with 1kΩ to 1MΩ resistors.
H = High Level
L = Low Level
I = Input
O = Output (Inversion of Input Level)
Z = High Impedance

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 CD54/74HC640, CD54/74HCT640

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 2) θJA (oC/W)
DC Input Diode Current, IIK PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
DC Output Diode Current, IOK Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
DC Drain Current, per Output, IO Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA (SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
2. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications
TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V
Voltage
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V
Voltage
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
Voltage
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
CMOS Loads
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output - - - - - - - - - V
Voltage
-6 4.5 3.98 - - 3.84 - 3.7 - V
TTL Loads
-7.8 6 5.48 - - 5.34 - 5.2 - V
Low Level Output VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
Voltage
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
CMOS Loads
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output - - - - - - - - - V
Voltage
6 4.5 - - 0.26 - 0.33 - 0.4 V
TTL Loads
7.8 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA
Current GND

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 CD54/74HC640, CD54/74HCT640

DC Electrical Specifications (Continued)

TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA
Current GND
Three-State Leakage IOZ VIL or VIH VO = 6 - - ±0.5 - ±5 - ±10 µA
Current VCC or
GND
HCT TYPES
High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V
Voltage 5.5
Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V
Voltage 5.5
High Level Output VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
Voltage
CMOS Loads
High Level Output -6 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads
Low Level Output VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Voltage
CMOS Loads
Low Level Output 6 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads
Input Leakage II VCC and 0 5.5 - - ±0.1 - ±1 - ±1 µA
Current GND
Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA
Current GND
Three-State Leakage IOZ VIL or VIH VO = 5.5 - - ±0.5 - ±5 - ±10 µA
Current VCC or
GND
Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA
Device Current Per -2.1 5.5
Input Pin: 1 Unit Load
NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

HCT Input Loading Table

INPUT UNIT LOADS

DIR 0.9

OE, A 1.5

B 1.5

NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,

360µA max at 25oC.

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 CD54/74HC640, CD54/74HCT640

Switching Specifications CL = 50pF, Input tr, tf = 6ns

-40oC TO -55oC TO
25oC 85oC 125oC
TEST
PARAMETER SYMBOL CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS

HC TYPES

Propagation Delay tPHL, tPLH CL = 50pF

A to B 2 - - 90 - 115 - 135 ns
B to A
4.5 - - 18 - 23 - 27 ns

CL = 15pF 5 - 7 - - - - - ns

CL = 50pF 6 - - 15 - 20 - 23 ns

Output High-Z tPHL, tPLH CL = 50pF 2 - - 150 - 190 - 225 ns

To High Level,
To Low Level 4.5 - - 30 - 38 - 45 ns

CL = 15pF 5 - 12 - - - - - ns

CL = 50pF 6 - - 26 - 33 - 38 ns

Output High Level tPHZ, tPLZ CL = 50pF 2 - - 150 - 190 - 225 ns

Output Low Level to High Z
4.5 - - 30 - 38 - 45 ns

CL = 15pF 5 - 12 - - - - - ns

CL = 50pF 6 - - 26 - 33 - 38 ns

Output Transition Time tTHL, tTLH CL = 50pF 2 - - 60 - 75 - 90 ns

4.5 - - 12 - 15 - 18 ns

6 - - 10 - 13 - 15 ns

Input Capacitance CIN CL = 50pF - 10 - 10 - 10 - 10 pF

Three-State Output CO - - - - 20 - 20 - 20 pF
Capacitance

Power Dissipation Capacitance CPD - 5 - 38 - - - - - pF

(Notes 3, 4)

HCT TYPES

Propagation Delay
A to B tPHL, tPLH CL = 50pF 4.5 - - 22 - 28 - 33 ns
B to A
CL = 15pF 5 - 9 - - - - - ns

Output High-Z tPHL, tPLH CL = 50pF 4.5 - - 30 - 38 - 45 ns

To High Level,
To Low Level CL = 15pF 5 - 12 - - - - - ns

Output High Level tPHZ, tPLZ CL = 50pF 4.5 - - 30 - 38 - 45 ns

Output Low Level to High Z
CL = 15pF 5 - 12 - - - - - ns

Output Transition Time tTHL, tTLH CL = 50pF 4.5 - - 12 - 15 - 18 ns

Input Capacitance CIN CL = 50pF - 10 - 10 - 10 - 10 pF

Three-State Output CO - - - - 20 - 20 - 20 pF
Capacitance

Power Dissipation Capacitance CPD - 5 - 41 - - - - - pF

(Notes 3, 4)

NOTES:
3. CPD is used to determine the dynamic power consumption, per channel.
4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

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 CD54/74HC640, CD54/74HCT640

Test Circuits and Waveforms

tr = 6ns tf = 6ns tr = 6ns tf = 6ns

VCC 3V
90% 2.7V
INPUT 50% INPUT 1.3V
10% GND 0.3V GND

tTHL tTLH tTHL tTLH

90% 90%
50% 1.3V
INVERTING 10% INVERTING
10%
OUTPUT OUTPUT
tPHL tPLH tPHL tPLH

FIGURE 1. HC TRANSITION TIMES AND PROPAGATION FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC

6ns 6ns tr 6ns tf 6ns

OUTPUT VCC OUTPUT 3V
90% 2.7
DISABLE 50% DISABLE 1.3
10% 0.3
GND GND
tPLZ tPZL tPLZ tPZL

OUTPUT LOW OUTPUT LOW

TO OFF 50% TO OFF
10% 10% 1.3V

tPHZ tPZH tPHZ

tPZH
90% 90%
OUTPUT HIGH 50% OUTPUT HIGH
TO OFF TO OFF 1.3V

OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS

ENABLED DISABLED ENABLED ENABLED DISABLED ENABLED

FIGURE 3. HC THREE-STATE PROPAGATION DELAY FIGURE 4. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM WAVEFORM

OTHER OUTPUT
INPUTS IC WITH RL = 1kΩ
TIED HIGH THREE- VCC FOR tPLZ AND tPZL
OR LOW STATE CL GND FOR tPHZ AND tPZH
OUTPUT 50pF
OUTPUT
DISABLE

NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to
VCC, CL = 50pF.
FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

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