Quadruple Bus Buffer Gate With 3-State Outputs: Features
Quadruple Bus Buffer Gate With 3-State Outputs: Features
1OE
VCC
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
1 14
– 200-V Machine Model (A115-A)
1A 2 13 4OE
– 1000-V Charged-Device Model (C101) 1Y 3 12 4A
2OE 4 11 4Y
2A 5 10 3OE
2Y 6 9 3A
7
GND 8
3Y
DESCRIPTION/ORDERING INFORMATION
This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC125A features independent line drivers with 3-state outputs. Each output is disabled when the
associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 1993–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVC125A
ORDERING INFORMATION
TA PACKAGE (1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
–40°C to 85°C QFN – RGY Reel of 1000 SN74LVC125ARGYR LC125A
Tube of 50 SN74LVC125AD
SOIC – D Reel of 2500 SN74LVC125ADRG3 LVC125A
Reel of 250 SN74LVC125ADT
SOP – NS Reel of 2000 SN74LVC125ANSR LVC125A
–40°C to 125°C
SSOP – DB Reel of 2000 SN74LVC125ADBR LC125A
Tube of 90 SN74LVC125APW
TSSOP – PW Reel of 2000 SN74LVC125APWRG3 LC125A
Reel of 250 SN74LVC125APWT
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
2 3 9 8
1A 1Y 3A 3Y
4 13
2OE 4OE
5 6 12 11
2A 2Y 4A 4Y
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) The package thermal impedance is calculated in accordance with JESD 51-5.
(6) For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K.
(7) For the DB, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5 mW/K.
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C –40°C to 85°C –40°C to 125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
IOH = –100 mA 1.65 V to 3.6 V VCC – 0.2 VCC – 0.2 VCC – 0.3
IOH = –4 mA 1.65 V 1.29 1.2 1.05
IOH = –8 mA 2.3 V 1.9 1.7 1.55
VOH V
2.7 V 2.2 2.2 2.05
IOH = –12 mA
3V 2.4 2.4 2.25
IOH = –24 mA 3V 2.3 2.2 2
IOL = 100 mA 1.65 V to 3.6 V 0.1 0.2 0.3
IOL = 4 mA 1.65 V 0.24 0.45 0.6
VOL IOL = 8 mA 2.3 V 0.3 0.7 0.75 V
IOL = 12 mA 2.7 V 0.4 0.4 0.6
IOL = 24 mA 3V 0.55 0.55 0.8
II VI = 5.5 V or GND 3.6 V ±1 ±5 ±20 mA
IOZ VO = VCC or GND 3.6 V ±1 ±10 ±20 mA
ICC VI = VCC or GND, IO = 0 3.6 V 1 10 40 mA
One input at VCC – 0.6 V,
ΔICC Other inputs at VCC or 2.7 V to 3.6 V 500 500 5000 mA
GND
Ci VI = VCC or GND 3.3 V 5 pF
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
FROM TO TA = 25°C –40°C to 85°C –40°C to 125°C
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
1.8 V ± 0.15 V 1 4.5 11.8 1 12.3 1 13.8
2.5 V ± 0.2 V 1 2.7 5.8 1 6.3 1 8.4
tpd A Y ns
2.7 V 1 3 5.3 1 5.5 1 7
3.3 V ± 0.3 V 1 2.5 4.6 1 4.8 1 6
1.8 V ± 0.15 V 1 4.3 13.8 1 14.3 1 15.8
2.5 V ± 0.2 V 1 2.7 6.9 1 7.4 1 9.5
ten OE Y ns
2.7 V 1 3.3 6.4 1 6.6 1 8.5
3.3 V ± 0.3 V 1 2.4 5.2 1 5.4 1 7
1.8 V ± 0.15 V 1 4.3 10.6 1 11.1 1 12.6
2.5 V ± 0.2 V 1 2.2 5.1 1 5.6 1 7.7
tdis OE Y ns
2.7 V 1 2.5 4.8 1 5 1 6.5
3.3 V ± 0.3 V 1 2.4 4.4 1 4.6 1 6
tsk(o) 3.3 V ± 0.3 V 1 1.5 ns
Operating Characteristics
TA = 25°C
TEST
PARAMETER VCC TYP UNIT
CONDITIONS
1.8 V 7.4
Cpd Power dissipation capacitance per gate f = 10 MHz 2.5 V 11.3 pF
3.3 V 15
LOAD CIRCUIT
INPUTS
VCC VM VLOAD CL RL V∆
VI tr/tf
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V
2.7 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V
3.3 V ± 0.3 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V
VI
Timing Input VM
0V
tw
VI tsu th
VI
Input VM VM
Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES
VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
Output
VOH VLOAD/2
Waveform 1
Output VM VM VM
S1 at VLOAD VOL + V∆
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
VOH Output
VOH
VM VM Waveform 2 VOH - V∆
Output VM
S1 at GND
VOL
(see Note B) ≈0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING
www.ti.com 10-Jun-2014
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
SN74LVC125AD ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI -40 to 125
SN74LVC125ADBR ACTIVE SSOP DB 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125ADE4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADG4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADR ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADRG3 ACTIVE SOIC D 14 2500 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADT ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADTG4 ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ANSR ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125APW ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 125
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2014
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
SN74LVC125APWR ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWRG3 ACTIVE TSSOP PW 14 2000 Green (RoHS CU SN Level-1-260C-UNLIM LC125A
& no Sb/Br)
SN74LVC125APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWT ACTIVE TSSOP PW 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125ARGYR ACTIVE VQFN RGY 14 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LC125A
& no Sb/Br)
SN74LVC125ARGYRG4 ACTIVE VQFN RGY 14 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LC125A
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2014
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
• Automotive: SN74LVC125A-Q1
• Enhanced Product: SN74LVC125A-EP
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Apr-2014
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Apr-2014
Pack Materials-Page 2
MECHANICAL DATA
0,38
0,65 0,15 M
0,22
28 15
0,25
0,09
5,60 8,20
5,00 7,40
Gage Plane
1 14 0,25
A 0°–ā8° 0,95
0,55
Seating Plane
PINS **
14 16 20 24 28 30 38
DIM
4040065 /E 12/01
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2014, Texas Instruments Incorporated