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Quadruple Bus Buffer Gate With 3-State Outputs: Features

The SN74LVC125A is a quadruple bus buffer gate with 3-state outputs, operating from 1.65 V to 3.6 V and specified for temperatures from -40°C to 125°C. It features independent line drivers, accepts input voltages up to 5.5 V, and is suitable for mixed 3.3-V/5-V systems. The device includes ESD protection and has a maximum propagation delay of 4.8 ns at 3.3 V.

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0% found this document useful (0 votes)
16 views20 pages

Quadruple Bus Buffer Gate With 3-State Outputs: Features

The SN74LVC125A is a quadruple bus buffer gate with 3-state outputs, operating from 1.65 V to 3.6 V and specified for temperatures from -40°C to 125°C. It features independent line drivers, accepts input voltages up to 5.5 V, and is suitable for mixed 3.3-V/5-V systems. The device includes ESD protection and has a maximum propagation delay of 4.8 ns at 3.3 V.

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SN74LVC125A

www.ti.com SCAS290P – JANUARY 1993 – REVISED OCTOBER 2010

QUADRUPLE BUS BUFFER GATE


WITH 3-STATE OUTPUTS
Check for Samples: SN74LVC125A

1FEATURES D, DB, NS, OR PW PACKAGE


• Operates From 1.65 V to 3.6 V (TOP VIEW)
• Specified From –40°C to 85°C
and –40°C to 125°C 1OE 1 14 VCC
• Inputs Accept Voltages to 5.5 V 1A 2 13 4OE
1Y 3 12 4A
• Max tpd of 4.8 ns at 3.3 V
2OE 4 11 4Y
• Typical VOLP (Output Ground Bounce) 5 10
2A 3OE
<0.8 V at VCC = 3.3 V, TA = 25°C 6 9
2Y 3A
• Typical VOHV (Output VOH Undershoot) GND 7 8 3Y
>2 V at VCC = 3.3 V, TA = 25°C
• Latch-Up Performance Exceeds 250 mA Per RGY PACKAGE
JESD 17 (TOP VIEW)

1OE

VCC
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
1 14
– 200-V Machine Model (A115-A)
1A 2 13 4OE
– 1000-V Charged-Device Model (C101) 1Y 3 12 4A
2OE 4 11 4Y
2A 5 10 3OE
2Y 6 9 3A
7
GND 8

3Y
DESCRIPTION/ORDERING INFORMATION
This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC125A features independent line drivers with 3-state outputs. Each output is disabled when the
associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 1993–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVC125A

SCAS290P – JANUARY 1993 – REVISED OCTOBER 2010 www.ti.com

ORDERING INFORMATION
TA PACKAGE (1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
–40°C to 85°C QFN – RGY Reel of 1000 SN74LVC125ARGYR LC125A
Tube of 50 SN74LVC125AD
SOIC – D Reel of 2500 SN74LVC125ADRG3 LVC125A
Reel of 250 SN74LVC125ADT
SOP – NS Reel of 2000 SN74LVC125ANSR LVC125A
–40°C to 125°C
SSOP – DB Reel of 2000 SN74LVC125ADBR LC125A
Tube of 90 SN74LVC125APW
TSSOP – PW Reel of 2000 SN74LVC125APWRG3 LC125A
Reel of 250 SN74LVC125APWT

(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.

Table 1. FUNCTION TABLE


(EACH BUFFER)
INPUTS OUTPUT
OE A Y
L H H
L L L
H X Z

LOGIC DIAGRAM (POSITIVE LOGIC)


1 10
1OE 3OE

2 3 9 8
1A 1Y 3A 3Y

4 13
2OE 4OE

5 6 12 11
2A 2Y 4A 4Y

2 Submit Documentation Feedback Copyright © 1993–2010, Texas Instruments Incorporated

Product Folder Link(s): SN74LVC125A


SN74LVC125A

www.ti.com SCAS290P – JANUARY 1993 – REVISED OCTOBER 2010

Absolute Maximum Ratings (1)


over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 V
(2)
VI Input voltage range –0.5 6.5 V
VO Output voltage range (2) (3)
–0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
D package (4) 86
DB package (4) 96
qJA Package thermal impedance NS package (4) 76 °C/W
PW package (4) 113
RGY package (5) 47
Tstg Storage temperature range –65 150 °C
Ptot Power dissipation TA = –40°C to 125°C (6) (7)
500 mW

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) The package thermal impedance is calculated in accordance with JESD 51-5.
(6) For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K.
(7) For the DB, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5 mW/K.

Recommended Operating Conditions (1)


TA = 25°C –40°C to 85°C –40°C to 125°C
UNIT
MIN MAX MIN MAX MIN MAX
Operating 1.65 3.6 1.65 3.6 1.65 3.6
VCC Supply voltage V
Data retention only 1.5 1.5 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC 0.65 × VCC 0.65 × VCC
High-level
VIH VCC = 2.3 V to 2.7 V 1.7 1.7 1.7 V
input voltage
VCC = 2.7 V to 3.6 V 2 2 2
VCC = 1.65 V to 1.95 V 0.35 × VCC 0.35 × VCC 0.35 × VCC
Low-level
VIL VCC = 2.3 V to 2.7 V 0.7 0.7 0.7 V
input voltage
VCC = 2.7 V to 3.6 V 0.8 0.8 0.8
VI Input voltage 0 5.5 0 5.5 0 5.5 V
VO Output voltage 0 VCC 0 VCC 0 VCC V
VCC = 1.65 V –4 –4 –4
High-level VCC = 2.3 V –8 –8 –8
IOH mA
output current VCC = 2.7 V –12 –12 –12
VCC = 3 V –24 –24 –24
VCC = 1.65 V 4 4 4
Low-level VCC = 2.3 V 8 8 8
IOL mA
output current VCC = 2.7 V 12 12 12
VCC = 3 V 24 24 24
Δt/Δv Input transition rise or fall rate 8 8 8 ns/V

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

Copyright © 1993–2010, Texas Instruments Incorporated Submit Documentation Feedback 3


Product Folder Link(s): SN74LVC125A
SN74LVC125A

SCAS290P – JANUARY 1993 – REVISED OCTOBER 2010 www.ti.com

Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C –40°C to 85°C –40°C to 125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
IOH = –100 mA 1.65 V to 3.6 V VCC – 0.2 VCC – 0.2 VCC – 0.3
IOH = –4 mA 1.65 V 1.29 1.2 1.05
IOH = –8 mA 2.3 V 1.9 1.7 1.55
VOH V
2.7 V 2.2 2.2 2.05
IOH = –12 mA
3V 2.4 2.4 2.25
IOH = –24 mA 3V 2.3 2.2 2
IOL = 100 mA 1.65 V to 3.6 V 0.1 0.2 0.3
IOL = 4 mA 1.65 V 0.24 0.45 0.6
VOL IOL = 8 mA 2.3 V 0.3 0.7 0.75 V
IOL = 12 mA 2.7 V 0.4 0.4 0.6
IOL = 24 mA 3V 0.55 0.55 0.8
II VI = 5.5 V or GND 3.6 V ±1 ±5 ±20 mA
IOZ VO = VCC or GND 3.6 V ±1 ±10 ±20 mA
ICC VI = VCC or GND, IO = 0 3.6 V 1 10 40 mA
One input at VCC – 0.6 V,
ΔICC Other inputs at VCC or 2.7 V to 3.6 V 500 500 5000 mA
GND
Ci VI = VCC or GND 3.3 V 5 pF

Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
FROM TO TA = 25°C –40°C to 85°C –40°C to 125°C
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
1.8 V ± 0.15 V 1 4.5 11.8 1 12.3 1 13.8
2.5 V ± 0.2 V 1 2.7 5.8 1 6.3 1 8.4
tpd A Y ns
2.7 V 1 3 5.3 1 5.5 1 7
3.3 V ± 0.3 V 1 2.5 4.6 1 4.8 1 6
1.8 V ± 0.15 V 1 4.3 13.8 1 14.3 1 15.8
2.5 V ± 0.2 V 1 2.7 6.9 1 7.4 1 9.5
ten OE Y ns
2.7 V 1 3.3 6.4 1 6.6 1 8.5
3.3 V ± 0.3 V 1 2.4 5.2 1 5.4 1 7
1.8 V ± 0.15 V 1 4.3 10.6 1 11.1 1 12.6
2.5 V ± 0.2 V 1 2.2 5.1 1 5.6 1 7.7
tdis OE Y ns
2.7 V 1 2.5 4.8 1 5 1 6.5
3.3 V ± 0.3 V 1 2.4 4.4 1 4.6 1 6
tsk(o) 3.3 V ± 0.3 V 1 1.5 ns

Operating Characteristics
TA = 25°C
TEST
PARAMETER VCC TYP UNIT
CONDITIONS
1.8 V 7.4
Cpd Power dissipation capacitance per gate f = 10 MHz 2.5 V 11.3 pF
3.3 V 15

4 Submit Documentation Feedback Copyright © 1993–2010, Texas Instruments Incorporated

Product Folder Link(s): SN74LVC125A


SN74LVC125A

www.ti.com SCAS290P – JANUARY 1993 – REVISED OCTOBER 2010

PARAMETER MEASUREMENT INFORMATION


VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
RL tPLZ/tPZL VLOAD
(see Note A)
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL V∆
VI tr/tf
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V
2.7 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V
3.3 V ± 0.3 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V

VI
Timing Input VM
0V
tw

VI tsu th
VI
Input VM VM
Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
Output
VOH VLOAD/2
Waveform 1
Output VM VM VM
S1 at VLOAD VOL + V∆
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
VOH Output
VOH
VM VM Waveform 2 VOH - V∆
Output VM
S1 at GND
VOL
(see Note B) ≈0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.


B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

Copyright © 1993–2010, Texas Instruments Incorporated Submit Documentation Feedback 5


Product Folder Link(s): SN74LVC125A
PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2014

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN74LVC125AD ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI -40 to 125
SN74LVC125ADBR ACTIVE SSOP DB 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125ADE4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADG4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADR ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADRG3 ACTIVE SOIC D 14 2500 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADT ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADTG4 ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ANSR ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125APW ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 125

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2014

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN74LVC125APWR ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWRG3 ACTIVE TSSOP PW 14 2000 Green (RoHS CU SN Level-1-260C-UNLIM LC125A
& no Sb/Br)
SN74LVC125APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWT ACTIVE TSSOP PW 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125ARGYR ACTIVE VQFN RGY 14 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LC125A
& no Sb/Br)
SN74LVC125ARGYRG4 ACTIVE VQFN RGY 14 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LC125A
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 2
PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2014

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC125A :

• Automotive: SN74LVC125A-Q1
• Enhanced Product: SN74LVC125A-EP

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 3
PACKAGE MATERIALS INFORMATION

www.ti.com 29-Apr-2014

TAPE AND REEL INFORMATION

*All dimensions are nominal


Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC125ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74LVC125ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC125ADR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1
SN74LVC125ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC125ADRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1
SN74LVC125ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC125ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC125ADT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC125ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LVC125APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC125APWRG3 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC125APWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC125ARGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 29-Apr-2014

*All dimensions are nominal


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC125ADBR SSOP DB 14 2000 367.0 367.0 38.0
SN74LVC125ADR SOIC D 14 2500 333.2 345.9 28.6
SN74LVC125ADR SOIC D 14 2500 364.0 364.0 27.0
SN74LVC125ADR SOIC D 14 2500 367.0 367.0 38.0
SN74LVC125ADRG3 SOIC D 14 2500 364.0 364.0 27.0
SN74LVC125ADRG4 SOIC D 14 2500 333.2 345.9 28.6
SN74LVC125ADRG4 SOIC D 14 2500 367.0 367.0 38.0
SN74LVC125ADT SOIC D 14 250 367.0 367.0 38.0
SN74LVC125ANSR SO NS 14 2000 367.0 367.0 38.0
SN74LVC125APWR TSSOP PW 14 2000 364.0 364.0 27.0
SN74LVC125APWRG3 TSSOP PW 14 2000 364.0 364.0 27.0
SN74LVC125APWRG4 TSSOP PW 14 2000 367.0 367.0 35.0
SN74LVC125ARGYR VQFN RGY 14 3000 367.0 367.0 35.0

Pack Materials-Page 2
MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE


28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.


B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
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supplied at the time of order acknowledgment.
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third party, or a license from TI under the patents or other intellectual property of TI.
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Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity

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