SN74LVC07A

www.ti.com SCAS595T – OCTOBER 1997 – REVISED FEBRUARY 2011

HEX BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS

Check for Samples: SN74LVC07A

1FEATURES
• Operates From 1.65 V to 5 V • Max tpd of 2.6 ns at 5 V
• Inputs and Open-Drain Outputs Accept • Latch-Up Performance Exceeds 250 mA Per
Voltages up to 5.5 V JESD 17

DESCRIPTION/ORDERING INFORMATION
This hex buffer/driver is designed for 1.65-V to 5.5-V VCC operation.
The outputs of the SN74LVC07A device are open drain and can be connected to other open-drain outputs to
implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 24 mA.
Inputs can be driven from 1.8-V, 2.5-V, 3.3-V (LVTTL), or 5-V (CMOS) devices. This feature allows the use of
this device as translators in a mixed-system environment.

ORDERING INFORMATION
TA PACKAGE (1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
QFN – RGY Reel of 1000 SN74LVC07ARGYR LC07A
Tube of 50 SN74LVC07AD
SOIC – D Reel of 2500 SN74LVC07ADRG3 LVC07A
Reel of 250 SN74LVC07ADT
SOP – NS Reel of 2000 SN74LVC07ANSR LVC07A
–40°C to 85°C
SSOP – DB Reel of 2000 SN74LVC07ADBR LC07A
Tube of 90 SN74LVC07APW
TSSOP – PW Reel of 2000 SN74LVC07APWRG3 LC07A
Reel of 250 SN74LVC07APWT
TVSOP – DGV Reel of 2000 SN74LVC07ADGVR LC07A

(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. © 1997–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVC07A

SCAS595T – OCTOBER 1997 – REVISED FEBRUARY 2011 www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

FUNCTION TABLE
(EACH BUFFER/DRIVER)
INPUT OUTPUT
A Y
H H
L L

LOGIC DIAGRAM, EACH BUFFER/DRIVER (POSITIVE LOGIC)

A Y

ABSOLUTE MAXIMUM RATINGS (1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 V
(2)
VI Input voltage range –0.5 6.5 V
VO Output voltage range –0.5 6.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

THERMAL INFORMATION
SN74LVC07A
THERMAL METRIC (1) (14) PINS UNITS
D DB DGV NS PW RGY
θJA Junction-to-ambient thermal resistance 120.8 135.1 157.7 120.3 151.5 79.4
θJCtop Junction-to-case (top) thermal resistance 79.7 86.7 78.3 76.3 77.6 95.7
θJB Junction-to-board thermal resistance 75.1 82.4 90.8 79 92.3 55.4
°C/W
ψJT Junction-to-top characterization parameter 37.2 43.7 21 36.2 21 16.4
ψJB Junction-to-board characterization parameter 74.8 81.9 90.1 78.7 92.7 55.6
θJCbot Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a n/a 34.8

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

2 Submit Documentation Feedback © 1997–2011, Texas Instruments Incorporated

Product Folder Link(s): SN74LVC07A

 SN74LVC07A

www.ti.com SCAS595T – OCTOBER 1997 – REVISED FEBRUARY 2011

RECOMMENDED OPERATING CONDITIONS (1)

MIN MAX UNIT
VCC Supply voltage 1.65 5.5 V
VCC = 1.65 V to 1.95 V 0.65 × VCC
VCC = 2.3 V to 2.7 V 1.7
VIH High-level input voltage V
VCC = 2.7 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × VCC
VCC = 1.65 V to 1.95 V 0.35 × VCC
VCC = 2.3 V to 2.7 V 0.7
VIL Low-level input voltage V
VCC = 2.7 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × VCC
VI Input voltage 0 5.5 V
VO Output voltage 0 5.5 V
VCC = 1.65 V 4
VCC = 2.3 V 12
IOL Low-level output current VCC = 2.7 V 12 mA
VCC = 3 V 24
VCC = 4.5 V 24
TA Operating free-air temperature –40 85 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP (1) MAX UNIT
IOL = 100 μA 1.65 V to 5.5 V 0.2
IOL = 4 mA 1.65 V 0.45
VOL 2.3 V 0.7 V
IOL = 12 mA
2.7 V 0.4
IOL = 24 mA 3V 0.55
II VI = 5.5 V or GND 3.6 V ±5 μA
Ioff VI or VO = 5.5 V 0V ±10 μA
ICC VI = VCC or GND, IO = 0 3.6 V 10 μA
ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND 2.7 V to 3.6 V 500 μA
Ci VI = VCC or GND 3.3 V 5 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 4)
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
FROM TO VCC = 2.7 V
PARAMETER ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V UNIT
(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
tpd A Y 1 5.6 1 3.4 3.3 1 3.6 1 2.6 ns

OPERATING CHARACTERISTICS
TA = 25°C
TEST VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
CONDITIONS TYP TYP TYP TYP
Power dissipation capacitance
Cpd f = 10 MHz 1.8 2 2.5 3.78 pF
per buffer/driver

© 1997–2011, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Link(s): SN74LVC07A
SN74LVC07A

SCAS595T – OCTOBER 1997 – REVISED FEBRUARY 2011 www.ti.com

PARAMETER MEASUREMENT INFORMATION

VCC = 1.8 V ± 0.15 V
2 × VCC
1 kΩ S1 Open
From Output
TEST S1
Under Test GND
tPZL (see Note F) 2 × VCC
CL = 30 pF
1 kΩ tPLZ (see Note G) 2 × VCC
(see Note A)
tPHZ/tPZH 2 × VCC

LOAD CIRCUIT
tw
VCC
VCC Input VCC/2 VCC/2
Timing
VCC/2 0V
Input
0V
VOLTAGE WAVEFORMS
PULSE DURATION
tsu th
VCC Output
Data VCC
VCC/2 VCC/2 Control
Input VCC/2 VCC/2
0V (low-level
enabling) 0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
tPZL tPLZ
Output VCC
VCC Waveform 1
Input VCC/2 VCC/2 S1 at 2 × VCC VCC/2 VOL + 0.15 V
0V (see Note B) VOL

tPLH tPHL tPZH tPHZ

Output VCC
VCC
Waveform 2 VCC − 0.15 V
Output VCC/2 VCC/2 VCC/2
S1 at 2 × VCC
VOL (see Note B) 0V

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at VCC/2.
G. tPLZ is measured at VOL + 0.15 V.
H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

4 Submit Documentation Feedback © 1997–2011, Texas Instruments Incorporated

Product Folder Link(s): SN74LVC07A

 SN74LVC07A

www.ti.com SCAS595T – OCTOBER 1997 – REVISED FEBRUARY 2011

PARAMETER MEASUREMENT INFORMATION

VCC = 2.5 V ± 0.2 V
2 × VCC
500 Ω S1 Open
From Output
TEST S1
Under Test GND
tPZL (see Note F) 2 × VCC
CL = 30 pF
500 Ω tPLZ (see Note G) 2 × VCC
(see Note A)
tPHZ/tPZH 2 × VCC

LOAD CIRCUIT
tw
VCC
VCC Input VCC/2 VCC/2
Timing
VCC/2 0V
Input
0V
VOLTAGE WAVEFORMS
PULSE DURATION
tsu th
VCC Output
Data VCC
VCC/2 VCC/2 Control
Input VCC/2 VCC/2
0V (low-level
enabling) 0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
tPZL tPLZ
Output VCC
VCC Waveform 1
Input VCC/2 VCC/2 S1 at 2 × VCC VCC/2 VOL + 0.15 V
0V (see Note B) VOL

tPLH tPHL tPZH tPHZ

Output VCC
VCC
Waveform 2 VCC − 0.15 V
Output VCC/2 VCC/2 VCC/2
S1 at 2 × VCC
VOL (see Note B) 0V

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at VCC/2.
G. tPLZ is measured at VOL + 0.15 V.
H. All parameters and waveforms are not applicable to all devices.

Figure 2. Load Circuit and Voltage Waveforms

© 1997–2011, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Link(s): SN74LVC07A
SN74LVC07A

SCAS595T – OCTOBER 1997 – REVISED FEBRUARY 2011 www.ti.com

PARAMETER MEASUREMENT INFORMATION

VCC = 2.7 and 3.3 V ± 0.3 V
6V
500 Ω S1 Open
From Output TEST S1
Under Test GND
tPZL (see Note F) 6V
CL = 50 pF tPLZ (see Note G) 6V
500 Ω
(see Note A)
tPHZ/tPZH 6V

LOAD CIRCUIT
tw
2.7 V
2.7 V Input 1.5 V 1.5 V
Timing
1.5 V 0V
Input
0V
VOLTAGE WAVEFORMS
PULSE DURATION
tsu th
2.7 V Output
Data 2.7 V
1.5 V 1.5 V Control
Input
0V (low-level 1.5 V 1.5 V
enabling) 0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
tPZL tPLZ
Output
2.7 V 3V
Waveform 1
Input 1.5 V 1.5 V S1 at 6 V 1.5 V VOL + 0.3 V
0V (see Note B) VOL

tPLH tPHL tPZH tPHZ

Output 3V
3V
Waveform 2 2.7 V
Output 1.5 V 1.5 V 1.5 V
S1 at 6 V
VOL (see Note B) 0V

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at 1.5 V.
G. tPLZ is measured at VOL + 0.3 V.
H. All parameters and waveforms are not applicable to all devices.

Figure 3. Load Circuit and Voltage Waveforms

6 Submit Documentation Feedback © 1997–2011, Texas Instruments Incorporated

Product Folder Link(s): SN74LVC07A

 SN74LVC07A

www.ti.com SCAS595T – OCTOBER 1997 – REVISED FEBRUARY 2011

PARAMETER MEASUREMENT INFORMATION

VCC = 5 V ± 0.5 V
2 x VCC
500 Ω
2 x VCC
2 x VCC
500 Ω 2 x VCC

Output
Waveform 1
S1 at 2 x VCC
(see Note B)

Output
Waveform 2
S1 at 2 x VCC 0.3 V
(see Note B)

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal connections such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal connections such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at VCC/2.
G. tPLZ is measured at VOL + 0.3 V.
H. All parameters and waveforms are not applicable to all devices.

Figure 4. Load Circuit and Voltage Waveforms

© 1997–2011, Texas Instruments Incorporated Submit Documentation Feedback 7

Product Folder Link(s): SN74LVC07A
 PACKAGE OPTION ADDENDUM

www.ti.com 20-Jan-2011

PACKAGING INFORMATION

Orderable Device Status

(1) Package Type Package Pins Package Qty Eco Plan
(2) Lead/ MSL Peak Temp
(3) Samples
Drawing Ball Finish (Requires Login)
SN74LVC07AD ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Purchase Samples
& no Sb/Br)
SN74LVC07ADBR ACTIVE SSOP DB 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
& no Sb/Br) or Sales Office
SN74LVC07ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
& no Sb/Br) or Sales Office
SN74LVC07ADE4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Purchase Samples
& no Sb/Br)
SN74LVC07ADG4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Purchase Samples
& no Sb/Br)
SN74LVC07ADGVR ACTIVE TVSOP DGV 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
& no Sb/Br) or Sales Office
SN74LVC07ADGVRE4 ACTIVE TVSOP DGV 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
& no Sb/Br) or Sales Office
SN74LVC07ADGVRG4 ACTIVE TVSOP DGV 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
& no Sb/Br) or Sales Office
SN74LVC07ADR ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
& no Sb/Br) or Sales Office
SN74LVC07ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
& no Sb/Br) or Sales Office
SN74LVC07ADRG3 ACTIVE SOIC D 14 2500 Green (RoHS CU SN Level-1-260C-UNLIM Request Free Samples
& no Sb/Br)
SN74LVC07ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
& no Sb/Br) or Sales Office
SN74LVC07ADT ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Purchase Samples
& no Sb/Br)
SN74LVC07ADTE4 ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Purchase Samples
& no Sb/Br)
SN74LVC07ADTG4 ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Purchase Samples
& no Sb/Br)
SN74LVC07ANSR ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Purchase Samples
& no Sb/Br)
SN74LVC07ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Purchase Samples
& no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 20-Jan-2011

Orderable Device Status

(1) Package Type Package Pins Package Qty Eco Plan
(2) Lead/ MSL Peak Temp
(3) Samples
Drawing Ball Finish (Requires Login)
SN74LVC07ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Purchase Samples
& no Sb/Br)
SN74LVC07APW ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Purchase Samples
& no Sb/Br)
SN74LVC07APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Purchase Samples
& no Sb/Br)
SN74LVC07APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Purchase Samples
& no Sb/Br)
SN74LVC07APWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI Samples Not Available
SN74LVC07APWR ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
& no Sb/Br) or Sales Office
SN74LVC07APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
& no Sb/Br) or Sales Office
SN74LVC07APWRG3 ACTIVE TSSOP PW 14 2000 Green (RoHS CU SN Level-1-260C-UNLIM Request Free Samples
& no Sb/Br)
SN74LVC07APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
& no Sb/Br) or Sales Office
SN74LVC07APWT ACTIVE TSSOP PW 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Purchase Samples
& no Sb/Br)
SN74LVC07APWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Purchase Samples
& no Sb/Br)
SN74LVC07APWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM Purchase Samples
& no Sb/Br)
SN74LVC07ARGYR ACTIVE VQFN RGY 14 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
& no Sb/Br)
SN74LVC07ARGYRG4 ACTIVE VQFN RGY 14 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 20-Jan-2011

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC07A :

• Automotive: SN74LVC07A-Q1
• Enhanced Product: SN74LVC07A-EP

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC07ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74LVC07ADGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74LVC07ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC07ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC07ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC07ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC07ADT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC07ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LVC07APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC07APWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
SN74LVC07APWRG3 TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
SN74LVC07APWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC07APWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC07ARGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC07ADBR SSOP DB 14 2000 367.0 367.0 38.0
SN74LVC07ADGVR TVSOP DGV 14 2000 367.0 367.0 35.0
SN74LVC07ADR SOIC D 14 2500 367.0 367.0 38.0
SN74LVC07ADR SOIC D 14 2500 333.2 345.9 28.6
SN74LVC07ADRG4 SOIC D 14 2500 333.2 345.9 28.6
SN74LVC07ADRG4 SOIC D 14 2500 367.0 367.0 38.0
SN74LVC07ADT SOIC D 14 250 367.0 367.0 38.0
SN74LVC07ANSR SO NS 14 2000 367.0 367.0 38.0
SN74LVC07APWR TSSOP PW 14 2000 367.0 367.0 35.0
SN74LVC07APWR TSSOP PW 14 2000 364.0 364.0 27.0
SN74LVC07APWRG3 TSSOP PW 14 2000 364.0 364.0 27.0
SN74LVC07APWRG4 TSSOP PW 14 2000 367.0 367.0 35.0
SN74LVC07APWT TSSOP PW 14 250 367.0 367.0 35.0
SN74LVC07ARGYR VQFN RGY 14 3000 367.0 367.0 35.0

Pack Materials-Page 2
 MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23
0,40 0,07 M
0,13
24 13

0,16 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25

0°–
8°
0,75
1 12
0,50
A

Seating Plane

0,15
1,20 MAX 0,08
0,05

PINS **
14 16 20 24 38 48 56
DIM

A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40

A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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