SN74LVC258A

SCLSA19 – JULY 2024

SN74LVC258A Quadruple 2-Line To 1-Line Inverting Data Selectors or Multiplexers

With 3-State Outputs
1 Features 3 Description
• Operating range from 1.1V to 3.6V The SN74LVC258A contains four 2-to-1 digital
• Over-voltage tolerant inputs support up to 5.5V multiplexers with inverted outputs. The output enable
independent of VCC (OE) and select (A/B) inputs control all channels.
• Supports partial-power-down with back drive
Package Information
protection (Ioff) PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE (NOM)(3)
• High push-pull output drive strength: D (SOIC, 16) 9.9mm × 6mm 9.9mm × 3.9mm
SN74LVC258A
– ±24mA at 3.3V PW (TSSOP, 16) 5mm × 6.4mm 5mm × 4.4mm

– ±8mA at 2.3V (1) For more information, see Section 11.

– ±4mA at 1.65V (2) The package size (length × width) is a nominal value and
• Maximum propagation delay of 6.4ns at 3.3V includes pins, where applicable
supply (3) The body size (length × width) is a nominal value and does
not include pins.
• Latch-up performance exceeds 100mA
per JESD78
2 Applications
• Data selection
• Multiplexing
Shared Control Logic

OE

A/B

xA
xY

xB

One of Four 2:1 Multiplexers

Functional Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7.3 Feature Description...................................................12
2 Applications..................................................................... 1 7.4 Device Functional Modes..........................................13
3 Description.......................................................................1 8 Application and Implementation.................................. 15
4 Pin Configuration and Functions...................................3 8.1 Application Information............................................. 15
5 Specifications.................................................................. 4 8.2 Typical Application.................................................... 15
5.1 Absolute Maximum Ratings........................................ 4 8.3 Power Supply Recommendations.............................17
5.2 ESD Ratings............................................................... 4 8.4 Layout....................................................................... 17
5.3 Recommended Operating Conditions.........................4 9 Device and Documentation Support............................18
5.4 Thermal Information....................................................5 9.1 Documentation Support............................................ 18
5.5 Electrical Characteristics.............................................5 9.2 Receiving Notification of Documentation Updates....18
5.6 Switching Characteristics............................................6 9.3 Support Resources................................................... 18
5.7 Noise Characteristics.................................................. 7 9.4 Trademarks............................................................... 18
5.8 Typical Characteristics................................................ 7 9.5 Electrostatic Discharge Caution................................18
6 Parameter Measurement Information.......................... 10 9.6 Glossary....................................................................18
7 Detailed Description......................................................12 10 Revision History.......................................................... 18
7.1 Overview................................................................... 12 11 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram......................................... 12 Information.................................................................... 18

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4 Pin Configuration and Functions

A/B 1 16 VCC
1A 2 15 OE
1B 3 14 4A
1Y 4 13 4B
2A 5 12 4Y
2B 6 11 3A
2Y 7 10 3B
GND 8 9 3Y

Figure 4-1. D or PW Package, 16-Pin SOIC or TSSOP (Top View)

Table 4-1. Pin Functions

PIN
TYPE(1) DESCRIPTION
NAME NO.
A/B 1 I Select data source
1A 2 I Channel 1, input A
1B 3 I Channel 1, input B
1Y 4 O Channel 1, output Y
2A 5 I Channel 2, input A
2B 6 I Channel 2, input B
2Y 7 O Channel 2, output Y
GND 8 G Ground
3Y 9 O Channel 3, output Y
3B 10 I Channel 3, input B
3A 11 I Channel 3, input A
4Y 12 O Channel 4, output Y
4B 13 I Channel 4, input B
4A 14 I Channel 4, input A
OE 15 I Output enable, active low
VCC 16 P Positive Supply

(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage range -0.5 6.5 V
VI Input voltage range(2) -0.5 6.5 V
High or low state -0.5 VCC + 0.5 V
VO Output voltage range(2)
High-impedance state -0.5 6.5 V
IIK Input clamp current VI < 0V -50 mA
IOK Output clamp current VO < 0V -50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
TJ Junction temperature 150 °C
Tstg Storage temperature -65 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
(2) The input and output negative voltage ratings may be exceeded if the input and output current ratings are observed.

5.2 ESD Ratings

VALUE UNIT

Electrostatic Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000

V(ESD) V
discharge Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±1000

(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage 1.1 3.6 V
VI Input voltage 0 5.5 V
VO Output voltage High or low state 0 VCC V
VO Output voltage High-impedance state 0 5.5 V
VCC = 1.1V 0.75 V
VCC = 1.2V 0.78 V
VCC = 1.5V 0.975 V
VCC = 1.65V 1.0725 V
VIH High-level input voltage
VCC = 1.95V 1.2675 V
VCC = 2.3V 1.7 V
VCC = 2.7V 1.7 V
VCC = 3.6V 2 V

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5.3 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC = 1.1V 0.40 V
VCC = 1.2V 0.42 V
VCC = 1.5V 0.525 V
VCC = 1.65V 0.5775 V
VIL Low-Level input voltage
VCC = 1.95V 0.6825 V
VCC = 2.3V 0.7 V
VCC = 2.7V 0.7 V
VCC = 3.6V 0.8 V
VCC = 1.8V -4
VCC = 2.3V -8
IOH High-level output current mA
VCC = 2.7V -12
VCC = 3V -24
VCC = 1.8V 4
VCC = 2.3V 8
IOL Low-level output current mA
VCC = 2.7V 12
VCC = 3V 24
Δt/Δv Input transition rise or fall rate 10 ns/V
TA Operating free-air temperature -40 125 °C

5.4 Thermal Information

THERMAL METRIC(1)
PACKAGE PINS UNIT
RθJA RθJC(top) RθJB ΨJT ΨJB RθJC(bot)
D (SOIC) 16 109.1 70.8 67.3 34.1 67.1 - °C/W
PW (TSSOP) 16 141.8 74 87.1 22.3 86.6 - °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
note.

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
-40°C to 125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX
VCC -
VOH IOH= –100μA 1.1V to 3.6V VCC - 0.2 V
0.01
VOH IOH= –4mA 1.65V 1.2 V
VOH IOH= –8mA 2.3V 1.75 V
VOH 2.7V 2.2 V
IOH= –12mA
VOH 3V 2.4 V
VOH IOH= –24mA 3V 2.2 V
VOL IOL = 100μA 1.1V to 3.6V 0.01 0.2 V
VOL IOL = 4mA 1.65V 0.45 V
VOL IOL = 8mA 2.3V 0.7 V
VOL IOL = 12mA 2.7V 0.2 0.4 V
VOL IOL = 24mA 3V 0.55 V
II VI = VCC or GND 3.6V ±5 µA

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5.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
-40°C to 125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX
Ioff VI or VO = VCC 0V ±10 µA
IOZ VO = VCC or GND 3.6V ±15 µA
ICC VI = VCC or GND, IO = 0 3.6V 40 µA
One input at VCC - 0.6V, other inputs at
ΔICC 2.7V to 3.6V 5000 µA
VCC or GND
CI VI = VCC or GND 3.3V 4.9 pF
CO VO = VCC or GND 3.3V 6.3 pF
CPD f = 10MHz 1.8V 12 pF
CPD f = 10MHz 2.5V 15 pF
CPD f = 10MHz 3.3V 17 pF
1.8V 2
CPD Outputs disabled, f = 10MHz 2.5V 3 pF
3.3V 4

5.6 Switching Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See Parameter
Measurement Information
-40°C to
TA = 25°C -40°C to 85°C
LOAD 125°C UNI
PARAMETER FROM (INPUT) TO (OUTPUT) VCC
CAPACITANCE MI TY MA MI TY MA MI TY MA T
N P X N P X N P X
13.
CL = 15pF 1.2V ± 0.1V 16 25 ns
7
13.
CL = 15pF 1.5V ± 0.12V 14 7.7 ns
3

A or B Y 13. 13. 15.

CL = 30pF 1.8V ± 0.15V 5.5 1 5.5 ns
5 5 5
CL = 30pF 2.5V ± 0.2V 3.2 7.4 1 7.4 3.7 10 ns
CL = 50pF 2.7V 3.6 5.7 1 5.4 3.7 7.4 ns
CL = 50pF 3.3V ± 0.3V 3 5 1 4.6 3.4 6.4 ns
tpd
26.
CL = 15pF 1.2V ± 0.1V 17 15 ns
2
CL = 15pF 1.5V ± 0.12V 16 8.5 14 ns
15. 15. 17.
CL = 30pF 1.8V ± 0.15V 6 1 6.3 ns
A/B Y 5 6 5
12.
CL = 30pF 2.5V ± 0.2V 3.7 9.6 1 9.5 4.4 ns
2
CL = 50pF 2.7V 4.1 7.9 1 7.5 4.4 10 ns
CL = 50pF 3.3V ± 0.3V 3.4 6.6 1 6.4 4.1 8.4 ns

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over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See Parameter
Measurement Information
-40°C to
TA = 25°C -40°C to 85°C
LOAD 125°C UNI
PARAMETER FROM (INPUT) TO (OUTPUT) VCC
CAPACITANCE MI TY MA MI TY MA MI TY MA T
N P X N P X N P X
13. 20.
CL = 15pF 1.2V ± 0.1V 16 ns
1 6
10.
CL = 15pF 1.5V ± 0.12V 15 7.2 ns
6

ten OE Y 14.
CL = 30pF 1.8V ± 0.15V 1 7.3 8.6 ns
6
CL = 30pF 2.5V ± 0.2V 1 8.7 4.8 5.7 ns
CL = 50pF 2.7V 1 6.7 5.2 6.7 ns
CL = 50pF 3.3V ± 0.3V 1 5.6 4.4 5.4 ns
CL = 15pF 1.2V ± 0.1V 17 12 17 ns
10.
CL = 15pF 1.5V ± 0.12V 16 7.5 ns
3
15. 15.
tdis OE Y CL = 30pF 1.8V ± 0.15V 1 7.9 ns
4 4
CL = 30pF 2.5V ± 0.2V 1 6.7 4.7 6.7 ns
CL = 50pF 2.7V 4.8 1 5.2 4.9 5.5 ns
CL = 50pF 3.3V ± 0.3V 4.4 1 4.9 4.6 5.1 ns
tsk(o) 3.3V ± 0.3V 1 1.5 ns

5.7 Noise Characteristics

VCC = 3.3V, CL = 50pF, TA = 25°C
PARAMETER DESCRIPTION MIN TYP MAX UNIT
VOL(P) Quiet output, maximum dynamic VOL 0.8 V
VOL(V) Quiet output, minimum dynamic VOL -0.8 -0.3 V
VOH(V) Quiet output, minimum dynamic VOH 2.2 3.3 V
VIH(D) High-level dynamic input voltage 2.0 V
VIL(D) Low-level dynamic input voltage 0.8 V

5.8 Typical Characteristics

TA = 25°C (unless otherwise noted)

60 800
1.8 V 3.3 V
54 2.5 V 720 5.0 V
48 640
ICC - Supply Current (µA)

ICC - Supply Current (µA)

42 560
36 480
30 400
24 320
18 240
12 160
6 80
0 0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VIN - Input Voltage (V) VIN - Input Voltage (V)

Figure 5-1. Supply Current Across Input Voltage 1.8V and 2.5V Figure 5-2. Supply Current Across Input Voltage 3.3V and 5.0V
Supply Supply

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5.8 Typical Characteristics (continued)

TA = 25°C (unless otherwise noted)

80 5
25°C
70 125°C 4.5
-40°C
60 4

50 3.5
ICC (nA)

VOH (V)
40 3

30 2.5

20 2 1.8 V
2.5 V
10 1.5 3.3 V
5.0 V
0
1
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
0 -2.5 -5 -7.5 -10 -12.5 -15 -17.5 -20 -22.5 -25
VCC (V)
IOH (mA)
Figure 5-3. Supply Current Across Supply Voltage
Figure 5-4. Output Voltage vs Current in HIGH State
0.55 5
4.95
0.5
4.9
0.45 4.85
0.4 4.8
0.35 4.75
4.7
VOH (V)
VOL (V)

0.3
4.65
0.25 4.6
0.2 4.55
0.15 4.5
1.8 V 4.45
0.1 2.5 V -40°C
4.4 25°C
3.3 V
0.05 5.0 V 4.35 125°C
0 4.3
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 -25 -22.5 -20 -17.5 -15 -12.5 -10 -7.5 -5 -2.5 0
IOL (mA) IOH (mA)

Figure 5-5. Output Voltage vs Current in LOW State Figure 5-6. Output Voltage vs Current in HIGH State; 5V Supply

0.5 3.3
3.25
0.45 3.2
0.4 3.15
3.1
0.35 3.05
0.3 3
VOH (V)
VOL (V)

2.95
0.25 2.9
2.85
0.2 2.8
0.15 2.75
2.7
0.1 -40°C 2.65 -40°C
0.05 25°C 2.6 25°C
125°C 2.55 125°C
0 2.5
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 -25 -22.5 -20 -17.5 -15 -12.5 -10 -7.5 -5 -2.5 0
IOL (mA) IOH (mA)

Figure 5-7. Output Voltage vs Current in LOW State; 5V Supply Figure 5-8. Output Voltage vs Current in HIGH State; 3.3V
Supply

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5.8 Typical Characteristics (continued)

TA = 25°C (unless otherwise noted)

0.6 2.5
0.55 2.45
0.5 2.4
0.45 2.35
0.4 2.3
0.35 2.25

VOH (V)
VOL (V)

0.3 2.2
0.25 2.15
0.2 2.1
0.15 2.05
0.1 -40°C 2 -40°C
25°C 25°C
0.05 125°C 1.95 125°C
0 1.9
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 -16 -14 -12 -10 -8 -6 -4 -2 0
IOL (mA) IOH (mA)

Figure 5-9. Output Voltage vs Current in LOW State; 3.3V Figure 5-10. Output Voltage vs Current in HIGH State; 2.5V
Supply Supply
0.4 1.8
1.775
0.35 1.75
1.725
0.3 1.7
1.675
0.25 VOH (V) 1.65
VOL (V)

1.625
0.2 1.6
1.575
0.15 1.55
1.525
0.1 1.5
-40°C 1.475 -40°C
0.05 25°C 1.45 25°C
125°C 1.425 125°C
0 1.4
0 2 4 6 8 10 12 14 16 -8 -7 -6 -5 -4 -3 -2 -1
IOL (mA) IOH (mA)

Figure 5-11. Output Voltage vs Current in LOW State; 2.5V Figure 5-12. Output Voltage vs Current in HIGH State; 1.8V
Supply Supply
0.28
0.26
0.24
0.22
0.2
0.18
0.16
VOL (V)

0.14
0.12
0.1
0.08
0.06
-40°C
0.04 25°C
0.02 125°C
0
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5
IOL (mA)

Figure 5-13. Output Voltage vs Current in LOW State; 1.8V Supply

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6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily for the examples listed in the following table. All
input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω, tt ≤ 2.5ns.
The outputs are measured individually with one input transition per measurement.
TEST S1 S2 RL CL ΔV VLOAD

tPLH, tPHL OPEN OPEN 500Ω 50pF — —

tPLZ, tPZL CLOSED OPEN 500Ω 50pF 0.3V 2×VCC

tPHZ, tPZH OPEN CLOSED 500Ω 50pF 0.3V —

VCC Vt RL CL ΔV VLOAD

1.2V ± 0.1V VCC/2 2kΩ 15pF 0.1V 2×VCC

1.5V ± 0.12V VCC/2 2kΩ 15pF 0.1V 2×VCC

1.8V ± 0.15V VCC/2 1kΩ 30pF 0.15V 2×VCC

2.5V ± 0.2V VCC/2 500Ω 30pF 0.15V 2×VCC

2.7V 1.5V 500Ω 50pF 0.3V 6V

3.3V ± 0.3V 1.5V 500Ω 50pF 0.3V 6V

Test VLOAD VCC

Point
Input Vt Vt
S1 0V
RL
From Output tPLH (1)
tPHL (1)

Under Test
VOH
CL(1) RL S2 Output
50% 50%
Waveform 1
VOL
(1) CL includes probe and test-fixture capacitance. tPHL(1) tPLH(1)
Figure 6-1. Load Circuit for 3-State Outputs VOH
Output
50% 50%
Waveform 2
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-2. Voltage Waveforms Propagation Delays
VCC VCC
90% 90%
Output
Vt Vt Input
Control
10% 10%
0V 0V
tr(1) tf(1)
(3) (4)
tPZL tPLZ

Output
VCC 90%

VOH
90%
Waveform 1
50% Output
S1 CLOSED VOL + V 10% 10%
S2 OPEN VOL VOL
tr(1) tf(1)
tPZH(3) tPHZ(4)
(1) The greater between tr and tf is the same as tt.
VOH
Output
VOH - V Figure 6-4. Voltage Waveforms, Input and Output
Waveform 2
S1 OPEN
50% Transition Times
S2 CLOSED 0V
(1) The greater between tPZL and tPZH is the same as ten.
(2) The greater between tPLZ and tPHZ is the same as tdis.
Figure 6-3. Voltage Waveforms Propagation Delays

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VOH(P), VOL(P)
Quiet
Output
VOL(V)

Noise values measured with all other outputs simultaneously switching.

Figure 6-5. Voltage Waveforms, Noise

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7 Detailed Description
7.1 Overview
The SN74LVC258A is a 4 channel 2-to-1 multiplexer with inverted outputs.
The output enable (OE) input enables all outputs when low, and forces all outputs into the high-impedance state
when high.
The select (A/B) input chooses the data source for all channels, with the low state indicating the A data source,
and the high state indicating the B data source.
7.2 Functional Block Diagram
Shared Control Logic

OE

A/B

xA
xY

xB

One of Four 2:1 Multiplexers

7.3 Feature Description

7.3.1 Balanced CMOS 3-State Outputs
This device includes balanced CMOS 3-state outputs. Driving high, driving low, and high impedance are the
three states that these outputs can be in. The term balanced indicates that the device can sink and source
similar currents. The drive capability of this device may create fast edges into light loads, so routing and load
conditions should be considered to prevent ringing. Additionally, the outputs of this device can drive larger
currents than the device can sustain without being damaged. It is important for the output power of the device
to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute
Maximum Ratings must be followed at all times.
When placed into the high-impedance state, the output will neither source nor sink current, with the exception of
minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output
voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected
to the node, then this is known as a floating node and the voltage is unknown. A pull-up or pull-down resistor
can be connected to the output to provide a known voltage at the output while it is in the high-impedance state.
The value of the resistor will depend on multiple factors, including parasitic capacitance and power consumption
limitations. Typically, a 10kΩ resistor can be used to meet these requirements.
Unused 3-state CMOS outputs should be left disconnected.
7.3.2 Partial Power Down (Ioff)
This device includes circuitry to disable all outputs when the supply pin is held at 0V. When disabled, the outputs
will neither source nor sink current, regardless of the input voltages applied. The amount of leakage current at
each output is defined by the Ioff specification in the Electrical Characteristics table.

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7.3.3 Standard CMOS Inputs

This device includes standard CMOS inputs. Standard CMOS inputs are high impedance and are typically
modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst
case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the
maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I).
Standard CMOS inputs require that input signals transition between valid logic states quickly, as defined
by the input transition time or rate in the Recommended Operating Conditions table. Failing to meet this
specification will result in excessive power consumption and could cause oscillations. More details can be found
in Implications of Slow or Floating CMOS Inputs.
Do not leave standard CMOS inputs floating at any time during operation. Unused inputs must be terminated at
VCC or GND. If a system will not be actively driving an input at all times, then a pull-up or pull-down resistor can
be added to provide a valid input voltage during these times. The resistor value will depend on multiple factors; a
10kΩ resistor, however, is recommended and will typically meet all requirements.
7.3.4 Clamp Diode Structure
Figure 7-1 shows the inputs and outputs to this device have negative clamping diodes only.

CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage
to the device. The input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.

Figure 7-1. Electrical Placement of Clamping Diodes for Each Input and Output

7.4 Device Functional Modes

Function Table lists the functional modes of the SN74LVC258A.
Table 7-1. Function Table
INPUTS(1)
OUTPUT(2)
SELECT DATA
OE
A/B A B Y
H X X X Z
L L L X H
L L H X L
L H X L H
L H X H L

(1) H = High voltage level, L = Low voltage level, X = Don't care

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(2) H = Driving high, L = Driving low

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

The SN74LVC258A is a quadruple 2-to-1 data selector/multiplexer with inverted outputs. The following
application shows an example of using the device with all required connections to switch a 4-bit data bus
between two source devices.
8.2 Typical Application
A/B
Receiver
A0 1A
Data A1
1Y Data[0]
1B
Source A2
2A
A A3 2Y Data[1]
2B
System
3A
Controller Data B0 3Y Data[2]
3B
B1
Source B2 4A
4Y Data[3]
B B3 4B

OE

Figure 8-1. Typical Application Block Diagram

8.2.1 Design Requirements

8.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions.
The supply voltage sets the device's electrical characteristics of the device as described in the Electrical
Characteristics section.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the SN74LVC258A plus the maximum static supply current, ICC, listed in the Electrical Characteristics,
and any transient current required for switching. The logic device can only source as much current that is
provided by the positive supply source. Ensure the maximum total current through VCC listed in the Absolute
Maximum Ratings is not exceeded.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74LVC258A plus the maximum supply current, ICC, listed in the Electrical Characteristics, and any transient
current required for switching. The logic device can only sink as much current that can be sunk into its ground
connection. Ensure the maximum total current through GND listed in the Absolute Maximum Ratings is not
exceeded.
The SN74LVC258A can drive a load with a total capacitance less than or equal to 50pF while still meeting all of
the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to exceed
50pF.
The SN74LVC258A can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and
current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the HIGH state, the
output voltage in the equation is defined as the difference between the measured output voltage and the supply
voltage at the VCC pin.

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Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.

CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.

8.2.1.2 Input Considerations

Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. The unused inputs can be directly terminated if the
input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is
used for a default state of LOW. The drive current of the controller, leakage current into the SN74LVC258A (as
specified in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10kΩ
resistor value is often used due to these factors.
The SN74LVC258A has CMOS inputs and thus requires fast input transitions to operate correctly, as defined in
the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power
consumption, and reduction in device reliability.
Refer to the Feature Description section for additional information regarding the inputs for this device.
8.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to the Feature Description section for additional information regarding the outputs for this device.
8.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50pF. This is not a hard limit; by design, however, it will
optimize performance. This can be accomplished by providing short, appropriately sized traces from the
SN74LVC258A to one or more of the receiving devices.
3. Ensure the resistive load at the output is larger than (VCC / IO(max))Ω. Doing this will prevent the maximum
output current from the Absolute Maximum Ratings from being violated. Most CMOS inputs have a resistive
load measured in MΩ; much larger than the minimum calculated previously.
4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.

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 SN74LVC258A
www.ti.com SCLSA19 – JULY 2024

8.2.3 Application Curve

xY

OE

A/B

xA

xB

Figure 8-2. Application Timing Diagram

8.3 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the
Recommended Operating Conditions.
During startup, the power supply should ramp within the provided power-up ramp rate range in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For the SN74LVC258A,
a 0.1μF bypass capacitor is recommended. To reject different frequencies of noise, use multiple bypass
capacitors in parallel. Capacitors with values of 0.1μF and 1μF are commonly used in parallel.
8.4 Layout
8.4.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices, inputs must never be left floating. In many cases,
functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
8.4.2 Layout Example

GND VCC

Recommend GND flood fill for Bypass capacitor

improved signal isolation, noise placed close to the
reduction, and thermal dissipation
0.1
F device

A/B 1 16 VCC
1A 2 15 OE
1B 3 14 4A
1Y 4 13 4B
2A 5 12 4Y
2B 6 11 3A Unused inputs
2Y 7 10 3B tied to VCC
Avoid 90°
Unused output
corners for GND 8 9 3Y
left floating
signal lines

Figure 8-3. Example Layout for the SN74LVC258A

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SCLSA19 – JULY 2024 www.ti.com

9 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, CMOS Power Consumption and Cpd Calculation application note
• Texas Instruments, Designing With Logic application note
• Texas Instruments, Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices
application note
• Texas Instruments, Implications of Slow or Floating CMOS Inputs application note
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE REVISION NOTES
July 2024 * Initial Release

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

18 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: SN74LVC258A

 PACKAGE OPTION ADDENDUM

www.ti.com 22-Aug-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74LVC258APWR ACTIVE TSSOP PW 16 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LVC258 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Sep-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC258APWR TSSOP PW 16 3000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Sep-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC258APWR TSSOP PW 16 3000 353.0 353.0 32.0

Pack Materials-Page 2
 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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