SN54/74LS669

SYNCHRONOUS 4-BIT
UP/DOWN COUNTER
The SN54 / 74LS669 is a synchronous 4-bit up/down counter. The LS669 is
a 4-bit binary counter. For high speed counting applications, this presettable
counter features an internal carry lookahead for cascading purposes. By
clocking all flip-flops simultaneously so the outputs change coincident with SYNCHRONOUS 4-BIT
each other (when instructed to do so by the count enable inputs and internal UP/DOWN COUNTER
gating) synchronous operation is provided. This helps to eliminate output
counting spikes, normally associated with asynchronous (ripple-clock) count- LOW POWER SCHOTTKY
ers. The four master-slave flip-flops are triggered on the rising (positive-going)
edge of the clock waveform by a buffered clock input.
Circuitry of the load inputs allows loading with the carry-enable output of the
cascaded counters. Because loading is synchronous, disabling of the counter
by setting up a low level on the load input will cause the outputs to agree with
J SUFFIX
the data inputs after the next clock pulse.
CERAMIC
Cascading counters for N-bit synchronous applications are provided by the CASE 620-09
carry look-ahead circuitry, without additional gating. Two count-enable inputs 16
and a carry output help accomplish this function. Count-enable inputs (P and 1
T) must both be low to count. The level of the up-down input determines the
direction of the count. When the input level is low, the counter counts down,
and when the input is high, the count is up. Input T is fed forward to enable the N SUFFIX
PLASTIC
carry output. The carry output will now produce a low level output pulse with a
CASE 648-08
duration ≈ equal to the high portion of the QA output when counting up and 16
when counting down ≈ equal to the low portion of the QA output. This low level 1
carry pulse may be utilized to enable successive cascaded stages. Regard-
less of the level of the clock input, transitions at the P or T inputs are allowed.
By diode-clamping all inputs, transmission line effects are minimized which D SUFFIX
allows simplification of system design. SOIC
16
Any changes at control inputs (ENABLE P, ENABLE T, LOAD, UP/ DOWN) 1 CASE 751B-03
will have no effect on the operating mode until clocking occurs because of the
fully independant clock circuits. Whether enabled, disabled, loading or count-
ing, the function of the counter is dictated entirely by the conditions meeting
the stable setup and hold times.
ORDERING INFORMATION
• Programmable Look-Ahead Up/ Down Binary/ Decade Counters
SN54LSXXXJ Ceramic
• Fully Synchronous Operation for Counting and Programming
SN74LSXXXN Plastic
• Internal Look-Ahead for Fast Counting SN74LSXXXD SOIC
• Carry Output for n-Bit Cascading
• Fully Independent Clock Circuit
• Buffered Outputs

CONNECTION DIAGRAM (TOP VIEW)

OUTPUTS
RIPPLE
CARRY ENABLE
VCC OUTPUT QA QB QC QD T LOAD
16 15 14 13 12 11 10 9

RIPPLE QA QB QC QD ENABLE
CARRY T
OUTPUT LOAD
UP/DOWN
ENABLE
CK A B C D P

1 2 3 4 5 6 7 8
U/D CK A B C D ENABLE GND
P
DATA INPUTS

FAST AND LS TTL DATA

5-1
 SN54/74LS669

LOGIC DIAGRAM

(3) (4) (5) (6)

DATA DATA DATA DATA
P0 P1 P2 P3
(9) LOAD

(7) ENP
(10) ENT
(1) U/D

RCO (15)
(RIPPLE CARRY
OUTPUT)

(2) CP
CP D CP D CP D CP D

QA QB QC QD
(14) (13) (12) (11)

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High 54, 74 – 0.4 mA
IOL Output Current — Low 54 4.0 mA
74 8.0

FAST AND LS TTL DATA

5-2
 SN54/74LS669

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
di i
Guaranteed Input HIGH Voltage for
VIH Input HIGH Voltage 2.0 V
All Inputs
54 0.7 Guaranteed Input
p LOW Voltage
g for
VIL Input LOW Voltage V
74 0.8 All Inputs

VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
54 2.5 3.5 V VCC = MIN,, IOH = MAX,, VIN = VIH
VOH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table

54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

VOL Output LOW Voltage VIN = VIL or VIH
74 0.35 0.5 V IOL = 8.0 mA per Truth Table

Others 20 µA
VCC = MAX
MAX, VIN = 2
2.7
7V
Enable T 40 µA
IIH I
Input HIGH C
Current
Others 0.1 mA
VCC = MAX
MAX, VIN = 7
7.0
0V
Enable T 0.2 mA
Others –0.4 mA
IIL Input LOW Current VCC = MAX
MAX, VIN = 0
0.4
4V
Enable T –0.8 mA
IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX
ICC Power Supply Current 34 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)

Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
di i
fMAX Maximum Clock Frequency 25 32 MHz
tPLH Propagation Delay, 26 40
ns
tPHL Clock to RCO 40 60

tPLH Propagation Delay, 18 27

ns
tPHL Clock to Any Q 18 27 CL = 15 pF
F
tPLH 11 17
Enable to RCO ns
tPHL 29 45

tPLH 22 35
U/D to RCO ns
tPHL 26 40

AC SETUP REQUIREMENTS (TA = 25°C)

Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
di i
tW Clock Pulse Width 20 ns
ts Data Setup Time 20 ns
ts Enable Setup Time 35 ns
VCC = 5
5.0
0V
ts Load Setup Time 25 ns
ts U/D Setup Time 30 ns
th Hold Time, Any Input 0 ns

FAST AND LS TTL DATA

5-3
 SN54/74LS669

PARAMETER MEASUREMENT INFORMATION

tw(clock) tw(clock)
3V
CLOCK
INPUT 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V
0V
ts ts
th
3V
LOAD 1.3 V 1.3 V
INPUT
0V
ts th
3V
DATA INPUTS
A,B,C, and D 1.3 V 1.3 V
0V

ts th
0V
ENABLE P or 1.3 V 1.3 V
ENABLE T
3V
ts th ts
th
3V
UP/DOWN 1.3 V 1.3 V 1.3 V 1.3 V
INPUT
0V

VOLTAGE WAVEFORMS

3V
ENABLE T 1.3 V 1.3 V
INPUT
0V
tPHL tPLH
VOL
RIPPLE 1.3 V 1.3 V
CARRY
OUTPUT VOH

FAST AND LS TTL DATA

5-4