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SN74LV04A
SCLS388K – SEPTEMBER 1997 – REVISED DECEMBER 2014

SN74LV04A Hex Inverters

1 Features 2 Applications
•
1 2-V to 5.5-V VCC Operation • Power Sub-Station Controls
• Max tpd of 6.5 ns at 5 V • Ethernet Switches
• Latch-Up Performance Exceeds 250 mA • Flow Meters
Per JESD 17 • I/O Modules; Digital PLC/DCS Inputs
• Typical VOLP (Output Ground Bounce) • Servers
< 0.8 V at VCC = 3.3 V, TA = 25°C • Tests and Measurement
• Typical VOHV (Output VOH Undershoot)
> 2.3 V at VCC = 3.3 V, TA = 25°C 3 Description
• Support Mixed-Mode Voltage Operation on This hex inverter is designed for 2-V to 5.5-V VCC
All Ports operation. The SN74LV04A device contains six
• Ioff Supports Partial-Power-Down Mode Operation independent inverters. This device perform the
Boolean function Y = A.
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model Device Information(1)
– 200-V Machine Model PART NUMBER PACKAGE BODY SIZE (NOM)
– 1000-V Charged-Device Model TVSOP (14) 3.60 mm x 4.40 mm
SOIC (14) 8.65 mm × 3.91 mm
SN74LV04A VQFN (14) 3.50 mm x 3.50 mm
SSOP (14) 6.20 mm x 5.30 mm
TSSOP (14) 5.00 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

4 Simplified Schematic

A Y

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LV04A
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Table of Contents
1 Features .................................................................. 1 9 Detailed Description .............................................. 9
2 Applications ........................................................... 1 9.1 Overview ................................................................... 9
3 Description ............................................................. 1 9.2 Functional Block Diagram ......................................... 9
4 Simplified Schematic............................................. 1 9.3 Feature Description................................................... 9
9.4 Device Functional Modes.......................................... 9
5 Revision History..................................................... 2
6 Pin Configuration and Functions ......................... 3 10 Application and Implementation........................ 10
10.1 Application Information.......................................... 10
7 Specifications......................................................... 4
10.2 Typical Application ............................................... 10
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4 11 Power Supply Recommendations ..................... 11
7.3 Recommended Operating Conditions....................... 5 12 Layout................................................................... 12
7.4 Thermal Information .................................................. 5 12.1 Layout Guidelines ................................................. 12
7.5 Electrical Characteristics........................................... 6 12.2 Layout Example .................................................... 12
7.6 Switching Characteristics, VCC = 2.5 V ± 0.2 V ........ 6 13 Device and Documentation Support ................. 12
7.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V ........ 6 13.1 Related Links ........................................................ 12
7.8 Switching Characteristics, VCC = 5 V ± 0.5 V ........... 6 13.2 Trademarks ........................................................... 12
7.9 Noise Characteristics ................................................ 7 13.3 Electrostatic Discharge Caution ............................ 12
7.10 Operating Characteristics........................................ 7 13.4 Glossary ................................................................ 12
7.11 Typical Characteristics ............................................ 7 14 Mechanical, Packaging, and Orderable
8 Parameter Measurement Information .................. 8 Information ........................................................... 12

5 Revision History
Changes from Revision J (April 2005) to Revision K Page

• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
• Deleted Ordering Information table. ....................................................................................................................................... 1
• Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 5

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6 Pin Configuration and Functions

SN74LV04A . . . D, DB, DGV, NS, SN74LV04A . . . RGY PACKAGE
OR PW PACKAGE (TOP VIEW)
(TOP VIEW)

VCC
1A
1A VCC 1 14
1 14
1Y 6A 1Y 2 13 6A
2 13
2A 6Y 2A 3 12 6Y
3 12
2Y 5A 2Y 4 11 5A
4 11
3A 5 10 5Y 3A 5 10 5Y
3Y 6 9 4A
3Y 6 9 4A
7 8
GND 7 8 4Y

4Y
GND
Pin Functions
PIN
SN74LV04A
TYPE DESCRIPTION
NAME D, DB, DGV,
RGY
NS, PW
1A 1 1 I 1A Input
1Y 2 2 O 1Y Output
2A 3 3 I 2A Input
2Y 4 4 O 2Y Output
3A 5 5 I 3A Input
3Y 6 6 O 3Y Output
4Y 8 8 O 4Y Output
4A 9 9 I 4A Input
5Y 10 10 O 5Y Output
5A 11 11 I 5A Input
6Y 12 12 O 6Y Output
6A 13 13 I 6A Input
GND 7 7 — Ground Pin
VCC 14 14 — Power Pin

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage range –0.5 7 V
(2)
VI Input voltage range –0.5 7 V
VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 7 V
VO Output voltage range (2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –20 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current VO = 0 to VCC ±25 mA
Continuous current through VCC or GND ±50 mA
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 5.5-V maximum.

7.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 2000
V(ESD) Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22-C101, V
1000
all pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage 2 5.5 V
VCC = 2 V 1.5
VCC = 2.3 V to 2.7 V VCC × 0.7
VIH High-level input voltage V
VCC = 3 V to 3.6 V VCC × 0.7
VCC = 4.5 V to 5.5 V VCC × 0.7
VCC = 2 V 0.5
VCC = 2.3 V to 2.7 V VCC × 0.3
VIL Low-level input voltage V
VCC = 3 V to 3.6 V VCC × 0.3
VCC = 4.5 V to 5.5 V VCC × 0.3
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 2 V –50 µA
VCC = 2.3 V to 2.7 V –2
IOH High-level output current
VCC = 3 V to 3.6 V –6 mA
VCC = 4.5 V to 5.5 V –12
VCC = 2 V 50 µA
VCC = 2.3 V to 2.7 V 2
IOL Low-level output current
VCC = 3 V to 3.6 V 6 mA
VCC = 4.5 V to 5.5 V 12
VCC = 2.3 V to 2.7 V 200
Δt/Δv Input transition rise or fall rate VCC = 3 V to 3.6 V 100 ns/V
VCC = 4.5 V to 5.5 V 20
TA Operating free-air temperature –40 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).

7.4 Thermal Information

SN74LV04A
THERMAL METRIC (1) D DB DGV NS PW RGY UNIT
14 PINS
RθJA Junction-to-ambient thermal resistance 94.9 107.4 130.4 91.4 122.6 57.6
RθJC(top) Junction-to-case (top) thermal resistance 56.3 59.9 53.4 49.0 51.3 70.4
RθJB Junction-to-board thermal resistance 49.2 54.7 63.5 50.2 64.4 33.6
Junction-to-top characterization
ψJT 20.7 21.0 7.3 15.3 6.8 .3.5 °C/W
parameter
Junction-to-board characterization
ψJB 48.9 51.2 62.8 49.8 63.8 33.7
parameter
Junction-to-case (bottom) thermal
RθJC(bot) — — — — — 14.1
resistance

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

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7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C –40°C to 85°C –40°C to 125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
2 V to VCC – VCC – VCC –
IOH = –50 µA
5.5 V 0.1 0.1 0.1
VOH IOH = –2 mA 2.3 V 2 2 2 V
IOH = –6 mA 3V 2.48 2.48 2.48
IOH = –12 mA 4.5 V 3.8 3.8 3.8
2 V to
IOL = 50 µA 0.1 0.1 0.1
5.5 V
VOL IOL = 2 mA 2.3 V 0.4 0.4 0.4 V
IOL = 6 mA 3V 0.44 0.44 0.44
IOL = 12 mA 4.5 V 0.55 0.55 0.55
0 to
II VI = 5.5 V or GND ±1 ±1 ±1 µA
5.5 V
ICC VI = VCC or GND, IO = 0 5.5 V 20 20 20 µA
Ioff VI or VO = 0 to 5.5 V 0 5 5 5 µA
3.3 V 2.3
Ci VI = VCC or GND pF
5V 2.3

7.6 Switching Characteristics, VCC = 2.5 V ± 0.2 V

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
FROM TO LOAD TA = 25°C –40°C to 85°C –40°C to 125°C
PARAMETER UNIT
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
CL = 15 pF 7.1 (1) 11.7 (1) 1 14 1 15
tpd A Y ns
CL = 50 pF 10 15.5 1 18 1 19

(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.

7.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
FROM TO LOAD TA = 25°C –40°C to 85°C –40°C to 125°C
PARAMETER UNIT
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
CL = 15 pF 5.1 (1) 7.1 (1) 1 8.5 1 9.5
tpd A Y ns
CL = 50 pF 7.3 10.6 1 12 1 13

(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.

7.8 Switching Characteristics, VCC = 5 V ± 0.5 V

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
FROM TO LOAD TA = 25°C –40°C to 85°C –40°C to 125°C
PARAMETER UNIT
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
CL = 15 pF 3.6 (1) 5.5 (1) 1 6.5 1 7.5
tpd A Y ns
CL = 50 pF 5.1 7.5 1 8.5 1 9.5

(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.

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7.9 Noise Characteristics (1)

VCC = 3.3 V, CL = 50 pF, TA = 25°C
SN74LV04A
PARAMETER UNIT
MIN TYP MAX
VOL(P) Quiet output, maximum dynamic VOL 0.3 0.8 V
VOL(V) Quiet output, minimum dynamic VOL –0.1 –0.8 V
VOH(V) Quiet output, minimum dynamic VOH 3.1 V
VIH(D) High-level dynamic input voltage 2.31 V
VIL(D) Low-level dynamic input voltage 0.99 V

(1) Characteristics are for surface-mount packages only.

7.10 Operating Characteristics

TA = 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
3.3 V 9.6
Cpd Power dissipation capacitance CL = 50 pF, f = 10 MHz pF
5V 11.4

7.11 Typical Characteristics

4.5 7
TPD in ns
4
6
3.5
5
3
TPD (ns)

TPD (ns)

2.5 4

2 3
1.5
2
1
1
0.5
TPD in ns
0 0
-100 -50 0 50 100 150 0 1 2 3 4 5 6
Temperature (qC) D001
VCC D002
Figure 1. TPD vs Temperature at 5 V Figure 2. TPD vs VCC at 25°C

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8 Parameter Measurement Information

VCC
RL = 1 kΩ S1 Open
From Output Test From Output TEST S1
Under Test Point Under Test GND tPLH/tPHL Open
CL CL tPLZ/tPZL VCC
(see Note A) (see Note A) tPHZ/tPZH GND
Open Drain VCC

LOAD CIRCUIT FOR LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS 3-STATE AND OPEN-DRAIN OUTPUTS

VCC
Timing Input 50% VCC
tw 0V
th
VCC tsu
VCC
Input 50% VCC 50% VCC
Data Input 50% VCC 50% VCC
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VCC VCC
Output
Input 50% VCC 50% VCC 50% VCC 50% VCC
Control
0V 0V

tPLH tPHL tPZL tPLZ

VOH Output ≈VCC
In-Phase 50% VCC 50% VCC Waveform 1 50% VCC
Output S1 at VCC VOL + 0.3 V
VOL VOL
(see Note B)
tPHL tPLH tPZH tPHZ

VOH Output
VOH
Out-of-Phase Waveform 2 VOH − 0.3 V
50% VCC 50% VCC 50% VCC
Output S1 at GND
VOL ≈0 V
(see Note B)
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, t r ≤ 3 ns, t f ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 3. Load Circuit and Voltage Waveforms

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9 Detailed Description

9.1 Overview
These hex inverters are designed for 2-V to 5.5-V VCC operation. The SN74LV04A devices contain six
independent inverters. These devices perform the Boolean function Y = A.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
The inputs are high impedance when VCC = 0V.

9.2 Functional Block Diagram

A Y

Figure 4. Logic Diagram Each Inverter (Positive Logic)

9.3 Feature Description

• Wide operating voltage range
– Operates from 2 V to 5.5 V
• Allows down-voltage translation
– Inputs accept voltages to 5.5 V
• Ioff feature
– Supports Live Insertion, Partial Power DownMode, and Back Drive Protection

9.4 Device Functional Modes

Table 1. Function Table

(Each Inverter)
INPUT OUTPUT
A Y
H L
L H

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10 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

10.1 Application Information

SN74LV04A is a low-drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The inputs can accept voltages to 5.5 V at any valid VCC making it Ideal for down translation.

10.2 Typical Application

5-V regulated

3.3-V or 5-V accessory

0.1 µF

Figure 5. Typical Application Schematic

10.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads, so routing and load conditions should be considered to prevent ringing.

10.2.2 Detailed Design Procedure

1. Recommended Input Conditions
– For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table.
– For specified High and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.

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Typical Application (continued)

10.2.3 Application Curves

Figure 6. Typical Application Curve

11 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and
1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.

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12 Layout

12.1 Layout Guidelines

When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when
asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.

12.2 Layout Example

Vcc
Input

Unused Input Output Output

Unused Input

Input

Figure 7. Layout Diagram

13 Device and Documentation Support

13.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 2. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
SN74LV04A Click here Click here Click here Click here Click here

13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74LV04ADBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV04A Samples

SN74LV04ADGVR ACTIVE TVSOP DGV 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV04A Samples

SN74LV04ADGVRE4 ACTIVE TVSOP DGV 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV04A Samples

SN74LV04ADR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LV04A Samples

SN74LV04ANSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 74LV04A Samples

SN74LV04APWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LV04A Samples

SN74LV04APWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV04A Samples

SN74LV04ARGYR ACTIVE VQFN RGY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LV04A Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

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(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LV04A :

• Enhanced Product : SN74LV04A-EP

NOTE: Qualified Version Definitions:

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LV04ADBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
SN74LV04ADGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74LV04ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LV04ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LV04ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LV04APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV04APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV04APWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV04APWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV04ARGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Feb-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LV04ADBR SSOP DB 14 2000 356.0 356.0 35.0
SN74LV04ADGVR TVSOP DGV 14 2000 356.0 356.0 35.0
SN74LV04ADR SOIC D 14 2500 353.0 353.0 32.0
SN74LV04ADR SOIC D 14 2500 356.0 356.0 35.0
SN74LV04ANSR SO NS 14 2000 367.0 367.0 38.0
SN74LV04APWR TSSOP PW 14 2000 353.0 353.0 32.0
SN74LV04APWR TSSOP PW 14 2000 356.0 356.0 35.0
SN74LV04APWRG4 TSSOP PW 14 2000 356.0 356.0 35.0
SN74LV04APWRG4 TSSOP PW 14 2000 356.0 356.0 35.0
SN74LV04ARGYR VQFN RGY 14 3000 356.0 356.0 35.0

Pack Materials-Page 2
 MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23
0,40 0,07 M
0,13
24 13

0,16 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25

0°–
8°
0,75
1 12
0,50
A

Seating Plane

0,15
1,20 MAX 0,08
0,05

PINS **
14 16 20 24 38 48 56
DIM

A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40

A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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