SN74HCS139-Q1

www.ti.com SCLS812SN74HCS139-Q1
– SEPTEMBER 2020
SCLS812 – SEPTEMBER 2020

SN74HCS139-Q1 Automotive Qualified Dual 2- to 4-Line Decoders/Demultiplexers

with Schmitt-Trigger Inputs

1 Features 3 Description
• AEC-Q100 Qualified for automotive applications: The SN74HCS139-Q1 contains two two-to-four
– Device temperature grade 1: –40°C to +125°C, decoders with one active low output strobe (G). When
TA the outputs of one channel are gated by the strobe
– Device HBM ESD Classification Level 2 input, they are all forced into the high state. When the
– Device CDM ESD Classifcation Level C6 outputs are not disabled by the strobe input, only the
selected output is low while all others are high.
• Wide operating voltage range: 2 V to 6 V
• Schmitt-trigger inputs allow for slow or noisy input Device Information
signals
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
• Low power consumption
SN74HCS139PW-Q1 TSSOP (16) 5.00 mm × 4.40 mm
– Typical ICC of 100 nA
SN74HCS139D-Q1 SOIC (16) 9.90 mm × 3.90 mm
– Typical input leakage current of ±100 nA
• ±7.8-mA output drive at 6 V (1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
• Memory device selection with shared data bus
• Reduce required number of outputs for chip select
applications
• Route data

Low Power Noise Rejection Supports Slow Inputs

Voltage
Voltage

Voltage

Input Voltage
Input
Input

Input

Waveforms
Input Voltage Time Time
Voltage

Standard
Voltage
Supply Current

CMOS Input
Output
Output

Current
Current

Response
Waveforms Input Voltage Time Time

Schmitt-trigger
Voltage

Voltage
Supply Current

CMOS Input
Output

Output
Current

Current

Response
Waveforms Time Time
Input Voltage

Benefits of Schmitt-trigger inputs

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
Copyright © 2020 Texas
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Table of Contents
1 Features............................................................................1 8.3 Device Functional Modes............................................9
2 Applications..................................................................... 1 9 Application and Implementation.................................. 10
3 Description.......................................................................1 9.1 Application Information............................................. 10
4 Revision History.............................................................. 2 9.2 Typical Application.................................................... 10
5 Pin Configuration and Functions...................................3 10 Power Supply Recommendations..............................13
6 Specifications.................................................................. 4 11 Layout........................................................................... 13
6.1 Absolute Maximum Ratings ....................................... 4 11.1 Layout Guidelines................................................... 13
6.2 ESD Ratings .............................................................. 4 11.2 Layout Example...................................................... 13
6.3 Recommended Operating Conditions ........................4 12 Device and Documentation Support..........................14
6.4 Thermal Information ...................................................4 12.1 Documentation Support.......................................... 14
6.5 Electrical Characteristics ............................................5 12.2 Receiving Notification of Documentation Updates..14
6.6 Switching Characteristics ...........................................5 12.3 Support Resources................................................. 14
6.7 Operating Characteristics .......................................... 5 12.4 Trademarks............................................................. 14
6.8 Typical Characteristics................................................ 6 12.5 Electrostatic Discharge Caution..............................14
7 Parameter Measurement Information............................ 7 12.6 Glossary..................................................................14
8 Detailed Description........................................................8 13 Mechanical, Packaging, and Orderable
8.1 Functional Block Diagram........................................... 8 Information.................................................................... 15
8.2 Feature Description.....................................................8

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE REVISION NOTES
September 2020 * Initial Release

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5 Pin Configuration and Functions

1G 1 16 VCC
1A0 2 15 2G
1A1 3 14 2A0
1Y0 4 13 2A1
1Y1 5 12 2Y0
1Y2 6 11 2Y1
1Y3 7 10 2Y2
GND 8 9 2Y3

D or PW Package 16-Pin SOIC or TSSOP Top View

Table 5-1. Pin Functions

PIN
SOIC or TSSOP I/O DESCRIPTION
NAME
NO.
1 1G I Channel 1, output enable, active low
2 1A0 I Channel 1, address select 0
3 1A1 I Channel 1, address select 1
4 1Y0 O Channel 1, output 0
5 1Y1 O Channel 1, output 1
6 1Y2 O Channel 1, output 2
7 1Y3 O Channel 1, output 3
8 GND — Ground
9 2Y3 O Channel 2, output 3
10 2Y2 O Channel 2, output 2
11 2Y1 O Channel 2, output 1
12 2Y0 O Channel 2, output 0
13 2A1 I Channel 2, address select 1
14 2A0 I Channel 2, address select 0
15 2G0 I Channel 2, output enable, active low
16 VCC — Positive supply

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
IIK Input clamp current(2) VI < –0.5 V or VI > VCC + 0.5 V ±20 mA
IOK Output clamp current(2) VI < –0.5 V or VI > VCC + 0.5 V ±20 mA
IO Continuous output current VO = 0 to VCC ±35 mA
Continuous current through VCC or GND ±70 mA
TJ Junction temperature(3) 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) Guaranteed by design.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per AEC Q100-002(1)
±4000
HBM ESD Classification Level 2
V(ESD) Electrostatic discharge V
Charged device model (CDM), per AEC
±1500
Q100-011 CDM ESD Classification Level C6

(1) AEC Q100-002 indicate that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 2 5 6 V
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
TA Ambient temperature –40 125 °C

6.4 Thermal Information

SN74HCS139-Q1
THERMAL METRIC(1) PW (TSSOP) D (SOIC) UNIT
16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 141.2 122.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 78.8 80.9 °C/W
RθJB Junction-to-board thermal resistance 85.8 80.6 °C/W
ΨJT Junction-to-top characterization parameter 27.7 40.4 °C/W
ΨJB Junction-to-board characterization parameter 85.5 80.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
2V 0.7 1.5
VT+ Positive switching threshold 4.5 V 1.7 3.15 V
6V 2.1 4.2
2V 0.3 1.0
VT- Negative switching threshold 4.5 V 0.9 2.2 V
6V 1.2 3.0
2V 0.2 1.0
ΔVT Hysteresis (VT+ - VT- )(1) 4.5 V 0.4 1.4 V
6V 0.6 1.6
IOH = -20 µA 2 V to 6 V VCC – 0.1 VCC – 0.002
VOH High-level output voltage VI = VIH or VIL IOH = -6 mA 4.5 V 4.0 4.3 V
IOH = -7.8 mA 6V 5.4 5.75
IOL = 20 µA 2 V to 6 V 0.002 0.1
VOL Low-level output voltage VI = VIH or VIL IOL = 6 mA 4.5 V 0.18 0.30 V
IOL = 7.8 mA 6V 0.22 0.33
II Input leakage current VI = VCC or 0 6V ±100 ±1000 nA
ICC Supply current VI = VCC or 0, IO = 0 6V 0.1 2 µA
Ci Input capacitance 2 V to 6 V 5 pF

(1) Guaranteed by design.

6.6 Switching Characteristics

CL = 50 pF; over operating free-air temperature range (unless otherwise noted). See Parameter Measurement
Information.
Operating free-air temperature (TA)
PARAMETER FROM TO VCC 25°C –40°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX
2V 19 30 45
A or B Any Y 4.5 V 7 11 18
6V 6 10 14
tpd Propagation delay ns
2V 18 28 45
G Any Y 4.5 V 7 11 18
6V 6 9 15
2V 9 17
tt Transition-time Any output 4.5 V 5 8 ns
6V 4 7

6.7 Operating Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Power dissipation capacitance
Cpd No load 2 V to 6 V 40 pF
per gate

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6.8 Typical Characteristics

TA = 25°C

46 70
VCC = 2 V VCC = 2 V
44 VCC = 3.3 V 65 VCC = 3.3 V
42 VCC = 4.5 V VCC = 4.5 V
VCC = 6 V 60 VCC = 6 V
Output Resistance (:)

Output Resistance (:)

40
38 55

36 50
34 45
32
40
30
28 35

26 30
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25
Output Sink Current (mA) Output Source Current (mA)

Figure 6-1. Output driver resistance in LOW state. Figure 6-2. Output driver resistance in HIGH state.
0.2 0.65
VCC = 2 V 0.6 VCC = 4.5 V
0.18
VCC = 2.5 V 0.55 VCC = 5 V
0.16
ICC ± Supply Current (mA)

ICC ± Supply Current (mA)

0.5
0.14 VCC = 3.3 V 0.45 VCC = 6 V
0.12 0.4
0.35
0.1
0.3
0.08 0.25
0.06 0.2
0.15
0.04
0.1
0.02 0.05
0 0
0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
VI ± Input Voltage (V) VI ± Input Voltage (V)

Figure 6-3. Supply current across input voltage, 2-, Figure 6-4. Supply current across input voltage,
2.5-, and 3.3-V supply 4.5-, 5-, and 6-V supply

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7 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 2.5 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.

Test VCC
Point
Input 50% 50%
0V
From Output
tPLH(1) tPHL(1)
Under Test
VOH
CL(1)
Output 50% 50%
VOL
(1) CL includes probe and test-fixture capacitance. (1) (1)
tPHL tPLH
Figure 7-1. Load Circuit for Push-Pull Outputs VOH
Output 50% 50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-2. Voltage Waveforms Propagation Delays
VCC
90% 90%
Input
10% 10%
0V
tr(1) tf(1)

VOH
90% 90%
Output
10% 10%
VOL
tr(1) tf(1)
(1) The greater between tr and tf is the same as tt.
Figure 7-3. Voltage Waveforms, Input and Output Transition Times

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8 Detailed Description
8.1 Functional Block Diagram

One of Two 2:4 Decoders

DECODER OUTPUT
ENABLE
00
xA0 xY0

01
xY1

10
xA1 xY2

11
xY3

xG

Figure 8-1. Logic Diagram (Positive Logic) for SN74HCS139-Q1 -Q1

8.2 Feature Description

8.2.1 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term "balanced" indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
8.2.2 CMOS Schmitt-Trigger Inputs
This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are
typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table
from the input to ground. The worst case resistance is calculated with the maximum input voltage, given in the
Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics
table, using Ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics
table, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much
slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the
inputs with slow transitioning signals will increase dynamic current consumption of the device. For additional
information regarding Schmitt-trigger inputs, please see Understanding Schmitt Triggers.
8.2.3 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Electrical
Placement of Clamping Diodes for Each Input and Output.

CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.

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VCC
Device

+IIK +IOK

Input Logic Output

-IIK -IOK

GND

Figure 8-2. Electrical Placement of Clamping Diodes for Each Input and Output

8.3 Device Functional Modes

Function Table lists the functional modes of the SN74HCS139-Q1.
Table 8-1. Function Table
INPUTS(1) OUTPUTS
nG nA1 nA0 nY0 nY1 nY2 nY3
L L L L H H H
L L H H L H H
L H L H H L H
L H H H H H L
H X X H H H H

(1) H = High Voltage Level, L = Low Voltage Level, X = Don't Care

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

9.1 Application Information

The SN74HCS139-Q1 is used to control multiple devices that operate on a shared data bus. A decoder provides
the capability to have a binary encoded input activate only one of the device's outputs. This is ideal for solid state
memory applications where multiple devices have to be read or written to with a limited number of GPIO pins
used on the system controller. The decoder is used to activate the chip select (CS) input to the selected memory
device, and the controller can then read or write from that device alone when using a shared bus.
9.2 Typical Application

1Y0 Device A1

DECODER

OUTPUT
ENABLE
1A0 1Y1 Device A2
1A1 2:4 1Y2 Device A3
1Y3 Device A4
1G
System
Controller 2G
2Y0 Device B1
DECODER

OUTPUT
ENABLE
2A0 2Y1 Device B2
2:4

2A1 2Y2 Device B3

2Y3 Device B4

Data Bus

Figure 9-1. Typical application block diagram

9.2.1 Design Requirements

9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the SN74HCS139-Q1 plus the maximum static supply current, ICC, listed in Electrical Characteristics
and any transient current required for switching. The logic device can only source as much current as is provided
by the positive supply source. Be sure not to exceed the maximum total current through VCC listed in the
Absolute Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74HCS139-Q1 plus the maximum supply current, ICC, listed in Electrical Characteristics, and any transient
current required for switching. The logic device can only sink as much current as can be sunk into its ground
connection. Be sure not to exceed the maximum total current through GND listed in the Absolute Maximum
Ratings.
The SN74HCS139-Q1 can drive a load with a total capacitance less than or equal to xx pF while still meeting all
of the datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to
exceed xx pF.
The SN74HCS139-Q1 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage
and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the high state,

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the output voltage in the equation is defined as the difference between the measured output voltage and the
supply voltage at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.

CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.

9.2.1.2 Input Considerations

Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74HCS139-Q1, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SN74HCS139-Q1 has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical
Characteristics. This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than VCC or ground is plotted in the Typical Characteristics.
Refer to the Feature Description section for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Feature Description section for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.

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2. Ensure the capacitive load at the output is ≤ xx pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the
SN74HCS139-Q1 to the receiving device(s).
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.2.3 Application Curve
1G

1A1

1A0

1Y0

1Y1

1Y2

1Y3

2Y0

2Y1

2Y2

2Y3

Figure 9-2. Application timing diagram

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10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
given example layout image.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example

GND VCC

Recommend GND flood fill for

improved signal isolation, noise Bypass capacitor
reduction, and thermal dissipation placed close to the
0.1 F device
Unused input
tied to GND Unused
1G 1 16 VCC inputs tied to
VCC
1A0 2 15 2G
1A1 3 14 2A0
1Y0 4 13 2A1
1Y1 5 12 2Y0
1Y2 6 11 2Y1
Avoid 90°
corners for 1Y3 7 10 2Y2
signal lines GND 8 9 2Y3 Unused
output left
floating

Figure 11-1. Example layout for the SN74HCS139-Q1.

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12 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, HCMOS Design Considerations application report (SCLA007)
• Texas Instruments, CMOS Power Consumption and Cpd Calculation application report (SDYA009)
• Texas Instruments, Designing With Logic application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74HCS139QDRQ1 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HCS139Q

SN74HCS139QPWRQ1 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HCS139Q

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

OTHER QUALIFIED VERSIONS OF SN74HCS139-Q1 :

• Catalog: SN74HCS139

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HCS139QDRQ1 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74HCS139QPWRQ1 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HCS139QDRQ1 SOIC D 16 2500 356.0 356.0 35.0
SN74HCS139QPWRQ1 TSSOP PW 16 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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