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SLOS364A – MARCH 2002 – REVISED AUGUST 2002

1.25-W MONO FULLY DIFFERENTIAL AUDIO POWER AMPLIFIER

FEATURES APPLICATIONS
D 1.25 W Into 8 Ω From a 5-V Supply at D Designed for Wireless or Cellular Handsets
THD = 1% (Typ) and PDAs
D Low Supply Current: 1.7 mA typ
D Shutdown Control <1 µA DESCRIPTION
D Only Five(1) External Components The TPA6203A1 is a 1.25-W mono fully differential
amplifier designed to drive a speaker with at least 8-Ω
– Improved PSRR (90 dB) and Wide Supply
impedance while consuming less than 37 mm2 total
Voltage (2.5 V to 5.5 V) for Direct Battery
printed-circuit board (PCB) area in most applications.
Operation
This device operates from 2.5 V to 5.5 V, drawing only
– Fully Differential Design Reduces RF 1.7 mA of quiescent supply current. The TPA6203A1 is
Rectification available in the space-saving 2 mm x 2 mm MicroStar
– Improved CMRR Eliminates Two Input Junior BGA package.
Coupling Capacitors
Features like 85-dB PSRR from 90 Hz to 5 kHz,
– C(BYPASS) Is Optional Due to Fully
improved RF-rectification immunity, and small PCB
Differential Design and High PSRR
area makes the TPA6203A1 ideal for wireless
handsets. A fast start-up time of 4 µs with minimal pop
makes the TPA6203A1 ideal for PDA applications.

APPLICATION CIRCUIT Actual Solution Size

VDD A3
RF To Battery
RF
RI Cs
– C3 IN– _ VO+ B3
In From
DAC + RI C2 IN+
VO– A1
(1)CB
CS
+

RF 5,25 mm
GND B2
RI
B1
SHUTDOWN Bias
C1 Circuitry
RI
(1)C(BYPASS)

RF
(1) C(BYPASS) is optional
6,9 mm

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroStar Junior is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products Copyright  2002, Texas Instruments Incorporated
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
TPA6203A1 www.ti.com
SLOS364A – MARCH 2002 – REVISED AUGUST 2002

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted(1)
TPA6203A1
Supply voltage, VDD –0.3 V to 5.5 V
Input voltage, VI –0.3 V to VDD +0.3V
Continuous total power dissipation See Dissipation Rating Table
Operating free-air temperature, TA –40°C to 85°C
Junction temperature, TJ –40°C to 150°C
Storage temperature, Tstg –65°C to 150°C
Lead temperature 1,6 mm (1/16 Inch) from case for 10 seconds 260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT
Supply voltage, VDD 2.5 5.5 V
High-level input voltage, VIH SHUTDOWN 2 V
Low-level input voltage, VIL SHUTDOWN 0.8 V
Common-mode input voltage, VIC VDD = 2.5 V, 5.5 V, CMRR ≤ –60 dB 0.5 VDD–0.8 V
Operating free-air temperature, TA –40 85 °C

DISSIPATION RATINGS
TA ≤ 25°C TA = 70°C TA = 85°C
PACKAGE DERATING FACTOR
POWER RATING POWER RATING POWER RATING
GQV 1.10 W 8.8 mW/°C 704 mW 572 mW

ORDERING INFORMATION
PACKAGED DEVICES
MicroStar Junior
(GQV)
Device TPA6203A1GQVR
Symbolization AADI
NOTE: The GQVR is only available taped and reeled. The suffix R
designates taped and reeled parts.

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SLOS364A – MARCH 2002 – REVISED AUGUST 2002

ELECTRICAL CHARACTERISTICS
TA = 25°C, Gain = 1 V/V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output offset voltage (measured
|VOO| VI = 0 V, VDD = 2.5 V to 5.5 V 9 mV
differentially)
PSRR Power supply rejection ratio VDD = 2.5 V to 5.5 V –90 –70 dB
VDD = 3.6 V to 5.5 V, VIC = 0.5 V to VDD–0.8 –70 –65
CMRR Common mode rejection ratio
Common-mode dB
VDD = 2.5 V, VIC = 0.5 V to 1.7 V –62 –55

RL = 8 Ω, VDD = 5.5 V 0.30 0.46

VOL Low-level
Low level out
output
ut voltage VIN+ = VDD, VIN– = 0 V or VDD = 3.6 V 0.22 V
VIN+ = 0 V, VIN– = VDD VDD = 2.5 V 0.19 0.26

RL = 8 Ω, VDD = 5.5 V 4.8 5.12

VOH High-level
High level out
output
ut voltage VIN+ = VDD, VIN– = 0 V or VDD = 3.6 V 3.28 V
VIN+ = 0 V, VIN– = VDD VDD = 2.5 V 2.1 2.24
|IIH| High-level input current VDD = 5.5 V, VI = 5.8 V 1.2 µA
|IIL| Low-level input current VDD = 5.5 V, VI = –0.3 V 1.2 µA
IDD Supply current VDD = 2.5 V to 5.5 V, no load, SHUTDOWN = 2 V 1.7 2 mA
SHUTDOWN = 0.8 V,
IDD(SD) Supply current in shutdown mode 0.01 0.9 µA
VDD = 2.5 V to 5.5 V, no load

OPERATING CHARACTERISTICS
TA = 25°C, Gain = 1 V/V, RL = 8 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD = 5 V 1.25
PO Output
Out ut power
ower THD + N
N= 1%, f = 1 kHz VDD = 3.6 V 0.63 W
VDD = 2.5 V 0.3
VDD = 5 V, PO = 1 W, f = 1 kHz 0.06%
THD+N Total harmonic distortion plus
lus noise VDD = 3.6 V, PO = 0.5 W, f = 1 kHz 0.07%
VDD = 2.5 V, PO = 200 mW, f = 1 kHz 0.08%
C(BYPASS) = 0.47 µF,
VDD = 3.6 V to 5.5 V, f = 217 Hz to 2 kHz,
–87
Inputs ac-grounded VRIPPLE = 200 mVp–p
with CI = 2 µF
C(BYPASS) = 0.47 µF,
VDD = 2.5 V to 3.6 V, f = 217 Hz to 2 kHz,
kSVR Supply ripple rejection ratio –82 dB
Inputs ac-grounded VRIPPLE = 200 mVp–p
with CI = 2 µF
C(BYPASS) = 0.47 µF,
VDD = 2.5 V to 5.5 V, f = 40 Hz to 20 kHz,
≤–74
Inputs ac-grounded VRIPPLE = 200 mVp–p
with CI = 2 µF
SNR Signal-to-noise ratio VDD = 5 V, PO = 1 W 104 dB
No weighting 17
Vn O t t voltage
Output lt noise
i f = 20 H
Hz tto 20 kH
kHz µV
VRMS
A weighting 13
VDD = 2.5 V to 5.5 V, f = 20 Hz to 1 kHz ≤–85
CMRR C
Common-mode
d rejection
j ti ratio
ti dB
VICM = 200 mVp–p f = 20 Hz to 20 kHz ≤–74
ZI Input impedance 2 MΩ
Shutdown attenuation f = 20 Hz to 20 kHz, RF = RI = 20 kΩ –80 dB

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SLOS364A – MARCH 2002 – REVISED AUGUST 2002

MicroStar Juniort (GQV) Package

(TOP VIEW)

GND
1 2 3
VO– A VDD
B VO+
SHUTDOWN
BYPASS C
IN–

IN+
(SIDE VIEW)

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
BYPASS C1 I Mid-supply voltage. Connect a capacitor to GND for BYPASS voltage filtering. Bypass capacitor is optional.
GND B2 I High-current ground
IN– C3 I Negative differential input
IN+ C2 I Positive differential input
SHUTDOWN B1 I Shutdown terminal. Pull this pin low (≤0.8 V) to place the device in shutdown and pull it high (≥2 V) for active mode.
VDD A3 I Supply voltage terminal
VO+ B3 O Positive BTL output
VO– A1 O Negative BTL output

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SLOS364A – MARCH 2002 – REVISED AUGUST 2002

TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
vs Supply voltage 1
PO Output power
vs Load resistance 2, 3
PD Power dissipation vs Output power 4, 5
Maximum ambient temperature vs Power dissipation 6
vs Output power 7, 8
Total harmonic distortion + noise vs Frequency 9, 10, 11, 12
vs Common-mode input voltage 13
Supply voltage rejection ratio vs Frequency 14, 15, 16, 17
Supply voltage rejection ratio vs Common-mode input voltage 18
GSM Power supply rejection vs Time 19
GSM Power supply rejection vs Frequency 20
vs Frequency 21
CMRR Common mode rejection ratio
Common-mode
vs Common-mode input voltage 22
Closed loop gain/phase vs Frequency 23
Open loop gain/phase vs Frequency 24
vs Supply voltage 25
IDD Supply current
vs Shutdown voltage 26
Start-up time vs Bypass capacitor 27

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TYPICAL CHARACTERISTICS

OUTPUT POWER OUTPUT POWER OUTPUT POWER

vs vs vs
SUPPLY VOLTAGE LOAD RESISTANCE LOAD RESISTANCE
1.8 1.4 1.8
RL = 8 Ω f = 1 kHz f = 1 kHz
1.6 1.6 THD+N = 10%
f = 1 kHz 1.2 THD+N = 1%
Gain = 1 V/V Gain = 1 V/V Gain = 1 V/V
1.4 1.4
PO – Output Power – W

PO – Output Power – W
VDD = 5 V

PO – Output Power – W
1 VDD = 5 V
1.2 1.2
THD+N = 10%
VDD = 3.6 V VDD = 3.6 V
1 0.8 1

0.8 VDD = 2.5 V 0.8 VDD = 2.5 V

0.6
0.6 THD+N = 1% 0.6
0.4
0.4 0.4

0.2 0.2 0.2

0 0 0
2.5 3 3.5 4 4.5 5 8 13 18 23 28 32 8 13 18 23 28 32
VDD – Supply Voltage – V RL – Load Resistance – Ω RL – Load Resistance – Ω

Figure 1 Figure 2 Figure 3

POWER DISSIPATION POWER DISSIPATION MAXIMUM AMBIENT TEMPERATURE

vs vs vs
OUTPUT POWER OUTPUT POWER POWER DISSIPATION
0.4 0.7 90
VDD = 3.6 V VDD = 5 V
0.35 80

Maximum Ambient Temperature –° C

0.6 8Ω
PD – Power Dissipation – W

PD – Power Dissipation – W

0.3 8Ω 70
0.5
60
0.25
0.4 50
0.2
0.3 40
0.15
16 Ω
16 Ω 30
0.2
0.1
20
0.05 0.1
10
0 0 0
0 0.2 0.4 0.6 0.8 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
PO – Output Power – W PO – Output Power – W PD – Power Dissipation – W

Figure 4 Figure 5 Figure 6

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs vs
OUTPUT POWER OUTPUT POWER FREQUENCY
THD+N – Total Harmonic Distortion + Noise – %

THD+N – Total Harmonic Distortion + Noise – %

THD+N – Total Harmonic Distortion + Noise – %

10 10 10
RL = 16 Ω 5 VDD = 5 V
5 5 f = 1 kHz CI = 2 µF 50 mW
C(Bypass) = 0 to 1 µF 2
2.5 V RL = 8 Ω
2 2 1
Gain = 1 V/V C(Bypass) = 0 to 1 µF
3.6 V 0.5 Gain = 1 V/V
1 1

0.5 5V 0.2 250 mW

0.5 2.5 V
5V 0.1
0.2 0.2 0.05
3.6 V
0.1 0.1 0.02 1W
0.01
0.05 0.05
RL = 8 Ω, f = 1 kHz 0.005
0.02 C(Bypass) = 0 to 1 µF 0.02 0.002
Gain = 1 V/V
0.01 0.01 0.001
10 m 100 m 1 2 3 10 m 100 m 1 2 20 100 200 1k 2k 10 k 20 k
PO – Output Power – W PO – Output Power – W f – Frequency – Hz

Figure 7 Figure 8 Figure 9

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SLOS364A – MARCH 2002 – REVISED AUGUST 2002

TYPICAL CHARACTERISTICS

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs vs
FREQUENCY FREQUENCY FREQUENCY

THD+N – Total Harmonic Distortion + Noise – %

THD+N – Total Harmonic Distortion + Noise – %

THD+N – Total Harmonic Distortion + Noise – %

10 10 10
VDD = 3.6 V 5 VDD = 3.6 V
5 25 mW 5 VDD = 2.5 V
CI = 2 µF CI = 2 µF
CI = 2 µF 15 mW
2
2 RL = 8 Ω 2
RL = 16 Ω 25 mW
RL = 8 Ω
1 C(Bypass) = 0 to 1 µF 1 1 C(Bypass) = 0 to 1 µF
C(Bypass) = 0 to 1 µF
0.5 Gain = 1 V/V 0.5 0.5 Gain = 1 V/V
Gain = 1 V/V
0.2 0.2 0.2 125 mW
0.1 0.1 0.1
125 mW
0.05 0.05 75 mW 0.05

0.02 0.02 0.02

500 mW
0.01 0.01 200 mW 0.01 250 mW
0.005 0.005 0.005

0.002 0.002 0.002

0.001 0.001 0.001
20 50 100 200 500 1 k 2 k 5 k 10 k 20 k 20 50 100 200 500 1 k 2 k 5 k 10 k 20 k 20 50 100 200 500 1 k 2 k 5 k 10 k 20 k
f – Frequency – Hz f – Frequency – Hz f – Frequency – Hz

Figure 10 Figure 11 Figure 12

TOTAL HARMONIC DISTORTION + NOISE SUPPLY VOLTAGE REJECTION RATIO SUPPLY VOLTAGE REJECTION RATIO
vs vs vs
COMMON MODE INPUT VOLTAGE FREQUENCY FREQUENCY
THD+N – Total Harmonic Distortion + Noise – %

10 0 0
– Supply Voltage Rejection Ratio – dB

– Supply Voltage Rejection Ratio – dB

f = 1 kHz –10 CI = 2 µF –10
Gain = 5 V/V
PO = 200 mW RL = 8 Ω CI = 2 µF
–20 C(Bypass) = 0.47 µF –20 RL = 8 Ω
Vp-p = 200 mV C(Bypass) = 0.47 µF
–30 –30
1 Inputs ac-Grounded Vp-p = 200 mV
–40 Gain = 1 V/V –40 Inputs ac-Grounded

–50 –50
VDD = 2.5 V VDD =2. 5 V
–60 –60 VDD = 5 V
VDD =2. 5 V
0.10 –70 VDD = 5 V –70
VDD = 3.6 V –80 –80
VDD = 3.6 V
SVR

–90
SVR

–90
VDD = 3.6 V
–100 –100
k

0.01
k

0 0.5 1 1.5 2 2.5 3 3.5 20 50 100 200 500 1 k 2 k 5 k 10 k 20 k 20 50 100 200 500 1 k 2 k 5 k 10 k 20 k
VIC – Common Mode Input Voltage – V f – Frequency – Hz f – Frequency – Hz

Figure 13 Figure 14 Figure 15

SUPPLY VOLTAGE REJECTION RATIO SUPPLY VOLTAGE REJECTION RATIO SUPPLY VOLTAGE REJECTION RATIO
vs vs vs
FREQUENCY FREQUENCY COMMON-MODE INPUT VOLTAGE
0 0 –10
– Supply Voltage Rejection Ratio – dB
– Supply Voltage Rejection Ratio – dB
– Supply Voltage Rejection Ratio – dB

CI = 2 µF VDD = 3.6 V f = 217 Hz

–10 –10
RL = 8 Ω CI = 2 µF –20 C(Bypass) = 0.47 µF
–20 Inputs Floating –20 RL = 8 Ω RL = 8 Ω
Gain = 1 V/V Inputs ac-Grounded –30 Gain = 1 V/V
–30 –30
Gain = 1 V/V
–40 –40 –40 VDD = 2.5 V VDD = 3.6 V
C(Bypass) = 0
–50 –50 C(Bypass) = 0.47 µF –50
VDD =2. 5 V
–60 –60
VDD = 5 V C(Bypass) = 1 µF –60
–70 –70
VDD = 3.6 V –70
–80 –80 C(Bypass) = 0.1 µF
–80
SVR

VDD = 5 V
SVR

–90
SVR

–90
–100 –100 –90
k
k
k

20 50 100 200 500 1 k 2 k 5 k 10 k 20 k 20 50 100 200 500 1 k 2 k 5 k 10 k 20 k 0 1 2 3 4 5

f – Frequency – Hz f – Frequency – Hz VIC – Common Mode Input Voltage – V

Figure 16 Figure 17 Figure 18

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SLOS364A – MARCH 2002 – REVISED AUGUST 2002

TYPICAL CHARACTERISTICS

GSM POWER SUPPLY REJECTION GSM POWER SUPPLY REJECTION

vs vs
TIME FREQUENCY

V DD – Supply Voltage – dBV

0
VDD
C1
Frequency –50
217.41 Hz
C1 – Duty –100
Voltage – V

20 %

VO – Output Voltage – dBV

C1 High 0 –150
3.598 V VDD Shown in Figure 19
CI = 2 µF,
–50 C(Bypass) = 0.47 µF,
C1 Pk–Pk
504 mV Inputs ac-Grounded
VO Gain = 1V/V
–100

–150
Ch1 100 mV/div 2 ms/div 0 200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k
Ch4 10 mV/div f – Frequency – Hz
t – Time – ms

Figure 19 Figure 20

COMMON-MODE REJECTION RATIO COMMON-MODE REJECTION RATIO

vs vs
FREQUENCY COMMON-MODE INPUT VOLTAGE
CMRR – Common Mode Rejection Ratio – dB

CMRR – Common Mode Rejection Ratio – dB

0 0

–10
VDD = 2.5 V to 5 V –10 RL = 8 Ω
VIC = 200 mVp–p Gain = 1 V/V
–20 RL = 8 Ω –20
Gain = 1 V/V –30
–30

–40 –40
VDD = 2.5 V
–50 –50
VDD = 5 V
–60 –60

–70 –70
–80 –80

–90 –90
VDD = 3.6 V
–100 –100
20 50 100 200 500 1 k 2 k 5 k 10 k 20 k 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
f – Frequency – Hz VIC – Common Mode Input Voltage – V

Figure 21 Figure 22

CLOSED LOOP GAIN/PHASE OPEN LOOP GAIN/PHASE

vs vs
FREQUENCY FREQUENCY
40 220
Phase 200 200
30 180 VDD = 3.6 V
20
150 RL = 8 Ω 150
140
10 100 100 100
Gain
Phase – Degrees

Gain
Phase – Degrees

0 60
50 50
Gain – dB

Gain – dB

–10 20
–20 –20 0 0

–30 –60 –50 –50

–40 –100 Phase
VDD = 3.6 V –100 –100
–50 –140
RL = 8 Ω
–60 Gain = 1 V/V –180 –150 –150
–70 –220
–200 –200
10 100 1k 10 k 100 k 1 M 10 M
100 1k 10 k 100 k 1M 10 M
f – Frequency – Hz
f – Frequency – Hz
Figure 23 Figure 24

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SLOS364A – MARCH 2002 – REVISED AUGUST 2002

TYPICAL CHARACTERISTICS
SUPPLY CURRENT SUPPLY CURRENT
vs vs
SUPPLY VOLTAGE SHUTDOWN VOLTAGE
1.8 1.8

1.6 1.6

I DD – Supply Current – mA
1.4
I DD – Supply Current – mA

1.4
VDD = 2.5 V
1.2
1.2
1.0 VDD = 3.6 V
1
0.8 VDD = 5 V
0.8
0.6
0.6

0.4 0.4

0.2 0.2

0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2
VDD – Supply Voltage – V Voltage on SHUTDOWN Terminal – V

Figure 25 Figure 26

START-UP TIME(1)
vs
BYPASS CAPACITOR
6

5
Start-Up Time – ms

0
0 0.5 1 1.5 2
C(Bypass) – Bypass Capacitor – µF

(1) Start-Up time is the time it takes (from a

low-to-high transition on SHUTDOWN) for the
gain of the amplifier to reach –3 dB of the final
gain.

Figure 27

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APPLICATION INFORMATION
FULLY DIFFERENTIAL AMPLIFIER However, removing the bypass capacitor slightly
worsens power supply rejection ratio (kSVR), but a
The TPA6203A1 is a fully differential amplifier with slight decrease of kSVR may be acceptable when an
differential inputs and outputs. The fully differential additional component can be eliminated (see
amplifier consists of a differential amplifier and a common- Figure 17).
mode amplifier. The differential amplifier ensures that the
amplifier outputs a differential voltage that is equal to the D Better RF-immunity:
differential input times the gain. The common-mode GSM handsets save power by turning on and shutting
feedback ensures that the common-mode voltage at the off the RF transmitter at a rate of 217 Hz. The
output is biased around VDD/2 regardless of the common- transmitted signal is picked-up on input and output
mode voltage at the input. traces. The fully differential amplifier cancels the
signal much better than the typical audio amplifier.
Advantages of Fully Differential Amplifiers
D Input coupling capacitors not required:
A fully differential amplifier with good CMRR, like the APPLICATION SCHEMATICS
TPA6203A1, allows the inputs to be biased at voltage
Figure 28 through Figure 30 show application schematics
other than mid-supply. For example, if a DAC has
for differential and single-ended inputs. Typical values are
mid-supply lower than the mid-supply of the
shown in Table 1.
TPA6203A1, the common-mode feedback circuit
adjusts for that, and the TPA6203A1 outputs are still
biased at mid-supply of the TPA6203A1. The inputs of Table 1. Typical Component Values
the TPA6203A1 can be biased from 0.5 V to VDD – 0.8 COMPONENT VALUE
V. If the inputs are biased outside of that range, input
RI 10 kΩ
coupling capacitors are required.
RF 10 kΩ
D Mid-supply bypass capacitor, C(BYPASS), not required: C(BYPASS)(1) 0.22 µF
The fully differential amplifier does not require a
CS 1 µF
bypass capacitor. This is because any shift in the mid-
supply affects both positive and negative channels CI 0.22 µF
equally and cancels at the differential output. (1) C(BYPASS) is optional

VDD A3
RF To Battery

Cs
– RI C3 IN– _ VO+ B3
In From
DAC + RI VO– A1
C2 IN+
+

RF GND B2
B1
SHUTDOWN Bias
C1 Circuitry
†
C(BYPASS)

† C(BYPASS) is optional

Figure 28. Typical Differential Input Application Schematic

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VDD A3
RF To Battery

CI Cs
RI C3 IN–
– _ VO+ B3
IN RI VO– A1
+ C2 IN+
+
CI RF GND B2
B1
SHUTDOWN Bias
C1 Circuitry
†
C(BYPASS)

† C(BYPASS) is optional

Figure 29. Differential Input Application Schematic Optimized With Input Capacitors

VDD A3
RF To Battery
CI Cs
RI
C3 IN– _ VO+ B3
IN
RI VO– A1
C2 IN+
+
CI
RF GND B2
B1
SHUTDOWN Bias
C1 Circuitry
†
C(BYPASS)

† C(BYPASS) is optional

Figure 30. Single-Ended Input Application Schematic

Selecting Components Bypass Capacitor (CBYPASS ) and Start-Up Time
The internal voltage divider at the BYPASS pin of this
Resistors (RF and RI ) device sets a mid-supply voltage for internal references
The input (RI) and feedback resistors (RF) set the gain of and sets the output common mode voltage to VDD/2.
the amplifier according to equation 1. Adding a capacitor to this pin filters any noise into this pin
and increases the kSVR. C(BYPASS) also determines the
Gain = RF/RI rise time of VO+ and VO– when the device is taken out of
(1)
shutdown. The larger the capacitor, the slower the rise
RF and RI should range from 1 kΩ to 100 kΩ. Most graphs time. Although the output rise time depends on the bypass
were taken with RF = RI = 20 kΩ. capacitor value, the device passes audio 4 µs after taken
out of shutdown and the gain is slowly ramped up based
Resistor matching is very important in fully differential on C(BYPASS).
amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors. Input Capacitor (CI )
CMRR, PSRR, and the cancellation of the second The TPA6203A1 does not require input coupling
harmonic distortion diminishes if resistor mismatch capacitors if using a differential input source that is biased
occurs. Therefore, it is recommended to use 1% tolerance from 0.5 V to VDD – 0.8 V. Use 1% tolerance or better
resistors or better to keep the performance optimized. gain-setting resistors if not using input coupling capacitors.

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In the single-ended input application an input capacitor, CI, 10-µF or greater capacitor placed near the audio power
is required to allow the amplifier to bias the input signal to amplifier also helps, but is not required in most
the proper dc level. In this case, CI and RI form a high-pass applications because of the high PSRR of this device.
filter with the corner frequency determined in equation 2.
USING LOW-ESR CAPACITORS
1 Low-ESR capacitors are recommended throughout this
fc + applications section. A real (as opposed to ideal) capacitor
2p R C
I I (2) can be modeled simply as a resistor in series with an ideal
capacitor. The voltage drop across this resistor minimizes
the beneficial effects of the capacitor in the circuit. The
–3 dB
lower the equivalent value of this resistance the more the
real capacitor behaves like an ideal capacitor.

DIFFERENTIAL OUTPUT VERSUS SINGLE-

ENDED OUTPUT
Figure 31 shows a Class-AB audio power amplifier (APA)
in a fully differential configuration. The TPA6203A1
amplifier has differential outputs driving both ends of the
fc load. There are several potential benefits to this differential
drive configuration, but initially consider power to the load.
The differential drive to the speaker means that as one side
The value of CI is important to consider as it directly affects
is slewing up, the other side is slewing down, and vice
the bass (low frequency) performance of the circuit.
versa. This in effect doubles the voltage swing on the load
Consider the example where RI is 10 kΩ and the
as compared to a ground referenced load. Plugging 2 ×
specification calls for a flat bass response down to 100 Hz.
VO(PP) into the power equation, where voltage is squared,
Equation 2 is reconfigured as equation 3.
yields 4× the output power from the same supply rail and
load impedance (see equation 4).
C + 1
I 2p R f c V
I (3) O(PP)
V (rms) +
2 Ǹ2
In this example, CI is 0.16 µF, so one would likely choose
a value in the range of 0.22 µF to 0.47 µF. A further 2
V
consideration for this capacitor is the leakage path from (rms)
the input source through the input network (RI, CI) and the
Power +
R
feedback resistor (RF) to the load. This leakage current L (4)
VDD
creates a dc offset voltage at the input to the amplifier that
reduces useful headroom, especially in high gain
applications. For this reason, a ceramic capacitor is the
best choice. When polarized capacitors are used, the
positive side of the capacitor should face the amplifier VO(PP)
input in most applications, as the dc level there is held at
VDD/2, which is likely higher than the source dc level. It is
important to confirm the capacitor polarity in the
application.
RL 2x VO(PP)
Decoupling Capacitor (CS ) VDD
The TPA6203A1 is a high-performance CMOS audio
amplifier that requires adequate power supply decoupling
to ensure the output total harmonic distortion (THD) is as
low as possible. Power supply decoupling also prevents –VO(PP)
oscillations for long lead lengths between the amplifier and
the speaker. For higher frequency transients, spikes, or
digital hash on the line, a good low equivalent-series-
resistance (ESR) ceramic capacitor, typically 0.1 µF to
1 µF, placed as close as possible to the device VDD lead
works best. For filtering lower frequency noise signals, a Figure 31. Differential Output Configuration
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 www.ti.com TPA6203A1
SLOS364A – MARCH 2002 – REVISED AUGUST 2002

In a typical wireless handset operating at 3.6 V, bridging Increasing power to the load does carry a penalty of
raises the power into an 8-Ω speaker from a singled-ended increased internal power dissipation. The increased
(SE, ground reference) limit of 200 mW to 800 mW. In dissipation is understandable considering that the BTL
sound power that is a 6-dB improvement—which is configuration produces 4× the output power of the SE
loudness that can be heard. In addition to increased power configuration.
there are frequency response concerns. Consider the
single-supply SE configuration shown in Figure 32. A FULLY DIFFERENTIAL AMPLIFIER
coupling capacitor is required to block the dc offset voltage EFFICIENCY AND THERMAL INFORMATION
from reaching the load. This capacitor can be quite large
(approximately 33 µF to 1000 µF) so it tends to be Class-AB amplifiers are inefficient. The primary cause of
expensive, heavy, occupy valuable PCB area, and have these inefficiencies is voltage drop across the output stage
the additional drawback of limiting low-frequency transistors. There are two components of the internal
performance of the system. This frequency-limiting effect
voltage drop. One is the headroom or dc voltage drop that
is due to the high pass filter network created with the varies inversely to output power. The second component
speaker impedance and the coupling capacitance and is is due to the sinewave nature of the output. The total
calculated with equation 5. voltage drop can be calculated by subtracting the RMS
value of the output voltage from VDD. The internal voltage
1 drop multiplied by the average value of the supply current,
fc +
2p R C IDD(avg), determines the internal power dissipation of the
L C (5) amplifier.

For example, a 68-µF capacitor with an 8-Ω speaker would An easy-to-use equation to calculate efficiency starts out
attenuate low frequencies below 293 Hz. The BTL as being equal to the ratio of power from the power supply
configuration cancels the dc offsets, which eliminates the to the power delivered to the load. To accurately calculate
need for the blocking capacitors. Low-frequency the RMS and average values of power in the load and in
performance is then limited only by the input network and the amplifier, the current and voltage waveform shapes
speaker response. Cost and PCB space are also must first be understood (see Figure 33).
minimized by eliminating the bulky coupling capacitor.
VO

VDD
V(LRMS)
VO(PP)

IDD
CC
VO(PP)
RL
IDD(avg)

Figure 33. Voltage and Current Waveforms for

–3 dB BTL Amplifiers

Although the voltages and currents for SE and BTL are

sinusoidal in the load, currents from the supply are very
different between SE and BTL configurations. In an SE
application the current waveform is a half-wave rectified
shape, whereas in BTL it is a full-wave rectified waveform.
This means RMS conversion factors are different. Keep in
fc mind that for most of the waveform both the push and pull
transistors are not on at the same time, which supports the
fact that each amplifier in the BTL device only draws
current from the supply for half the waveform. The
Figure 32. Single-Ended Output and Frequency following equations are the basis for calculating amplifier
Response efficiency.

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TPA6203A1 www.ti.com
SLOS364A – MARCH 2002 – REVISED AUGUST 2002

P (6)
Efficiency of a BTL amplifier + L
P
SUP
Where: 2
V rms 2 V V
P + L , and V + P , therefore, P + P
L R LRMS Ǹ2 L 2R
L L
p V V 2V
1
and P SUP + VDD I DDavg and I DDavg + p ŕ R
P sin(t) dt + 1
p R
P [cos(t)] p +
0 pR
P
L
0 L L
Therefore,
V 2V
P DD P
+
SUP pR
L
substituting PL and PSUP into equation 6, PL = Power delivered to load
2 PSUP = Power drawn from power supply
VP VLRMS = RMS voltage on BTL load
2 RL p VP RL = Load resistance
Efficiency of a BTL amplifier + + VP = Peak voltage on BTL load
2 V DD V P 4 VDD IDDavg = Average current drawn from the
p RL power supply
Where: VDD = Power supply voltage
ηBTL = Efficiency of a BTL amplifier
V
P
+ Ǹ2 PL RL

Therefore, (7)
p Ǹ2 PL RL
h BTL +
4V
DD

Table 2. Efficiency and Maximum Ambient Temperature vs Output Power in 5-V 8-Ω BTL Systems
Output Power Efficiency Internal Dissipation Power From Supply Max Ambient Temperature
(W) (%) (W) (W) (°C)
0.25 31.4 0.55 0.75 87
0.50 44.4 0.62 1.12 78
1.00 62.8 0.59 1.59 82
1.25 70.2 0.53 1.78 89

Table 2 employs equation 7 to calculate efficiencies for A simple formula for calculating the maximum power
four different output power levels. Note that the efficiency dissipated, PDmax, may be used for a differential output
of the amplifier is quite low for lower power levels and rises application:
sharply as power to the load is increased resulting in a 2V2 (8)
nearly flat internal power dissipation over the normal DD
P Dmax +
operating range. Note that the internal dissipation at full p 2R L
output power is less than in the half power range.
Calculating the efficiency for a specific system is the key PDmax for a 5-V, 8-Ω system is 634 mW.
to proper power supply design. For a 1.25-W audio system The maximum ambient temperature depends on the heat
with 8-Ω loads and a 5-V supply, the maximum draw on the sinking ability of the PCB system. The derating factor for
power supply is almost 1.8 W. the 2 mm x 2 mm Microstar Junior package is shown in
A final point to remember about Class-AB amplifiers is how the dissipation rating table (see page 2). Converting this to
to manipulate the terms in the efficiency equation to the ΘJA:
utmost advantage when possible. Note that in equation 7, (9)
Θ + 1 + 1 + 113°CńW
VDD is in the denominator. This indicates that as VDD goes JA Derating Factor 0.0088
down, efficiency goes up.

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 www.ti.com TPA6203A1
SLOS364A – MARCH 2002 – REVISED AUGUST 2002

Given ΘJA, the maximum allowable junction temperature, PCB LAYOUT

and the maximum internal dissipation, the maximum
ambient temperature can be calculated with the following In making the pad size for the BGA balls, it is
equation. The maximum recommended junction recommended that the layout use solder-mask-defined
temperature for the TPA6203A1 is 150°C. (SMD) land. With this method, the copper pad is made
larger than the desired land area, and the opening size is
defined by the opening in the solder mask material. The
T A Max + T J Max * ΘJA P Dmax (10)
advantages normally associated with this technique
+ 150 * 113(0.634) + 78.4°C include more closely controlled size and better copper
adhesion to the laminate. Increased copper also increases
the thermal performance of the IC. Better size control is
Equation 10 shows that the maximum ambient
the result of photo imaging the stencils for masks. Small
temperature is 78.4°C at maximum power dissipation with
plated vias should be placed near the center ball
a 5-V supply.
connecting ball B2 to the ground plane. Added plated vias
and ground plane act as a heatsink and increase the
Table 2 shows that for most applications no airflow is
thermal performance of the device. Figure 34 shows the
required to keep junction temperatures in the specified
appropriate diameters for a 2mm X 2mm MicroStar
range. The TPA6203A1 is designed with thermal
Junior BGA layout.
protection that turns the device off when the junction
temperature surpasses 150°C to prevent damage to the It is very important to keep the TPA6203A1 external
IC. Also, using more resistive than 8-Ω speakers components very close to the TPA6203A1 to limit noise
dramatically increases the thermal performance by pickup. The TPA6203A1 evaluation module (EVM) layout
reducing the output current. is shown in the next section as a layout example.
0.38 mm

0.25 mm 0.28 mm

C1 B1 A1

C2 B2 VIAS to Ground Plane

Solder Mask
C3 B3 A3
Paste Mask (Stencil)

Copper Trace

Figure 34. MicroStar Junior BGA Recommended Layout

15
TPA6203A1 www.ti.com
SLOS364A – MARCH 2002 – REVISED AUGUST 2002

TPA6203A1 EVM PCB Layers

The following illustrations depict the TPA6203A1 EVM PCB layers and silkscreen. These drawings are enlarged to better
show the routing. Gerber plots can be obtained from any TI sales office.

Only Required
Circuitry for Most
Applications

Figure 35. TPA6203A1 EVM Top Layer (Not to Scale)

Figure 36. TPA6203A1 EVM Bottom Layer (Not to Scale)

16
 www.ti.com TPA6203A1
SLOS364A – MARCH 2002 – REVISED AUGUST 2002

MECHANICAL DATA
GQV (S-PBGA-N8) PLASTIC BALL GRID ARRAY

2,10
SQ 1,00 TYP
1,90
0,50

0,50
C

B 1,00 TYP

1 2 3

(BOTTOM VIEW)

0,68
0,62 1,00 MAX

Seating Plane

0,35
0,08
0,25 0,21
0,11
∅ 0,05 M
4201040/C 11/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. MicroStar Junior configuration
D. Falls within JEDEC MO-225

MicroStar Junior is a trademark of Texas Instruments.

17
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