SN74ACT574

SCAS537F – OCTOBER 1995 – REVISED FEBRUARY 2024

SN74ACT574 Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs

1 Features 2 Description
• Operation of 4.5V to 5.5V VCC These 8-bit flip-flops feature 3-state outputs designed
• Inputs accept voltages to 5.5V specifically for driving highly capacitive or relatively
• Max tpd of 9ns at 5V low-impedance loads. The devices are particularly
• Inputs are TTL-voltage compatible suitable for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
DB (SSOP, 20) 7.2mm × 7.8mm 7.2mm × 5.30mm
12.80mm ×
DW (SOIC, 20) 12.80mm × 7.5mm
10.3mm
SN74ACT574
N (PDIP, 20) 24.33mm × 9.4mm 24.33mm × 6.35mm
NS (SOP, 20) 12.6mm × 7.8mm 12.6mm × 5.3mm
PW (TSSOP, 20) 6.50mm × 6.4mm 6.50mm × 4.40mm

(1) For more information, see Section 10.

(2) The package size (length × width) is a nominal value and
includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does
not include pins.

Logic Diagram (Positive Logic)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN74ACT574
SCAS537F – OCTOBER 1995 – REVISED FEBRUARY 2024 www.ti.com

Table of Contents
1 Features............................................................................1 6.2 Functional Block Diagram........................................... 8
2 Description.......................................................................1 6.3 Device Functional Modes............................................8
3 Pin Configuration and Functions...................................3 7 Application and Implementation.................................... 9
4 Specifications.................................................................. 4 7.1 Power Supply Recommendations...............................9
4.1 Absolute Maximum Ratings........................................ 4 7.2 Layout......................................................................... 9
4.2 ESD Ratings............................................................... 4 8 Device and Documentation Support............................10
4.3 Recommended Operating Conditions.........................4 8.1 Documentation Support (Analog)..............................10
4.4 Thermal Information....................................................4 8.2 Receiving Notification of Documentation Updates....10
4.5 Electrical Characteristics.............................................5 8.3 Support Resources................................................... 10
4.6 Timing Requirements.................................................. 5 8.4 Trademarks............................................................... 10
4.7 Switching Characteristics............................................5 8.5 Electrostatic Discharge Caution................................10
4.8 Operating Characteristics........................................... 6 8.6 Glossary....................................................................10
5 Parameter Measurement Information............................ 7 9 Revision History............................................................ 10
6 Detailed Description........................................................8 10 Mechanical, Packaging, and Orderable
6.1 Overview..................................................................... 8 Information.................................................................... 11

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3 Pin Configuration and Functions

Figure 3-1. SN74ACT574 DB, DW, N, NS, or PW Package (Top View)

Table 3-1. Pin Functions

PIN
I/O DESCRIPTION
NAME NO.
OE 1 Input Output enable for all channels, active low
D1 2 Input Input for channel 1
D2 3 Input Input for channel 2
D3 4 Input Input for channel 3
D4 5 Input Input for channel 4
D5 6 Input Input for channel 5
D6 7 Input Input for channel 6
D7 8 Input Input for channel 7
D8 9 Input Input for channel 8
GND 10 — Ground
CLK 11 Input Clock input for all channels, rising edge triggered
Q8 12 Output Output for channel 8
Q7 13 Output Output for channel 7
Q6 14 Output Output for channel 6
Q5 15 Output Output for channel 5
Q4 16 Output Output for channel 4
Q3 17 Output Output for channel 3
Q2 18 Output Output for channel 2
Q1 19 Output Output for channel 1
VCC 20 — Postive supply

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4 Specifications
4.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage range −0.5 7 V
2
VI Input voltage range −0.5 VCC + 0.5 V
2
VO Output voltage range −0.5 VCC + 0.5 V
IIK Input clamp current (VI < 0 or VI > VCC) ±20 mA
IOK Output clamp current (VO < 0 or VO > VCC) ±20 mA
IO Continuous output current (VO = 0 to VCC) ±50 mA
Continuous current through VCC or GND ±200 mA
Tstg Storage temperature range −65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

4.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)1
SN74ACT574
UNIT
MIN MAX
VCC Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
IOH High-level output current –8 mA
IOL Low-level output current 8 mA
∆t/∆v Input transition rise or fall rate 20 ns/V
TA Operating free-air temperature –40 85 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

4.4 Thermal Information

SN74ACT574
THERMAL METRIC(1) DB DW N NS PW UNIT
20 PINS
Junction-to-ambient thermal
RθJA 70 101.2 69 106.2 126.2 °C/W
resistance

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

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4.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C SN74ACT574
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX
4.5 V 4.4 4.49 4.4
IOH = –50 µA
5.5 V 5.4 5.49 5.4
4.5 V 3.86 3.76
VOH IOH = –24 mA V
5.5 V 4.86 4.76
1
IOH = –50 mA 5.5 V
1
IOH = –75 mA 5.5 V 3.85
4.5 V 0.1 0.1
IOL = 50 µA
5.5 V 0.1 0.1
4.5 V 0.36 0.44
VOL IOL = 24 mA V
5.5 V 0.36 0.44
1
IOL = 50 mA 5.5 V
1
IOL = 75 mA 5.5 V 1.65
IOZ V O = VCC or GND 5.5 V ±0.25 ±2.5 µA
II V I = VCC or GND 5.5 V ±0.1 ±1 µA
ICC VI = VCC or GND, IO = 0 5.5 V 4 40 µA
2 One input at 3.4 V,
ΔICC 5.5 V 0.6 1.5 mA
Other inputs at GND or VCC
Ci VI = VCC or GND 5V 4.5 pF

(1) Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
(2) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.

4.6 Timing Requirements

over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Load Circuit and
Voltage Waveforms)
TA = 25°C SN74ACT574
PARAMETER UNIT
MIN MAX MIN MAX
fclock Clock frequency 100 85 MHz
tw Pulse duration, CLK high or low 3 4 ns
tsu Setup time, data before CLK↑ 2.5 2.5 ns
th Hold time, data after CLK↑ 1 1 ns

4.7 Switching Characteristics

over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Load Circuit and
Voltage Waveforms)
FROM TO TA = 25°C SN74ACT574
PARAMETER UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX
fmax 100 110 85 MHz
2.5 7 11 2 12
tpd CLK Q ns
2 6.5 10 1.5 11
2 6.4 9.5 1.5 10
tPHL OE Q ns
2 6 9 1.5 10
2 7 10.5 1.5 11.5
tt OE Q ns
2 5.5 8.5 1.5 9

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4.8 Operating Characteristics

VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance CL = 50 pF, f = 1 MHz 40 pF

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5 Parameter Measurement Information

Figure 5-1. Load Circuit and Voltage Waveforms

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6 Detailed Description
6.1 Overview
The eight flip-flops of the ’ACT574 devices are D-type edge-triggered flip-flops. On the positive transition of the
clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
in a bus-organized system without need for interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
6.2 Functional Block Diagram

Figure 6-1. Logic Diagram (Positive Logic)

6.3 Device Functional Modes

Table 6-1. Function Table (Each Flip-flop)
INPUTS
OUTPUT Q
OE CLK D
L ↑ H H
L ↑ L L
L H or L X Q0
H X X Z

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7 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

7.1 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in
the Absolute Maximum Ratings section. Each VCC terminal must have a good bypass capacitor to prevent
power disturbance. For devices with a single supply, TI recommends a 0.1-μF capacitor; if there are multiple
VCC terminals, then TI recommends a 0.01-μF or 0.022-μF capacitor for each power terminal. Multiple bypass
capacitors can be paralleled to reject different frequencies of noise. Frequencies of 0.1 μF and 1 μF are
commonly used in parallel. The bypass capacitor must be installed as close as possible to the power terminal for
best results.
7.2 Layout
7.2.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices, inputs must never be left floating. In many cases,
functions or parts of functions of digital logic devices are unused (for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used). Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
7.2.2 Layout Example

VCC GND
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation

F Bypass capacitor
OE VCC placed close to the
device
1 20
1D 2 19 1Q
2D 3 18 2Q
Unused input Unused output
tied to GND 3D 4 17 3Q left floating
4D 5 16 4Q
5D 6 GND 15 5Q
6D 7 14 6Q
7D 8 13 7Q

8D 9 12 8Q
10 11
Avoid 90° GND CLK
corners for
signal lines

Figure 7-1. Layout example for the SN74ACT574

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8 Device and Documentation Support

8.1 Documentation Support (Analog)
8.1.1 Related Documentation
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8-1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
SN74ACT574 Click here Click here Click here Click here Click here

8.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

8.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (May 2023) to Revision F (February 2024) Page
• Added ESD Ratings table, Application and Implementation section, Device and Documentation Support
section, and Mechanical, Packaging, and Orderable Information section..........................................................1
• Updated RθJA values: DW = 58 to 101.2, NS = 60 to 106.2, PW = 83 to 126.2, all values in °C/W ................ 4

Changes from Revision D (November 2002) to Revision E (May 2023) Page

• Added Package Information table, Pin Functions table, and Thermal Information table....................................1

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10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

SN74ACT574DBR Active Production SSOP (DB) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 AD574
SN74ACT574DBR.A Active Production SSOP (DB) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 AD574
SN74ACT574DW Obsolete Production SOIC (DW) | 20 - - Call TI Call TI -40 to 85 ACT574
SN74ACT574DWR Active Production SOIC (DW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 ACT574
SN74ACT574DWR.A Active Production SOIC (DW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 ACT574
SN74ACT574N Active Production PDIP (N) | 20 20 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 SN74ACT574N
SN74ACT574N.A Active Production PDIP (N) | 20 20 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 SN74ACT574N
SN74ACT574NSR Active Production SOP (NS) | 20 2000 | LARGE T&R Yes NIPDAU | NIPDAU Level-1-260C-UNLIM -40 to 85 ACT574
SN74ACT574NSR.A Active Production SOP (NS) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 ACT574
SN74ACT574PW Obsolete Production TSSOP (PW) | 20 - - Call TI Call TI -40 to 85 AD574
SN74ACT574PWR Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU | NIPDAU Level-1-260C-UNLIM -40 to 85 AD574
SN74ACT574PWR.A Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 AD574

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 23-May-2025

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 23-May-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74ACT574DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74ACT574DWR SOIC DW 20 2000 330.0 24.4 10.9 13.3 2.7 12.0 24.0 Q1
SN74ACT574DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
SN74ACT574NSR SOP NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1
SN74ACT574NSR SOP NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1
SN74ACT574PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74ACT574PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 23-May-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ACT574DBR SSOP DB 20 2000 356.0 356.0 35.0
SN74ACT574DWR SOIC DW 20 2000 356.0 356.0 45.0
SN74ACT574DWR SOIC DW 20 2000 367.0 367.0 45.0
SN74ACT574NSR SOP NS 20 2000 367.0 367.0 45.0
SN74ACT574NSR SOP NS 20 2000 356.0 356.0 45.0
SN74ACT574PWR TSSOP PW 20 2000 353.0 353.0 32.0
SN74ACT574PWR TSSOP PW 20 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

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TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN74ACT574N N PDIP 20 20 506 13.97 11230 4.32
SN74ACT574N.A N PDIP 20 20 506 13.97 11230 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
DB0020A SCALE 2.000
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C
PIN 1 INDEX AREA SEATING
18X 0.65 PLANE
20
1

2X
7.5
5.85
6.9
NOTE 3

10
11 0.38
20X
0.22
5.6 0.1 C A B
B
5.0
NOTE 4

2 MAX
(0.15) TYP 0.25
SEE DETAIL A GAGE PLANE

0.95 0.05 MIN

0 -8 0.55

DETAIL A
A 15

TYPICAL

4214851/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.

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 EXAMPLE BOARD LAYOUT
DB0020A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

20X (1.85) SYMM

1 (R0.05) TYP

20X (0.45) 20

SYMM
18X (0.65)

10 11

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4214851/B 08/2019
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
DB0020A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

20X (1.85) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4214851/B 08/2019
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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 PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1

13.0 2X
12.6 11.43
NOTE 3

10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4

0.33
TYP
0.10

0.25
SEE DETAIL A GAGE PLANE

1.27 0.3
0 -8 0.40 0.1

DETAIL A
TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

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 EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2) SYMM

1
20

20X (0.6)

18X (1.27)

SYMM

(R0.05)
TYP

10 11

(9.3)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2)
SYMM
1
20

20X (0.6)

18X (1.27)

SYMM

10 11

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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 PACKAGE OUTLINE
PW0020A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
6.6 C
TYP PLANE
A 6.2
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1

2X
6.6 5.85
6.4
NOTE 3

10
11
0.30
20X
4.5 0.19 1.2 MAX
B
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE 0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220206/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

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 EXAMPLE BOARD LAYOUT
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220206/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220206/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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