SN54ACT244, SN74ACT244

SCAS517E – JUNE 1995 – REVISED JULY 2023

SNx4ACT244 Octal Buffers and Drivers With 3-State Outputs

1 Features 3 Description
• 4.5-V to 5.5-V VCC operation These SNx4ACT244 octal buffers and drivers are
• Inputs accept voltages to 5.5 V designed specifically to improve the performance and
• Maximum tpd of 9.5 ns at 5 V density of 3-state memory address drivers, clock
• Inputs are TTL compatible drivers, and bus-oriented receivers and transmitters.
• On products compliant to MIL-PRF-38535,
The SNx4ACT244 devices are organized as two 4-
all parameters are tested unless otherwise noted.
bit buffers and drivers with separate output-enable
On all other products, production processing does
(OE) inputs. When OE is low, the device passes non-
not necessarily include testing of all parameters.
inverted data from the A inputs to the Y outputs.
2 Applications When OE is high, the outputs are in the high-
impedance state.
• LED displays
• Servers and telecommunication Device Information
• Switching networks PART NUMBER PACKAGE(1) BODY SIZE (NOM)(2) PACKAGE SIZE(3)
DB (SSOP, 20) 7.2 mm × 5.3 mm 7.2 mm × 7.8 mm
DW (SOIC, 20) 12.8 mm × 7.5 mm 12.8 mm × 10.3 mm
N (PDIP, 20) 24.33 mm × 6.35 mm 24.33 mm × 9.4 mm
SN74ACT244
NS (SO, 20) 12.6 mm × 5.3 mm 12.6 mm × 7.8 mm
PW (TSSOP, 20) 6.5 mm × 4.4 mm 6.5 mm × 6.4 mm
RKS (VQFN, 20) 4.5 mm × 2.5 mm 4.5 mm × 2.5 mm
J (CDIP, 20) 24.2 mm × 6.92 mm 24.2 mm × 6.92 mm
SN54ACT244 W (CFP, 20) 13.09 mm × 6.92 mm 13.09 mm × 6.92 mm
FK (LCCC, 20) 8.89 mm × 8.89 mm 8.89 mm × 8.89 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.
(2) The body size (length × width) is a nominal value and does
not include pins.
(3) The package size (length × width) is a nominal value and
includes pins, where applicable.

Logic Diagram (Positive Logic)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 8.2 Functional Block Diagram........................................... 9
2 Applications..................................................................... 1 8.3 Feature Description.....................................................9
3 Description.......................................................................1 8.4 Device Functional Modes............................................9
4 Revision History.............................................................. 2 9 Application and Implementation.................................. 10
5 Pin Configuration and Functions...................................3 9.1 Application Information............................................. 10
6 Specifications.................................................................. 4 9.2 Typical Application.................................................... 10
6.1 Absolute Maximum Ratings........................................ 4 9.3 Power Supply Recommendations............................. 11
6.2 ESD Ratings............................................................... 4 9.4 Layout....................................................................... 11
6.3 Recommended Operating Conditions.........................4 10 Device and Documentation Support..........................12
6.4 Thermal Information....................................................5 10.1 Documentation Support.......................................... 12
6.5 Electrical Characteristics.............................................5 10.2 Receiving Notification of Documentation Updates..12
6.6 Switching Characteristics............................................6 10.3 Support Resources................................................. 12
6.7 Operating Characteristics........................................... 7 10.4 Trademarks............................................................. 12
6.8 Typical Characteristics................................................ 7 10.5 Electrostatic Discharge Caution..............................12
7 Parameter Measurement Information............................ 8 10.6 Glossary..................................................................12
8 Detailed Description........................................................9 11 Mechanical, Packaging, and Orderable
8.1 Overview..................................................................... 9 Information.................................................................... 12

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (January 2016) to Revision E (July 2023) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Updated the Device Information table to include body and package lead size.................................................. 1
• Add RKS Package information........................................................................................................................... 1

Changes from Revision C (October 2002) to Revision D (January 2016) Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1

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5 Pin Configuration and Functions

1OE 1 20 VCC 1OE 1 20 VCC

1A1 2 19 2OE 1A1 2 19 2OE
2Y4 3 18 1Y1 2Y4 3 18 1Y1
1A2 4 17 2A4 1A2 4 17 2A4
2Y3 5 16 1Y2
2Y3 5 16 1Y2
1A3 6 15 2A3
1A3 6 15 2A3
2Y2 7 14 1Y3
2Y2 7 14 1Y3
1A4 8 13 2A2
1A4 8 13 2A2
2Y1 9 12 1Y4
2Y1 9 12 1Y4 GND 10 11 2A1
GND 10 11 2A1
Figure 5-2. SN74ACT244: DB, DW, N, NS, or PW
Figure 5-1. SN54ACT244: J or W Packages, 20-Pin
Packages, 20-Pin SSOP, SOIC, PDIP, SO, or TSSOP
CDIP or CFP (Top View)
(Top View)
1OE

2OE
VCC

1OE VCC
2Y4
1A1

1 20
1A1 2 19 2OE
2Y4 3 18 1Y1
3 2 1 20 19
1A2 4 18 1Y1 1A2 4 17 2A4
2Y3 5 16 1Y2
2Y3 5 17 2A4 6 PAD
1A3 15 2A3
1A3 6 16 1Y2 2Y2 7 14 1Y3
2Y2 7 15 2A3 1A4 8 13 2A2
8 14 2Y1 9 12 1Y4
1A4 1Y3
9 10 11 12 13 10 11
GND 2A1
GND
2Y1

2A1
1Y4
2A2

Figure 5-4. SN74ACT244: RKS Packages, 20-Pin

VQFN (Top View)
Figure 5-3. SN54ACT244: FK Package 20-Pin LCCC
(Top View)

Table 5-1. Pin Functions

PIN
TYPE(1) DESCRIPTION
NO. NAME
1 1 OE I 1 Active low Output enable
2 1A1 I 1A1 input
3 2Y4 O 2Y4 output
4 1A2 I 1A2 input
5 2Y3 O 2Y3 Output
6 1A3 I 1A3 input
7 2Y2 O 2Y2 Output
8 1A4 I 1A4 input
9 2Y1 O 2Y1 Output
10 GND — Ground
11 2A1 I 2A1 input
12 1Y4 O 1Y4 output
13 2A2 I 2A2 input
14 1Y3 O 1Y3 Output
15 2A3 I 2A3 input
16 1Y2 O 1Y2 Output
17 2A4 I 2A4 input
18 1Y1 O 1Y1 Output
19 2 OE I 2 Active low Output enable
20 VCC — Power

(1) I = input, O = output

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
VI Input voltage(2) –0.5 VCC + 0.5 V
VO Output voltage(2) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 or VI > VCC ±20 mA
IOK Output clamp current VO < 0 or VO > VCC ±20 mA
IO Continuous output current VO = 0 to VCC ±50 mA
Continuous current through VCC or GND ±200 mA
TJ Absolute Maximum Junction Temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

VALUE UNIT
SN74ACT244 in DW Package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±3000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±2000
C101(2)
SN54ACT244 in J, W, DB, N, NS, PW, FK Packages
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
IOH High-level output current –24 mA
IOL Low-level output current 24 mA
Δt/Δv Input transition rise or fall rate 8 ns/V
SN54ACT244 –55 125
TA Operating free-air temperature °C
SN74ACT244 –40 85

(1) All unused inputs of the device must be held at VCC or GND for proper device operation. See the TI application report, Implications of
Slow or Floating CMOS Inputs.

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6.4 Thermal Information

SN74ACT244
DB DW N NS PW RKS
THERMAL METRIC(1) UNIT
(SSOP) (SOIC) (PDIP) (SO) (TSSOP) (VQFN)
20 PINS 20 PINS 20 PINS 20 PINS 20 PINS 20 PINS
Junction-to-ambient thermal
RθJA 94.1 81.4 48.1 76.4 103 67.7 °C/W
resistance
Junction-to-case (top) thermal
RθJC(top) 55.6 46.8 34.1 42.6 37.7 72.4 °C/W
resistance
Junction-to-board thermal
RθJB 49.3 49.3 29 43.9 54 40.4 °C/W
resistance
Junction-to-top characterization
ψJT 20.8 20 19.5 18.8 2.8 10.3 °C/W
parameter
Junction-to-board characterization
ψJB 48.9 48.8 28.9 43.5 53.5 40.4 °C/W
parameter
Junction-to-case (bottom) thermal
RθJC(bot) N/A N/A N/A N/A N/A 24.1 °C/W
resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
TA = 25°C 4.4 4.49
SN54ACT244 4.5 V 4.4
SN74ACT244 4.4
IOH = –50 µA
TA = 25°C 5.4 5.49
SN54ACT244 5.5 V 5.4
SN74ACT244 5.4
TA = 25°C 3.86
VOH V
SN54ACT244 4.5 V 3.7
SN74ACT244 3.76
IOH = –24 mA
TA = 25°C 4.86
SN54ACT244 5.5 V 4.7
SN74ACT244 4.76
IOH = –50 mA(1) SN54ACT244 5.5 V 3.85
IOH = –75 mA(1) SN74ACT244 5.5 V 3.85

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6.5 Electrical Characteristics (continued)

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
TA = 25°C 0.001 0.1
SN54ACT244 4.5 V 0.1
SN74ACT244 0.1
IOL = 50 µA
TA = 25°C 0.001 0.1
SN54ACT244 5.5 V 0.1
SN74ACT244 0.1
TA = 25°C 0.36
VOL V
SN54ACT244 4.5 V 0.5
SN74ACT244 0.44
IOL = 24 mA
TA = 25°C 0.36
SN54ACT244 5.5 V 0.5
SN74ACT244 0.44
IOL = 50 mA(1) SN54ACT244 5.5 V 1.65
IOL = 75 mA(1) SN74ACT244 5.5 V 1.65
TA = 25°C ±0.25
IOZ VO = VCC or GND SN54ACT244 5.5 V ±5 µA
SN74ACT244 ±2.5
TA = 25°C ±0.1
II VI = VCC or GND SN54ACT244 5.5 V ±1 µA
SN74ACT244 ±1
TA = 25°C 4
ICC VI = VCC or GND, IO = 0 SN54ACT244 5.5 V 80 µA
SN74ACT244 40
TA = 25°C 0.6
One input at 3.4 V,
ΔICC (2) SN54ACT244 5.5 V 1.6 mA
Other inputs at GND or VCC
SN74ACT244 1.5
CI VI = VCC or GND TA = 25°C 5V 2.5 pF
Co VI = VCC or GND TA = 25°C 5V 8 pF

(1) Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
(2) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.

6.6 Switching Characteristics

over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 7-1)
FROM TO
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
TA = 25°C 2 6.5 9
tPLH SN54ACT244 1 10
SN74ACT244 1.5 10
A Y ns
TA = 25°C 2 7 9
tPHL SN54ACT244 1 10
SN74ACT244 1.5 10

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6.6 Switching Characteristics (continued)

over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 7-1)
FROM TO
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
TA = 25°C 1.5 7 8.5
tPZH SN54ACT244 1 9.5
SN74ACT244 1 9.5
OE Y ns
TA = 25°C 2 7 9.5
tPZL SN54ACT244 1 11
SN74ACT244 1.5 10.5
TA = 25°C 2 8 9.5
tPHZ SN54ACT244 1 11
SN74ACT244 1.5 10.5
OE Y ns
TA = 25°C 2.5 7.5 10
tPLZ SN54ACT244 1 11.5
SN74ACT244 2 10.5

6.7 Operating Characteristics

VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per buffer/driver CL = 50 pF, f = 1 MHz 45 pF

6.8 Typical Characteristics

5.4
5.3 VCC 5.5V
5.2
5.1
5
4.9
4.8
VOH min (V)

4.7
4.6
4.5
4.4
4.3
4.2
4.1
4
3.9
3.8
-75 -65 -55 -45 -35 -25 -15 -5
IOH mA D001
Figure 6-1. VOH Vs IOH

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7 Parameter Measurement Information

2 × VCC
500 Ω S1 Open TEST S1
From Output
Under Test tPLH/tPHL Open
tPLZ/tPZL 2 × VCC
CL = 50 pF
(see Note A) 500 Ω tPHZ/tPZH Open

LOAD CIRCUIT Output 3V

Control
1.5 V 1.5 V
(low-level
0V
enabling)
tPZL tPLZ
3V
Output ≈VCC
Input 1.5 V 1.5 V Waveform 1 50% VCC
0V S1 at 2 × VCC VOL + 0.3 V
VOL
(see Note B)
tPLH tPHL tPZH tPHZ
VOH Output
VOH
50% VCC 50% VCC Waveform 2 VOH − 0.3 V
Output 50% VCC
S1 at Open
VOL ≈0 V
(see Note B)

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.

Figure 7-1. Load Circuit and Voltage Waveforms

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8 Detailed Description
8.1 Overview
The SNx4ACT244 devices are buffer drivers with separate output enable inputs. The active low output enable
sets the output to high impedance when a logic high is applied. For the high-impedance state during power up or
power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined
by the current-sinking capability of the driver.
8.2 Functional Block Diagram

Figure 8-1. Logic Diagram (Positive Logic)

8.3 Feature Description

The SNx4ACT244 devices are recommended for 4.5 V to 5.5-V VCC range under normal operating conditions.
The inputs are TTL compatible accepting 2-V minimum high at 5-V VCC.
8.4 Device Functional Modes
Table 8-1 lists the functions of the device.
Table 8-1. Function Table (Each Buffer)
INPUTS OUTPUT
OE A Y

L H H
L L L
H X Hi-Z

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

The SNx4ACT244 is high-drive buffer drivers providing 24-mA current drive per channel at nominal operating
specifications. It can be used as LED driver with appropriate current-limiting resistors to ground or VCC withing
the device's and LEDs operating characteristics.
9.2 Typical Application
Vcc
Control signal 1k

LED

SNx4ACT244

Vcc Vcc
Control signal 1k

LED
SNx4ACT244
Copyright © 2016, Texas Instruments Incorporated

Figure 9-1. Typical LED driving application

9.2.1 Design Requirements

The pullup and pull-down current limiting resistors are chosen to operate within the LED and the SNx4ACT244
device operating specifications. A 1-kΩ resistor, limits the current to less than 5 mA at 5-V VCC operation.
9.2.2 Detailed Design Procedure
1. Recommended input conditions:
• For the specified high and low levels See (VIH and VIL) in the Section 6.3.
• Inputs are not overvoltage tolerant and must be limited to VCC.
2. Recommended output conditions:
• Limit the output voltage to VCC.
• Choose the current-limiting resistor for the LED to limit the output current to IO as per the Section 6.3.

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9.2.3 Application Curve

1.7
1.6 VCC 5.5V
1.5
1.4
1.3
1.2
1.1

VOL max (V)

1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75
IOL (mA) D001

Figure 9-2. VOL vs IOL

9.3 Power Supply Recommendations

The power supply may be any voltage between the MIN and MAX supply voltage rating located in the Section
6.3.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-µF capacitor is
recommended for devices with a single supply. If there are multiple VCC terminals, then 0.01-µF or 0.022-µF
capacitors are recommended for each power terminal. It is permissible to parallel multiple bypass capacitors to
reject different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies
of noise. The bypass capacitor should be installed as close to the power terminal as possible for the best results.
9.4 Layout
9.4.1 Layout Guidelines
Inputs should not float when using multiple bit logic devices. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples include situations when only two inputs of a triple-input AND
gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected
because the undefined voltages at the outside connections result in undefined operational states.
Specified in the Figure 9-3 are rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally, they will be tied to
GND or VCC, whichever makes more sense or is more convenient.
9.4.2 Layout Example

VCC Input
Unused Input Output Unused Input Output

Input

Figure 9-3. Layout Example

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10 Device and Documentation Support

10.1 Documentation Support
10.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Implications of Slow or Floating CMOS Inputs
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-8776001M2A ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 8776001M2A
SNJ54ACT
244FK
5962-8776001MRA ACTIVE CDIP J 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8776001MR Samples
& Green A
SNJ54ACT244J
5962-8776001MSA ACTIVE CFP W 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8776001MS Samples
& Green A
SNJ54ACT244W
5962-8776001SRA ACTIVE CDIP J 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8776001SR Samples
& Green A
SNV54ACT244J
5962-8776001SSA ACTIVE CFP W 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8776001SS Samples
& Green A
SNV54ACT244W
SN74ACT244DBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AD244 Samples

SN74ACT244DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT244 Samples

SN74ACT244DWRE4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT244 Samples

SN74ACT244DWRG4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT244 Samples

SN74ACT244N ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74ACT244N Samples

SN74ACT244NE4 ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74ACT244N Samples

SN74ACT244NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT244 Samples

SN74ACT244NSRG4 ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT244 Samples

SN74ACT244PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 AD244 Samples

SN74ACT244PWRE4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AD244 Samples

SN74ACT244PWRG4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AD244 Samples

Addendum-Page 1
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Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74ACT244RKSR ACTIVE VQFN RKS 20 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -45 to 125 ACT244 Samples

SNJ54ACT244FK ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 8776001M2A
SNJ54ACT
244FK
SNJ54ACT244J ACTIVE CDIP J 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8776001MR Samples
& Green A
SNJ54ACT244J
SNJ54ACT244W ACTIVE CFP W 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8776001MS Samples
& Green A
SNJ54ACT244W

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Aug-2023

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54ACT244, SN54ACT244-SP, SN74ACT244 :

• Catalog : SN74ACT244, SN54ACT244

• Automotive : SN74ACT244-Q1, SN74ACT244-Q1
• Enhanced Product : SN74ACT244-EP, SN74ACT244-EP
• Military : SN54ACT244
• Space : SN54ACT244-SP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 7-Aug-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74ACT244DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74ACT244DWR SOIC DW 20 2000 330.0 24.4 10.9 13.3 2.7 12.0 24.0 Q1
SN74ACT244NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1
SN74ACT244PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74ACT244PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74ACT244PWRG4 TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74ACT244RKSR VQFN RKS 20 3000 180.0 12.4 2.8 4.8 1.2 4.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 7-Aug-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ACT244DBR SSOP DB 20 2000 356.0 356.0 35.0
SN74ACT244DWR SOIC DW 20 2000 367.0 367.0 45.0
SN74ACT244NSR SO NS 20 2000 367.0 367.0 45.0
SN74ACT244PWR TSSOP PW 20 2000 356.0 356.0 35.0
SN74ACT244PWR TSSOP PW 20 2000 364.0 364.0 27.0
SN74ACT244PWRG4 TSSOP PW 20 2000 356.0 356.0 35.0
SN74ACT244RKSR VQFN RKS 20 3000 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 7-Aug-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-8776001M2A FK LCCC 20 1 506.98 12.06 2030 NA
5962-8776001MSA W CFP 20 1 506.98 26.16 6220 NA
5962-8776001SSA W CFP 20 1 506.98 26.16 6220 NA
SN74ACT244N N PDIP 20 20 506 13.97 11230 4.32
SN74ACT244NE4 N PDIP 20 20 506 13.97 11230 4.32
SNJ54ACT244FK FK LCCC 20 1 506.98 12.06 2030 NA
SNJ54ACT244W W CFP 20 1 506.98 26.16 6220 NA

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

www.ti.com
 PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1

13.0 2X
12.6 11.43
NOTE 3

10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4

0.33
TYP
0.10

0.25
SEE DETAIL A GAGE PLANE

1.27 0.3
0 -8 0.40 0.1

DETAIL A
TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2) SYMM

1
20

20X (0.6)

18X (1.27)

SYMM

(R0.05)
TYP

10 11

(9.3)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2)
SYMM
1
20

20X (0.6)

18X (1.27)

SYMM

10 11

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
PW0020A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
6.6 C
TYP PLANE
A 6.2
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1

2X
6.6 5.85
6.4
NOTE 3

10
11
0.30
20X
4.5 0.19 1.2 MAX
B
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE 0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220206/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220206/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220206/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DB0020A SCALE 2.000
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C
PIN 1 INDEX AREA SEATING
18X 0.65 PLANE
20
1

2X
7.5
5.85
6.9
NOTE 3

10
11 0.38
20X
0.22
5.6 0.1 C A B
B
5.0
NOTE 4

2 MAX
(0.15) TYP 0.25
SEE DETAIL A GAGE PLANE

0.95 0.05 MIN

0 -8 0.55

DETAIL A
A 15

TYPICAL

4214851/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.

www.ti.com
 EXAMPLE BOARD LAYOUT
DB0020A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

20X (1.85) SYMM

1 (R0.05) TYP

20X (0.45) 20

SYMM
18X (0.65)

10 11

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4214851/B 08/2019
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DB0020A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

20X (1.85) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4214851/B 08/2019
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 GENERIC PACKAGE VIEW
RKS 20 VQFN - 1 mm max height
2.5 x 4.5, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4226872/A

www.ti.com
 PACKAGE OUTLINE
RKS0020A SCALE 3.300
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

2.6 B
A
2.4

PIN 1 INDEX AREA

4.6
4.4

0.1 C

1.0 C
0.8
SEATING PLANE
0.05
0.00 0.08 C
1 0.1

2X 0.5 (0.2) TYP

10 11
14X 0.5
9 EXPOSED
12 THERMAL PAD

2X
3.5 3 0.1

2
19
0.30
1 20 20X
PIN 1 ID 0.18
(OPTIONAL) 0.5 0.1 C A B
20X
0.3 0.05

4222490/B 02/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RKS0020A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(1)
SYMM

1 20
20X (0.6)

2
19

20X (0.24)

(1.25)

SYMM
(3)
(4.3)

16X (0.5)

(R0.05) TYP

9 12

( 0.2) VIA
TYP
10 11
(2.3)

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL OPENING

SOLDER MASK METAL UNDER

OPENING SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4222490/B 02/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.

www.ti.com
 EXAMPLE STENCIL DESIGN
RKS0020A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

2X (0.95)

1 20

20X (0.6)
2
19

20X (0.24)

2X (1.31)

16X (0.5)

SYMM

(4.3)
(0.76)

METAL
TYP

9 12

(R0.05) TYP

10 11

SYMM

(2.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
83% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X

4222490/B 02/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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