SN54AC574, SN74AC574

SCAS541G – OCTOBER 1995 – REVISED MARCH 2024

SNx4AC574 Octal D-Type Edge-Triggered Flip-Flops with 3-State Outputs

1 Features 2 Description
• Operation of 2V to 6V VCC These 8-bit flip-flops feature 3-state outputs designed
• Inputs accept voltages to 6V specifically for driving highly capacitive or relatively
• Max tpd of 8.5ns at 5V low-impedance loads. The devices are particularly
• 3-state outputs drive bus lines directly suitable for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
Device Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
DB (SSOP, 20) 7.2mm × 7.8mm 7.2mm × 5.30mm
DW (SOIC, 20) 12.8mm × 10.3mm 12.80mm × 7.50mm
SNx4AC574
N (PDIP, 20) 24.33mm × 9.4mm 24.33mm × 6.35mm
PW (TSSOP, 20) 6.5mm × 6.4mm 6.50mm × 4.40mm

(1) For more information, see Section 10.

(2) The package size (length × width) is a nominal value and
includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does
not include pins.

Logic Diagram (Positive Logic)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 6.2 Functional Block Diagram........................................... 8
2 Description.......................................................................1 6.3 Device Functional Modes............................................8
3 Pin Configuration and Functions...................................3 7 Application and Implementation.................................... 9
4 Specifications.................................................................. 4 7.1 Power Supply Recommendations...............................9
4.1 Absolute Maximum Ratings........................................ 4 7.2 Layout......................................................................... 9
4.2 Recommended Operating Conditions.........................4 8 Device and Documentation Support............................10
4.3 Thermal Information....................................................5 8.1 Documentation Support (Analog)..............................10
4.4 Electrical Characteristics.............................................5 8.2 Receiving Notification of Documentation Updates....10
4.5 Timing Requirements, VCC = 3.3 V ± 0.3 V.................5 8.3 Support Resources................................................... 10
4.6 Timing Requirements, VCC = 5 V ± 0.5 V....................6 8.4 Trademarks............................................................... 10
4.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V...........6 8.5 Electrostatic Discharge Caution................................10
4.8 Switching Characteristics, VCC = 5 V ± 0.5 V..............6 8.6 Glossary....................................................................10
4.9 Operating Characteristics........................................... 6 9 Revision History............................................................ 10
5 Parameter Measurement Information............................ 7 10 Mechanical, Packaging, and Orderable
6 Detailed Description........................................................8 Information.................................................................... 10
6.1 Overview..................................................................... 8

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3 Pin Configuration and Functions

Figure 3-1. SN54AC574 J or W Package; Figure 3-2. SN54AC574 FK Package (Top View)
SN74AC574 DB, DW, N, NS, or PW Package (Top
View)

Table 3-1. Pin Functions

PIN
I/O DESCRIPTION
NAME NO.
OE 1 Input Output enable for all channels, active low
D1 2 Input Input for channel 1
D2 3 Input Input for channel 2
D3 4 Input Input for channel 3
D4 5 Input Input for channel 4
D5 6 Input Input for channel 5
D6 7 Input Input for channel 6
D7 8 Input Input for channel 7
D8 9 Input Input for channel 8
GND 10 — Ground
CLK 11 Input Clock input for all channels, rising edge triggered
Q8 12 Output Output for channel 8
Q7 13 Output Output for channel 7
Q6 14 Output Output for channel 6
Q5 15 Output Output for channel 5
Q4 16 Output Output for channel 4
Q3 17 Output Output for channel 3
Q2 18 Output Output for channel 2
Q1 19 Output Output for channel 1
VCC 20 — Postive supply
The thermal pad can be connect to GND or left floating. Do not connect to any other signal
Thermal Pad —
or supply.

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4 Specifications
4.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage range −0.5 7 V
VI (2) Input voltage range −0.5 VCC + 0.5 V
VO (2) Output voltage range −0.5 VCC + 0.5 V
IIK Input clamp current (VI < 0 or VI > VCC) ±20 mA
IOK Output clamp current (VO < 0 or VO > VCC) ±20 mA
IO Continuous output current (VO = 0 to VCC) ±50 mA
Continuous current through VCC or GND ±200 mA
Tstg Storage temperature range −65 150 °C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

4.2 Recommended Operating Conditions

over recommended operating free-air temperature range (unless otherwise noted)(1)
SN54AC574 SN74AC574
UNIT
MIN MAX MIN MAX
VCC Supply voltage 2 6 2 6 V
VCC = 3 V 2.1 2.1
VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V
VCC = 5.5 V 3.85 3.85
VCC = 3 V 0.9 0.9
VIL Low-level input voltage VCC = 4.5V 1.35 1.35 V
VCC = 5.5 V 1.65 1.65
VI Input voltage 0 VCC 0 VCC V
VO Output voltage 0 VCC 0 VCC V
VCC = 3 V −12 −12
IOH High-level output current VCC = 4.5 V −24 −24 mA
VCC = 5.5 V −24 −24
VCC = 3 V 12 12
IOL Low-level output current VCC = 4.5 V 24 24 mA
VCC = 5.5 V 24 24
Δt/Δv Input transition rise or fall rate 8 8 ns/V
TA Operating free-air temperature −55 125 −40 85 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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4.3 Thermal Information

SNx4AC574
DB DW N NS PW
THERMAL METRIC(1) UNIT
(SSOP) (SOIC) (PDIP) (SOP) (TSSOP)
20 PINS
Junction-to-ambient thermal
RθJA 70 101.2 69 60 126.2 °C/W
resistance

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

4.4 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C SN54AC574 SN74AC574
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
3V 2.9 2.9 2.9
IOH = −50μA 4.5 V 4.4 4.4 4.4
5.5 V 5.4 5.4 5.4
VOH V
IOH = −12 mA 3V 2.56 2.4 2.46
4.5 V 3.94 3.7 3.76
IOH = −24 mA
5.5 V 4.94 4.7 4.76
3V 0.1 0.1 0.1
IOL = 50μA 4.5 V 0.1 0.1 0.1
5.5 V 0.1 0.1 0.1
VOL V
IOL = 12 mA 3V 0.36 0.5 0.44
4.5 V 0.36 0.5 0.44
IOL = 24 mA
5.5 V 0.36 0.5 0.44
II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 μA
IOZ VO = VCC or GND 5.5 V ±0.5 ±5 ±2.5 μA
ICC VI = VCC or GND, IO = 0 5.5 V 4 80 40 μA
Ci VI = VCC or GND 5V 4.5 pF

4.5 Timing Requirements, VCC = 3.3 V ± 0.3 V

over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Load Circuit and
Voltage Waveforms)
TA = 25°C SN54AC574 SN74AC574
UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency 75 55 60 MHz
tw Pulse duration, CLK high or low 6 7.5 7 ns
tsu Setup time, data before CLK↑ 2.5 6.5 3 ns
th Hold time, data after CLK↑ 1.5 2.5 1.5 ns

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4.6 Timing Requirements, VCC = 5 V ± 0.5 V

over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Load Circuit and
Voltage Waveforms)
TA = 25°C SN54AC574 SN74AC574
UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency 95 85 85 MHz
tw Pulse duration, CLK high or low 4 5 5 ns
tsu Setup time, data before CLK↑ 1.5 3.5 2 ns
th Hold time, data after CLK↑ 1.5 2.5 1.5 ns

4.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V

over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Load Circuit and
Voltage Waveforms)
TA = 25°C SN54AC574 SN74AC574
PARAMETER TO (INPUT) TO (OUTPUT) UNIT
MIN TYP MAX MIN MAX MIN MAX
fmax 75 112 55 60 MHz
tPLH 3.5 8.5 13.5 1 16.5 3.5 15
CLK Q ns
tPHL 3.5 7.5 12 1 15 3.5 13.5
tPZH 2.5 7 11 1 13 2.5 12
OE Q ns
tPZL 3 6.5 10.5 1 12.5 3 11.5
tPHZ 3.5 7.5 12 1 14 2.5 13
OE Q ns
tPLZ 2 5.5 9 1 10.5 1.5 10

4.8 Switching Characteristics, VCC = 5 V ± 0.5 V

over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Load Circuit and
Voltage Waveforms)
TA = 25°C SN54AC574 SN74AC574
PARAMETER TO (INPUT) TO (OUTPUT) UNIT
MIN TYP MAX MIN MAX MIN MAX
fmax 95 153 85 85 MHz
tPLH 2 6 9.5 1.5 11.5 2 11
CLK Q ns
tPHL 2 5.5 8.5 1.5 10.5 2 9.5
tPZH 2 5 8.5 1.5 9.5 2 9
OE Q ns
tPZL 2 5 8 1.5 9.5 1.5 9
tPHZ 2 6 9.5 1.5 11.5 1.5 10.5
OE Q ns
tPLZ 1 4.5 7.5 1.5 9 1 8.5

4.9 Operating Characteristics

VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance CL = 50 pF, f = 1 MHz 40 pF

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5 Parameter Measurement Information

A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.

Figure 5-1. Load Circuit and Voltage Waveforms

TEST S1
tPLH/tPHL Open
tPLZ/tPZL 2 × VCC
tPHZ/tPZH Open

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6 Detailed Description
6.1 Overview
The eight flip-flops of the ′AC574 devices are D-type edge-triggered flip-flops. On the positive transition of the
clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
in a bus-organized system without need for interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
For the specified high-impedance state during power up or power down, OE must be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
6.2 Functional Block Diagram

Figure 6-1. Logic Diagram (Positive Logic)

6.3 Device Functional Modes

Table 6-1. Function Table (Each Flip-flop)
INPUTS
OUTPUT Q
OE CLK D
L ↑ H H
L ↑ L L
L H or L X Q0
H X X Z

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7 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

7.1 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a
single supply, a 0.1 μF capacitor is recommended. If there are multiple VCC terminals then 0.01 μF or 0.022 μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1 μF and 1.0 μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for the best results.
7.2 Layout
7.2.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in layout example are rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the
part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part
when asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.
7.2.1.1 Layout Example

VCC GND
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation

F Bypass capacitor
OE VCC placed close to the
device
1 20
1D 2 19 1Q
2D 3 18 2Q
Unused input Unused output
tied to GND 3D 4 17 3Q left floating
4D 5 16 4Q
5D 6 GND 15 5Q
6D 7 14 6Q
7D 8 13 7Q

8D 9 12 8Q
10 11
Avoid 90° GND CLK
corners for
signal lines

Figure 7-1. Layout example for the SNx4AC574

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8 Device and Documentation Support

8.1 Documentation Support (Analog)
8.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, CMOS Power Consumption and Cpd Calculation application report
• Texas Instruments, Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices
application report
8.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

8.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (August 2023) to Revision G (March 2024) Page
• Updated RθJA values: DW = 58 to 101.2, PW = 83 to 126.2, all values in °C/W ............................................. 5
• Added Application and Implementation section..................................................................................................9

Changes from Revision E (October 2003) to Revision F ( August 2023) Page

• Added Device Information table, Pin Functions table, Thermal Information table, Device Functional Modes,
Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section 1

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

5962-9677301Q2A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-
9677301Q2A
SNJ54AC
574FK
5962-9677301QRA Active Production CDIP (J) | 20 20 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-9677301QR
A
SNJ54AC574J
5962-9677301QSA Active Production CFP (W) | 20 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-9677301QS
A
SNJ54AC574W
SN74AC574DBR Active Production SSOP (DB) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 AC574
SN74AC574DBR.A Active Production SSOP (DB) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 AC574
SN74AC574DWR Active Production SOIC (DW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 AC574
SN74AC574DWR.A Active Production SOIC (DW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 AC574
SN74AC574N Active Production PDIP (N) | 20 20 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 SN74AC574N
SN74AC574N.A Active Production PDIP (N) | 20 20 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 SN74AC574N
SN74AC574PW Obsolete Production TSSOP (PW) | 20 - - Call TI Call TI -40 to 85 AC574
SN74AC574PWR Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 AC574
SN74AC574PWR.A Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 AC574
SN74AC574PWRG4 Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 AC574
SNJ54AC574FK Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-
9677301Q2A
SNJ54AC
574FK
SNJ54AC574FK.A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-
9677301Q2A
SNJ54AC
574FK
SNJ54AC574J Active Production CDIP (J) | 20 20 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-9677301QR
A
SNJ54AC574J

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Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

SNJ54AC574J.A Active Production CDIP (J) | 20 20 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-9677301QR
A
SNJ54AC574J
SNJ54AC574W Active Production CFP (W) | 20 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-9677301QS
A
SNJ54AC574W
SNJ54AC574W.A Active Production CFP (W) | 20 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-9677301QS
A
SNJ54AC574W

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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OTHER QUALIFIED VERSIONS OF SN54AC574, SN74AC574 :

• Catalog : SN74AC574
• Military : SN54AC574

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 3
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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AC574DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74AC574DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
SN74AC574DWR SOIC DW 20 2000 330.0 24.4 10.9 13.3 2.7 12.0 24.0 Q1
SN74AC574PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1

Pack Materials-Page 1
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TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AC574DBR SSOP DB 20 2000 353.0 353.0 32.0
SN74AC574DWR SOIC DW 20 2000 356.0 356.0 45.0
SN74AC574DWR SOIC DW 20 2000 356.0 356.0 45.0
SN74AC574PWR TSSOP PW 20 2000 353.0 353.0 32.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

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TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-9677301Q2A FK LCCC 20 55 506.98 12.06 2030 NA
5962-9677301QSA W CFP 20 25 506.98 26.16 6220 NA
SN74AC574N N PDIP 20 20 506 13.97 11230 4.32
SN74AC574N.A N PDIP 20 20 506 13.97 11230 4.32
SNJ54AC574FK FK LCCC 20 55 506.98 12.06 2030 NA
SNJ54AC574FK.A FK LCCC 20 55 506.98 12.06 2030 NA
SNJ54AC574W W CFP 20 25 506.98 26.16 6220 NA
SNJ54AC574W.A W CFP 20 25 506.98 26.16 6220 NA

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

www.ti.com
 PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1

13.0 2X
12.6 11.43
NOTE 3

10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4

0.33
TYP
0.10

0.25
SEE DETAIL A GAGE PLANE

1.27 0.3
0 -8 0.40 0.1

DETAIL A
TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2) SYMM

1
20

20X (0.6)

18X (1.27)

SYMM

(R0.05)
TYP

10 11

(9.3)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2)
SYMM
1
20

20X (0.6)

18X (1.27)

SYMM

10 11

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
PW0020A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
6.6 C
TYP PLANE
A 6.2
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1

2X
6.6 5.85
6.4
NOTE 3

10
11
0.30
20X
4.5 0.19 1.2 MAX
B
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE 0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220206/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220206/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220206/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DB0020A SCALE 2.000
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C
PIN 1 INDEX AREA SEATING
18X 0.65 PLANE
20
1

2X
7.5
5.85
6.9
NOTE 3

10
11 0.38
20X
0.22
5.6 0.1 C A B
B
5.0
NOTE 4

2 MAX
(0.15) TYP 0.25
SEE DETAIL A GAGE PLANE

0.95 0.05 MIN

0 -8 0.55

DETAIL A
A 15

TYPICAL

4214851/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.

www.ti.com
 EXAMPLE BOARD LAYOUT
DB0020A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

20X (1.85) SYMM

1 (R0.05) TYP

20X (0.45) 20

SYMM
18X (0.65)

10 11

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4214851/B 08/2019
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DB0020A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

20X (1.85) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4214851/B 08/2019
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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