SN54HCT125, SN74HCT125

SCLS069G – NOVEMBER 1988 – REVISED OCTOBER 2022

SNx4HCT125 Quadruple Bus Buffer Gates With 3-State Outputs

1 Features 2 Description
• Operating voltage range of 4.5 V to 5.5 V The SNx4HCT125 contains four independent buffers
• High-current can drive up to 15 LSTTL loads with TTL-compatible inputs and 3-state outputs. Each
• Low power consumption, 80-µA max ICC gate performs the Boolean function Y = A in positive
• Typical tpd = 12 ns logic.
• ±6-mA output drive at 5 V
Device Information
• Low input current of 1 µA max (1)
PART NUMBER PACKAGE BODY SIZE (NOM)
• Inputs are TTL-voltage compatible
• High-current 3-state outputs drive bus lines or SN74HCT125D SOIC (14) 8.65 mm × 3.90 mm
buffer memory address registers SN74HCT125N PDIP (14) 19.31 mm × 6.35 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Functional Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7.2 Functional Block Diagram........................................... 8
2 Description.......................................................................1 7.3 Device Functional Modes............................................8
3 Revision History.............................................................. 2 8 Power Supply Recommendations..................................9
4 Pin Configuration and Functions...................................3 9 Layout...............................................................................9
5 Specifications.................................................................. 4 9.1 Layout Guidelines....................................................... 9
5.1 Absolute Maximum Ratings........................................ 4 10 Device and Documentation Support..........................10
(1)
5.2 Recommended Operating Conditions ..................... 4 10.1 Documentation Support.......................................... 10
5.3 Thermal Information....................................................4 10.2 Receiving Notification of Documentation Updates..10
5.4 Electrical Characteristics.............................................5 10.3 Support Resources................................................. 10
5.5 Switching Characteristics............................................5 10.4 Trademarks............................................................. 10
5.6 Operating Characteristics........................................... 6 10.5 Electrostatic Discharge Caution..............................10
6 Parameter Measurement Information............................ 7 10.6 Glossary..................................................................10
7 Detailed Description........................................................8 11 Mechanical, Packaging, and Orderable
7.1 Overview..................................................................... 8 Information.................................................................... 10

3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (February 2022) to Revision G (October 2022) Page
• Increased RθJA for packages: D (86 to 138.7); N (80 to 75.3)...........................................................................4

Changes from Revision E (August 2003) to Revision F (February 2022) Page

• Updated the numbering, formatting, tables, figures, and cross-references throughout the doucment to reflect
modern data sheet standards............................................................................................................................. 1

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4 Pin Configuration and Functions

1OE 1 14 VCC
2 13 4OE
1A
1Y 3 12 4A
4 11 4Y
2OE
2A 5 10 3OE
2Y 6 9 3A
GND 7 8 3Y

D, N, J or W Package
14-Pin SOIC or PDIP
Top View

FK Package
20-Pin LCCC
Top View

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage range -0.5 7 V
(2)
IIK Input clamp current (VI < 0 or VI > VCC) ±20 mA
(2)
IOK Output clamp current (VO < 0 or VO > VCC) ±20 mA
IO Continuous output current (VO = 0 to VCC) ±35 mA
VCC or GND Continuous current through ±70 mA
TJ Junction temperature 150 °C
Tstg Storage temperature -65 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

(1)
5.2 Recommended Operating Conditions
SN54HCT125(2) SN74HCT125
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V
VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 0.8 V
VI Input voltage 0 VCC 0 VCC V
VO Output voltage 0 VCC 0 VCC V
tt Input transition rise/fall time 500 500 ns
TA Operating free-air temperature –55 125 –40 85 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating SMOS Inputs, literature number SCBA004.
(2) SN54HCT125 is in product preview.

5.3 Thermal Information

D (SOIC) N (PDIP)
THERMAL METRIC 14 PINS 14 PINS UNIT
(1)
RθJA Junction-to-ambient thermal resistance 138.7 75.3 °C/W
RθJC Junction-to-case (top) thermal resistance 93.8 68.6 °C/W
RθJB Junction-to-board thermal resistance 94.7 55.1 °C/W
ψJT Junction-to-top characterization paramete 49.1 41.1 °C/W
ψJB Junction-to-board characterization parameter 94.3 54.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.

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5.4 Electrical Characteristics

VCC TA = 25°C SN54HCT125(3) SN74HCT125
PARAMETER TEST CONDITIONS(1) UNIT
(V) MIN TYP MAX MIN MAX MIN MAX
IOH = –20 μA 4.4 4.499 4.4 4.4
VOH High-level output voltage 4.5 V
IOH = –6 mA 3.98 4.3 3.7 3.84
IOL = 20 μA 0.001 0.1 0.1 0.1
VOL Low-level output voltage 5.5 V
IOL = 6 mA 0.17 0.26 0.4 0.33
II Input hold current VI = VCC or 0 5.5 ±0.1 ±100 ±1000 ±1000 nA
IOZ Off-state output current Vo = VCC or 0 5.5 ±0.01 ±0.5 ±10 ±5 μA
ICC Supply current VI = VCC or 0. IO = 0 5.5 8 160 80 μA
One input at 0.5 V or 2.4
ΔICC (2) Supply-current change V, Other inputs at 0 or 5.5 1.4 2.4 3 2.9 mA
VCC
4.5 to
Ci Input capacitance 3 10 10(4) 10 pF
5.5

(1) VI = VIH or VIL, unless otherwise noted.

(2) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
(3) SN54HCT125 is in product preview.
(4) On products compliant to MIL-PRF-38535, this parameter is not production tested.

5.5 Switching Characteristics

CL = 50 pF. See Figure 6
SN54HCT125 SN74HCT125
FROM VCC TA = 25°C (1)
PARAMETER TO (OUTPUT)
(INPUT) (V)
MIN TYP MAX MIN MAX MIN MAX
4.5 11 20 39 25
tpd Propagation delay A Y ns
5.5 10 18 35 22
4.5 18 28 42 35
ten Enable time OE Y ns
5.5 15 25 38 31
4.5 15 26 39 33
tdis Diable time OE Y ns
5.5 13 23 35 30
4.5 8 15 22 19
tt Transition time Any ns
5.5 7 14 21 17

(1) SN54HCT125 is in product preview.

5.5 Switching Characteristics

CL = 150 pF. See Figure 6
SN54HCT125 SN74HCT125
FROM VCC TA = 25°C (1)
PARAMETER TO (OUTPUT)
(INPUT) (V)
MIN TYP MAX MIN MAX MIN MAX
4.5 19 36 58 46
tpd Propagation delay A Y ns
5.5 16 32 48 42
4.5 25 40 60 50
ten Enable time OE Y ns
5.5 21 35 53 43
4.5 17 42 63 53
tt Transition time Any ns
5.5 14 38 57 48

(1) SN54HCT125 is in product preview.

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5.6 Operating Characteristics

TA = 25°C
Test Conditions TYP UNIT
Cpd Power dissipation capacitance No load 35 pF

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6 Parameter Measurement Information

tpd is the maximum between tPLH and tPHL
tt is the maximum between tTLH and tTHL

Figure 6-1. Load Circuit

Figure 6-2.

Figure 6-3. Voltage Waveforms

Propagation Delay Times

Figure 6-4. Voltage Waveforms

Enable and Disable Times For 3-state Outputs

A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when diabled by the
output control.
Waveform 2 is for an output with internal conditions such that the output is high except when diabled by the
output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following charactersitics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.

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7 Detailed Description
7.1 Overview
These bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the
associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
7.2 Functional Block Diagram

7.3 Device Functional Modes

Table 7-1. Function Table
(each gate)
INPUTS OUTPUT
OE A Y
L H H
L L L
H X Z

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8 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.

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10 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Documentation Support
10.1.1 Related Documentation

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74HCT125DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HCT125 Samples

SN74HCT125DRE4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT125 Samples

SN74HCT125N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HCT125N Samples

SN74HCT125NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HCT125N Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

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continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HCT125DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HCT125DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

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TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HCT125DR SOIC D 14 2500 356.0 356.0 35.0
SN74HCT125DR SOIC D 14 2500 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

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TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN74HCT125N N PDIP 14 25 506 13.97 11230 4.32
SN74HCT125N N PDIP 14 25 506 13.97 11230 4.32
SN74HCT125NE4 N PDIP 14 25 506 13.97 11230 4.32
SN74HCT125NE4 N PDIP 14 25 506 13.97 11230 4.32

Pack Materials-Page 3
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