SN54ACT373, SN74ACT373

SCAS544F – OCTOBER 1995 – REVISED MAY 2024

SNx4ACT373 Octal D-Type Transparent Latches with 3-State Outputs

1 Features 2 Description
• Operation of 4.5V to 5.5V VCC These 8-bit latches feature 3-state outputs designed
• Inputs accept voltages to 5.5V specifically for driving highly capacitive or relatively
• Max tpd of 10ns at 5V low-impedance loads. The devices are particularly
• Inputs are TTL-voltage compatible suitable for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
Device Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
DB (SSOP, 20) 7.2mm × 7.8mm 7.50mm x 5.30mm
DW (SOIC, 20) 12.8mm × 10.3mm 12.80mm x 7.50mm
SNx4ACT373 N (PDIP, 20) 24.33mm × 9.4mm 24.33mm x 6.35mm
NS (SOP, 20) 12.6mm × 7.8mm 12.6mm x 5.3mm
PW (TSSOP, 20) 6.5mm × 6.4mm 6.50mm x 4.40mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.
(2) The package size (length × width) is a nominal value and
includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does
not include pins.

Logic Diagram (Positive Logic)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54ACT373, SN74ACT373
SCAS544F – OCTOBER 1995 – REVISED MAY 2024 www.ti.com

Table of Contents
1 Features............................................................................1 6.3 Device Functional Modes............................................8
2 Description.......................................................................1 7 Application and Implementation.................................... 9
3 Pin Configuration and Functions...................................3 7.1 Power Supply Recommendations...............................9
4 Specifications.................................................................. 4 7.2 Layout......................................................................... 9
4.1 Absolute Maximum Ratings........................................ 4 8 Device and Documentation Support............................10
4.2 Recommended Operating Conditions.........................4 8.1 Documentation Support (Analog)..............................10
4.3 Thermal Information....................................................4 8.2 Receiving Notification of Documentation Updates....10
4.4 Electrical Characteristics.............................................5 8.3 Support Resources................................................... 10
4.5 Timing Requirements.................................................. 5 8.4 Trademarks............................................................... 10
4.6 Switching Characteristics............................................6 8.5 Electrostatic Discharge Caution................................10
4.7 Operating Characteristics........................................... 6 8.6 Glossary....................................................................10
5 Parameter Measurement Information............................ 7 9 Revision History............................................................ 10
6 Detailed Description........................................................8 10 Mechanical, Packaging, and Orderable
6.1 Overview..................................................................... 8 Information.................................................................... 10
6.2 Functional Block Diagram........................................... 8

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3 Pin Configuration and Functions

Figure 3-1. SN54ACT373 J or W Package; Figure 3-2. SN54ACT373 FK Package (Top View)
SN74ACT373 DB, DW, N, NS, or PW Package (Top
View)

Table 3-1. Pin Functions

PIN
SSOP, TVSOP, SOIC, TYPE DESCRIPTION
NO. VQFN
SO, or TSSOP
1 OE OE I Output Enable
2 1Q 1Q O 1Q Output
3 1D 1D I 1D Input
4 2D 2D I 2D Input
5 2Q 2Q O 2Q Output
6 3Q 3Q O 3Q Output
7 3D 3D I 3D Input
8 4D 4D I 4D Input
9 4Q 4Q O 4Q Output
10 GND GND — Ground Pin
11 LE LE I Latch Enable
12 5Q 5Q O 5Q Output
13 5D 5D I 5D Input
14 6D 6D I 6D Input
15 6Q 6Q O 6Q Output
16 7Q 7Q O 7Q Output
17 7D 7D I 7D Input
18 8D 8D I 8D Input
19 8Q 8Q O 8Q Output
20 VCC VCC — Power Pin

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4 Specifications
4.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage range –0.5 7 V
VI 2 Input voltage range –0.5 VCC + 0.5 V
VO 2 Output voltage range –0.5 VCC + 0.5 V
IIK Input clamp current (VI < 0 or VI > VCC) ±20 mA
IOK Output clamp current (VO < 0 or VO > VCC) ±20 mA
IO Continuous output current (VO = 0 to VCC) ±50 mA
Continuous current through VCC or GND ±200 mA
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

4.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
SN54ACT373 SN74ACT373
UNIT
MIN MAX MIN MAX
VCC Supply voltage 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VI Input voltage 0 VCC 0 VCC V
VO Output voltage 0 VCC 0 VCC V
IOH High-level output current –24 –24 mA
IOL Low-level output current 24 24 mA
∆t/∆v Input transition rise or fall rate 8 8 ns/V
TA Operating free-air temperature –55 125 –40 85 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

4.3 Thermal Information

SNx4ACT373
THERMAL METRIC(1) DB (SSOP) DW (SOIC) N (PDIP) NS (SO) PW (TSSOP) UNIT
20 PINS
RθJA Junction-to-ambient thermal resistance 117.2 101.2 69 60 126.2 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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4.4 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C SN54ACT373 SN74ACT373
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
4.5 V 4.4 4.49 4.4 4.4
IOH = –50 µA
5.5 V 5.4 5.49 5.4 5.4
4.5 V 3.86 3.7 3.76
VOH IOH = –24 mA V
5.5 V 4.86 4.7 4.76
(1)
IOH = –50 mA 5.5 V 3.85
(1)
IOH = –75 mA 5.5 V 3.85
4.5 V 0.1 0.1 0.1
IOL = 50µA
5.5 V 0.1 0.1 0.1
4.5 V 0.36 0.44 0.44
VOL IOL = 24 mA V
5.5 V 0.36 0.44 0.44
(1)
IOL = 50 mA 5.5 V 1.65
(1)
IOL = 75 mA 5.5 V 1.65
IOZ VO = VCC or GND 5.5 V ±0.25 ±5 ±2.5 µA
II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
ICC VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA
One input at 3.4 V, Other inputs at
∆ICC (2) 5.5 V 0.6 1.5 1.5 mA
GND or VCC
Ci VI = VCC or GND 5V 4.5 pF

(1) Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
(2) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.

4.5 Timing Requirements

over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Load Circuit and
Voltage Waveforms)
TA = 25°C SN54ACT373 SN74ACT373
UNIT
MIN MAX MIN MAX MIN MAX
tw Pulse duration, LE high 7 8.5 8 ns
Setup time, data before
tsu 7 8.5 8 ns
LE↓
th Hold time, data after LE↓ 0 1 1 ns

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4.6 Switching Characteristics

over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Load Circuit and
Voltage Waveforms)
TA = 25°C SN54ACT373 SN74ACT373
PARAMETER FROM (INPUT) TO (OUTPUT) UNIT
MIN TYP MAX MIN MAX MIN MAX
tPLH 2.5 8.5 10 1.5 12.5 1.5 11.5
D Q ns
tPHL 2 8 10 1.5 12.5 1.5 11.5
tPLH 2.5 8.5 11 1.5 12.5 2 11.5
LE Q ns
tPHL 2 8 10 1.5 11.5 1.5 11.5
tPZH 2 8 9.5 1.5 11.5 1.5 10.5
OE Q ns
tPZL 2 7.5 9 1.5 11 1.5 10.5
tPHZ 2.5 9 11 1.5 14 2.5 12.5
OE Q ns
tPLZ 1.5 7.5 8.5 1.5 11 1 10

4.7 Operating Characteristics

VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance CL = 50 pF, f = 1 MHz 40 pF

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5 Parameter Measurement Information

A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.

Figure 5-1. Load Circuit and Voltage Waveforms

TEST S1
tPLH/tPHL Open
tPLZ/tPZL 2 × VCC
tPHZ/tPZH Open

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6 Detailed Description
6.1 Overview
The eight latches are D-type transparent latches. When the latch-enable (LE) input is high, the Q outputs follow
the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines in
bus-organized systems without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
6.2 Functional Block Diagram

Figure 6-1. Logic Diagram (Positive Logic)

6.3 Device Functional Modes

Table 6-1. Function Table (Each Latch)
INPUTS OUTPUT Q
OE LE D
L H H H
L H L L
L L X Q0
H X X Z

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7 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

7.1 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Section
4.2.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended; if there are multiple VCC pins, then 0.01 μF or 0.022 μF is recommended for
each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF
and a 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
7.2 Layout
7.2.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Layout Diagram are rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the
part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part
when asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.
7.2.2 Layout Example

VCC GND
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation

F Bypass capacitor
OE VCC placed close to the
device
1 20
1Q 2 19 8Q
1D 3 18 8D
Unused input
tied to GND 2D 4 17 7D
Unused output 7Q
2Q 5 16
left floating
3Q 6 GND 15 6Q
3D 7 14 6D
4D 8 13 5D

4Q 9 12 5Q
10 11
Avoid 90° GND LE
corners for
signal lines

Figure 7-1. Layout example for the SNx4ACT373

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8 Device and Documentation Support

8.1 Documentation Support (Analog)
8.1.1 Related Documentation
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8-1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
SN54ACT373 Click here Click here Click here Click here Click here
SN74ACT373 Click here Click here Click here Click here Click here

8.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

8.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (October 2002) to Revision F (May 2024) Page
• Added Device Information table, Pin Functions table, Thermal Information table, Device Functional Modes,
Application and Implementation section Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ................................................................................................. 1
• Updated RθJA values: DB = 70 to 117.2, DW = 58 to 101.2, PW = 83 to 126.2, all values in °C/W ................ 4

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 31-Oct-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-87556012A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 87556012A
SNJ54ACT
373FK
5962-8755601RA ACTIVE CDIP J 20 20 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8755601RA Samples
& Green SNJ54ACT373J
5962-8755601SA ACTIVE CFP W 20 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8755601SA Samples
& Green SNJ54ACT373W
5962-8755601VRA ACTIVE CDIP J 20 20 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8755601VR Samples
& Green A
SNV54ACT373J
SN74ACT373DBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AD373 Samples

SN74ACT373DW OBSOLETE SOIC DW 20 TBD Call TI Call TI -40 to 85 ACT373

SN74ACT373DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT373 Samples

SN74ACT373N ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74ACT373N Samples

SN74ACT373NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT373 Samples

SN74ACT373PW OBSOLETE TSSOP PW 20 TBD Call TI Call TI -40 to 85 AD373

SN74ACT373PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AD373 Samples

SNJ54ACT373FK ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 87556012A
SNJ54ACT
373FK
SNJ54ACT373J ACTIVE CDIP J 20 20 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8755601RA Samples
& Green SNJ54ACT373J
SNJ54ACT373W ACTIVE CFP W 20 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8755601SA Samples
& Green SNJ54ACT373W

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 31-Oct-2024

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54ACT373, SN54ACT373-SP, SN74ACT373 :

• Catalog : SN74ACT373, SN54ACT373

• Enhanced Product : SN74ACT373-EP, SN74ACT373-EP
• Military : SN54ACT373
• Space : SN54ACT373-SP

NOTE: Qualified Version Definitions:

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 31-Oct-2024

• Catalog - TI's standard catalog product

• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Apr-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74ACT373DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74ACT373DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74ACT373DWR SOIC DW 20 2000 330.0 24.4 10.9 13.3 2.7 12.0 24.0 Q1
SN74ACT373DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
SN74ACT373NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1
SN74ACT373PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74ACT373PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Apr-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ACT373DBR SSOP DB 20 2000 356.0 356.0 35.0
SN74ACT373DBR SSOP DB 20 2000 353.0 353.0 32.0
SN74ACT373DWR SOIC DW 20 2000 356.0 356.0 45.0
SN74ACT373DWR SOIC DW 20 2000 367.0 367.0 45.0
SN74ACT373NSR SO NS 20 2000 367.0 367.0 45.0
SN74ACT373PWR TSSOP PW 20 2000 353.0 353.0 32.0
SN74ACT373PWR TSSOP PW 20 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Apr-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-87556012A FK LCCC 20 55 506.98 12.06 2030 NA
5962-8755601SA W CFP 20 25 506.98 26.16 6220 NA
SN74ACT373N N PDIP 20 20 506 13.97 11230 4.32
SNJ54ACT373FK FK LCCC 20 55 506.98 12.06 2030 NA
SNJ54ACT373W W CFP 20 25 506.98 26.16 6220 NA

Pack Materials-Page 3
 PACKAGE OUTLINE
PW0020A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
6.6 C
TYP PLANE
A 6.2
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1

2X
6.6 5.85
6.4
NOTE 3

10
11
0.30
20X
4.5 0.19 1.2 MAX
B
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE 0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220206/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

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 EXAMPLE BOARD LAYOUT
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220206/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220206/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DB0020A SCALE 2.000
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C
PIN 1 INDEX AREA SEATING
18X 0.65 PLANE
20
1

2X
7.5
5.85
6.9
NOTE 3

10
11 0.38
20X
0.22
5.6 0.1 C A B
B
5.0
NOTE 4

2 MAX
(0.15) TYP 0.25
SEE DETAIL A GAGE PLANE

0.95 0.05 MIN

0 -8 0.55

DETAIL A
A 15

TYPICAL

4214851/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.

www.ti.com
 EXAMPLE BOARD LAYOUT
DB0020A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

20X (1.85) SYMM

1 (R0.05) TYP

20X (0.45) 20

SYMM
18X (0.65)

10 11

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4214851/B 08/2019
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DB0020A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

20X (1.85) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4214851/B 08/2019
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

www.ti.com
 PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1

13.0 2X
12.6 11.43
NOTE 3

10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4

0.33
TYP
0.10

0.25
SEE DETAIL A GAGE PLANE

1.27 0.3
0 -8 0.40 0.1

DETAIL A
TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2) SYMM

1
20

20X (0.6)

18X (1.27)

SYMM

(R0.05)
TYP

10 11

(9.3)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2)
SYMM
1
20

20X (0.6)

18X (1.27)

SYMM

10 11

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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