CD54HC259, CD74HC259, CD54HCT259, CD74HCT259

SCHS173D – NOVEMBER 1997 – REVISED NOVEMBER 2021

CDx4HC(T)259 High-Speed SMOS Logic 8-Bit Addressable Latch

1 Features 2 Description
• Buffered inputs and outputs The CDx4HC(T)259 is an 8-bit addressable latch with
• Four operating modes three active modes of operation (addressable latch,
• Typical propagation delay of 15ns at VCC = 5V, CL memory, 8-line demultiplexer) and one reset mode.
= 15pF, TA = 25oC
Device Information
• Fanout (over temperature range) (1)
PART NUMBER PACKAGE BODY SIZE (NOM)
– Standard Outputs: 10 LSTTL loads
CD54HC259F3A CDIP (16) 21.34 mm × 6.92 mm
– Bus driver outputs: 15 LSTTL loads
• Wide operating temperature range: -55oC to 125oC CD54HCT259F3A CDIP (16) 21.34 mm × 6.92 mm
• Balanced propagation delay and transition times CD74HC259E PDIP (16) 19.31 mm × 6.35 mm
• Significant power reduction compared to LSTTL CD74HCT259E PDIP (16) 19.31 mm × 6.35 mm
logic ICs CD74HC259M SOIC (16) 9.90 mm × 3.90 mm
• HC types CD74HCT259M SOIC (16) 9.90 mm × 3.90 mm
– 2 V to 6 V operation
– High noise immunity: NIL = 30%, NIH = 30% of (1) For all packages see the orderable addendum at the end of
VCC at VCC = 5 V the data sheet.
• HCT types
– 4.5 V to 5.5 V operation
– Direct LSTTL input logic compatability, VIL = 0.8
V (max), VIH = 2 V (min)
– CMOS input compatibility, II ≤ 1µA at VOL, VOH
3:8 DECODER LATCH OUTPUT STORAGE
ENABLE
000 D
LE Q Q0
R
S0
001 D
LE Q Q1
R

S1 010 D
LE Q Q2
R

011 D
S2 LE Q Q3
R

100 D
LE Q Q4
R

101 D
LE Q Q5
R

G 110 D
LE Q Q6
R

D D
111
LE Q Q7
R
CLR

Functional Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259
SCHS173D – NOVEMBER 1997 – REVISED NOVEMBER 2021 www.ti.com

Table of Contents
1 Features............................................................................1 7.2 Functional Block Diagram......................................... 10
2 Description.......................................................................1 7.3 Device Functional Modes..........................................11
3 Revision History.............................................................. 2 8 Power Supply Recommendations................................12
4 Pin Configuration and Functions...................................3 9 Layout.............................................................................12
5 Specifications.................................................................. 4 9.1 Layout Guidelines..................................................... 12
5.1 Absolute Maximum Ratings........................................ 4 10 Device and Documentation Support..........................13
5.2 Recommended Operating Conditions.........................4 10.1 Documentation Support.......................................... 13
5.3 Thermal Information....................................................4 10.2 Receiving Notification of Documentation Updates..13
5.4 Electrical Characteristics.............................................5 10.3 Support Resources................................................. 13
5.5 Prerequisite for Switching Characteristics.................. 6 10.4 Trademarks............................................................. 13
(2)
5.6 Switching Characteristics ........................................ 7 10.5 Electrostatic Discharge Caution..............................13
6 Parameter Measurement Information............................ 8 10.6 Glossary..................................................................13
7 Detailed Description......................................................10 11 Mechanical, Packaging, and Orderable
7.1 Overview................................................................... 10 Information.................................................................... 13

3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2003) to Revision D (November 2021) Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern datasheet standards.............................................................................................................................. 1
• Updated pin names to match current TI naming conventions. A0 is now S0, A1 is now S1, A2 is now S2.......... 3

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4 Pin Configuration and Functions

S0 1 16 VCC
S1 2 15 CLR
S2 3 14 G
Q0 4 13 D
Q1 5 12 Q7
Q2 6 11 Q6
Q3 7 10 Q5
GND 8 9 Q4

J, D or PW Package
16-Pin CDIP, SOIC or TSSOP
Top View

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5 Specifications
5.1 Absolute Maximum Ratings
(1)
Over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage -0.5 7 V
IIK Input clamp diode current For VI < -0.5V or VI > VCC + 0.5V ±20 mA
IOK Output clamp diode current For VO < -0.5V or VO > VCC + 0.5V ±20 mA
IO Drain current, per output For -0.5V < VO < VCC + 0.5V ±25 mA
Output source or sink
IO For VO > -0.5V or VO < VCC + 0.5V ±25 mA
current per output pin
Continuous current through VCC or GND ±50 mA
TJ Junction temperature 150 °C
Tstg Storage temperature -65 150 °C
Lead temperature (Soldering 10s) (SOIC - lead tips only) 300 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

5.2 Recommended Operating Conditions

MIN MAX UNIT
HC Types 2 6
VCC Supply voltage range V
HCT Types 4.5 5.5
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
VCC = 2V 1000
tt Input rise and fall time VCC = 4.5V 500 ns
VCC = 6V 400
TA Temperature range -55 125 °C

5.3 Thermal Information

CD74HC259, CD74HCT259
N (PDIP) D (SOIC)
THERMAL METRIC 16 PINS 16 PINS UNIT
(1)
RθJA Junction-to-ambient thermal resistance 67 73 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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5.4 Electrical Characteristics

TEST 25°C -40°C to 85°C -55°C to 125°C
PARAMETER VCC (V) UNIT
CONDITIONS MIN TYP MAX MIN MAX MIN MAX
HC TYPES
2 1.5 1.5 1.5 V
VIH High-level input voltage 4.5 3.15 3.15 3.15 V
6 4.2 4.2 4.2 V
2 0.5 0.5 0.5 V
VIL Low-level input voltage 4.5 1.35 1.35 1.35 V
6 1.8 1.8 1.8 V
IOH = – 20 µA 2 1.9 1.9 1.9 V
High-level output voltage IOH = – 20 µA 4.5 4.4 4.4 4.4 V
VOH IOH = – 20 µA 6 5.9 5.9 5.9 V
IOH= – 4 mA 4.5 3.98 3.84 3.7 V
High-level output voltage
IOH = – 5.2 mA 6 5.48 5.34 5.2 V
IOL = 20 µA 2 0.1 0.1 0.1 V
Low-level output voltage IOL = 20 µA 4.5 0.1 0.1 0.1 V
VOL IOL = 20 µA 6 0.1 0.1 0.1 V
IOL= 4 mA 4.5 0.26 0.33 0.4 V
Low-level output voltage
IOL = 5.2 mA 6 0.26 0.33 0.4 V
II Input leakage current VI = VCC or GND 6 ±0.1 ±1 ±1 µA
ICC Supply current VI = VCC or GND 6 8 80 160 µA
HCT TYPES
4.5 to
VIH High-level input voltage 2 2 2 V
5.5
4.5 to
VIL Low-level input voltage 0.8 0.8 0.8 V
5.5
High-level output voltage VOH = – 20 µA 4.5 4.4 4.4 4.4 V
VOH
HIgh-level output voltage VOH = – 4 mA 4.5 3.98 3.84 3.7 V
Low-level output voltage VOL = 20 µA 4.5 0.1 0.1 0.1 V
VOL
Low-level output voltage VOL = 4 mA 4.5 0.26 0.33 0.4 V
II Input leakage current VI = VCC or GND 5.5 ±0.1 ±1 ±1 µA
ICC Supply current VI = VCC or GND 5.5 8 80 160 µA
One of A0 - A2
4.5 to
and LE inputs 100 540 675 735
5.5
held at VCC – 2.1
Additional supply current
∆ICC(1) D input held at 4.5 to µA
per input pin 100 432 540 588
VCC – 2.1 5.5
MR input held at 4.5 to
100 270 337.5 367.5
VCC – 2.1 5.5

(1) VI = VIH or VIL, unless otherwise noted.

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5.5 Prerequisite for Switching Characteristics

25°C -40°C to 85°C -55°C to 125°C
PARAMETER VCC (V) UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
HC TYPES
2 70 90 105
tWL Pulse Width G 4.5 14 18 21 ns
5 12 15 18
2 70 90 105
tWL CLR 4.5 14 18 21 ns
6 12 15 18
Setup time 2 80 100 120
tSU D to G 4.5 16 20 24 ns
S to G 6 14 17 20
Hold time 2 0 0 0
tH D to G 4.5 0 0 0 ns
S to G 6 0 0 0
HCT TYPES
Pulse width
tWL G 4.5 18 23 27 ns
CLR
Setup Time
tSU D to G 4.5 17 21 26 ns
S to G
Hold Time
tH D to G 4.5 0 0 0 pF
S to G

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(2)
5.6 Switching Characteristics
CL = 50pF, Input tt = 6ns
25°C -40°C to 85°C -55°C to 125°C
PARAMETER VCC (V) UNIT
MIN TYP MAX MIN MAX MIN MAX
HC TYPES
2 185 230 280
(1)
D to Q 4.5 15 37 46 56 ns
6 31 39 48
2 170 215 255
(1)
G to Q 4.5 14 34 43 51 ns
6 29 37 43
tpd
2 185 230 280
(1)
S to Q 4.5 15 37 46 56 ns
6 31 39 48
2 155 195 235
(1)
CLR to Q 4.5 13 31 39 47 ns
6 26 33 40
2 75 95 110
tt Output transition time 4.5 15 19 22 ns
6 13 16 19
(1) (1)
Cpd Power dissipation Capacitance 5 21 pF
Ci Input capacitance 10 10 10 10 pF
HCT TYPES
(1)
D to Q 4.5 16 39 49 59 ns
(1)
G to Q 4.5 16 38 48 57 ns
tpd (1)
S to Q 4.5 17 41 51 61 ns
(1)
CLR to Q 4.5 16 39 49 59 pF
(1) (1)
Cpd Power dissipaction Capacitance 5 22 pF
Ci Input Capacitance 10 10 10 10 pF
tt Output transition time 4.5 15 19 22 ns

(1) CL = 15pF and VCC = 5 V.

(2) For details on CMOS power calculation see, SCAA053B.

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6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.

Test
Point

From Output
Under Test
CL(1)

(1) CL includes probe and test-fixture capacitance.

Figure 6-1. Load Circuit for Push-Pull Outputs

tw VCC
VCC Clock
50%
Input
Input 50% 50% 0V
0V
tsu th
Figure 6-2. Voltage Waveforms, Standard CMOS VCC
Inputs Pulse Duration Data
50% 50%
Input
0V
Figure 6-3. Voltage Waveforms, Standard CMOS
Inputs Setup and Hold Times
VCC VCC
90% 90%
Input 50% 50% Input
10% 10%
0V 0V
(1) (1)
tr(1) tf(1)
tPLH tPHL
VOH VOH
90% 90%
Output 50% 50% Output
10% 10%
VOL VOL
(1) (1)
tr(1) tf(1)
tPHL tPLH
(1) The greater between tr and tf is the same as tt.
VOH
Figure 6-5. Voltage Waveforms, Input and Output
Output 50% 50% Transition Times for Standard CMOS Input Devices
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-4. Voltage Waveforms, Standard CMOS
Inputs Setup Propagation Delays

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tw 3V
3V Clock
1.3V
Input
Input 1.3V 1.3V 0V
0V
tsu th
Figure 6-6. Voltage Waveforms, TTL-Compatible 3V
CMOS Inputs Pulse Duration Data
1.3V 1.3V
Input
0V
Figure 6-7. Voltage Waveforms, TTL-Compatible
CMOS Inputs Setup and Hold Times
3V
Input 1.3V 1.3V
0V
tPLH(1) tPHL(1)
VOH
Output
50% 50%
Waveform 1
VOL
tPHL(1) tPLH(1)
VOH
Output
50% 50%
Waveform 2
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-8. Voltage Waveforms, TTL-Compatible CMOS Inputs Propagation Delays

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7 Detailed Description
7.1 Overview
The CDx4HC(T)259 8-bit addressable latches are designed for general-purpose storage applications in
digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or
demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable latches
and being a 1-of-8 decoder or demultiplexer with active-high outputs.
Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs:
• Addressable-latch mode: CLR = HIGH; G = LOW
– Data at the data-in terminal is written into the addressed latch
– The addressed latch follows the data input, with all unaddressed latches remaining in their previous states
• Memory mode: CLR = HIGH; G = HIGH
– All latches remain in their previous states and are unaffected by the data or address inputs
– To eliminate the possibility of entering erroneous data in the latches, G should be held high (inactive) while
the address lines are changing
• 1-of-8 decoding or demultiplexing mode: CLR = LOW; G = LOW
– The addressed output follows the level of the D input with all other outputs low
• Clear mode: CLR = LOW; G = HIGH
– All outputs are low and unaffected by the address and data inputs
7.2 Functional Block Diagram
3:8 DECODER LATCH OUTPUT STORAGE
ENABLE
000 D
LE Q Q0
R
S0
001 D
LE Q Q1
R

S1 010 D
LE Q Q2
R

011 D
S2 LE Q Q3
R

100 D
LE Q Q4
R

101 D
LE Q Q5
R

G 110 D
LE Q Q6
R

D D
111
LE Q Q7
R
CLR

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7.3 Device Functional Modes

The Function Tableand Latch Selection Table below list the functional modes of the CDx4HC(T)259.
Table 7-1. Function Table
INPUTS(1) OUTPUT OF
EACH OTHER
ADDRESSED FUNCTION
CLR G (2) OUTPUT(2)
LATCH
H L D QiO Addressable
latch
H H QiO QiO Memory
L L D L 8-line
demultiplexer
L H L L Clear

(1) H = High voltage level, L = Low voltage level

(2) QiO = Previous output state of selected latch, D = Data input
logic value

Table 7-2. Latch Selection Table

SELECT INPUTS(1) LATCH
S2 S1 S0 ADDRESSED

L L L 0
L L H 1
L H L 2
L H H 3
H L L 4
H L H 5
H H L 6
H H H 7

(1) H = High Voltage Level, L = Low Voltage Level

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8 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.

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10 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Documentation Support
10.1.1 Related Documentation

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-8985201EA ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8985201EA Samples
& Green CD54HCT259F3A
CD54HC259F3A ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8551901EA Samples
& Green CD54HC259F3A
CD54HCT259F3A ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8985201EA Samples
& Green CD54HCT259F3A
CD74HC259E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC259E Samples

CD74HC259M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HC259M Samples

CD74HCT259E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT259E Samples

CD74HCT259EE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT259E Samples

CD74HCT259M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HCT259M Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

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(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC259, CD54HCT259, CD74HC259, CD74HCT259 :

• Catalog : CD74HC259, CD74HCT259

• Military : CD54HC259, CD54HCT259

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC259M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HCT259M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

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TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC259M96 SOIC D 16 2500 356.0 356.0 35.0
CD74HCT259M96 SOIC D 16 2500 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Mar-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD74HC259E N PDIP 16 25 506 13.97 11230 4.32
CD74HC259E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT259E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT259E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT259EE4 N PDIP 16 25 506 13.97 11230 4.32
CD74HCT259EE4 N PDIP 16 25 506 13.97 11230 4.32

Pack Materials-Page 3
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