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Buk9y40 55B

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Nalson
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© © All Rights Reserved
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BUK9Y40-55B

N-channel TrenchMOS logic level FET


Rev. 03 — 22 February 2008 Product data sheet

1. Product profile

1.1 General description


Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using Nexperia High-Performance Automotive (HPA) TrenchMOS technology.
This product has been designed and qualified to the appropriate AEC standard for use
in automotive critical applications.

1.2 Features
„ 175 °C rated „ Logic level compatible
„ Q101 compliant „ Very low on-state resistance

1.3 Applications
„ 12 V and 24 V loads „ Automotive systems
„ General purpose power switching „ Motors, lamps and solenoids

1.4 Quick reference data


Table 1. Quick reference
Symbol Parameter Conditions Min Typ Max Unit
ID drain current VGS = 5 V; Tmb = 25 °C; - - 26 A
see Figure 1 and 4
Ptot total power dissipation Tmb = 25 °C; see Figure 2 - - 59 W
Static characteristics
RDSon drain-source on-state VGS = 5 V; ID = 15 A; - 34 40 mΩ
resistance Tj = 25 °C; see Figure 12 and
13
Avalanche ruggedness
EDS(AL)S non-repetitive ID = 26 A; Vsup ≤ 55 V; - - 36 mJ
drain-source avalanche RGS = 50 Ω; VGS = 5 V;
energy Tj(init) = 25 °C; unclamped
Nexperia BUK9Y40-55B
N-channel TrenchMOS logic level FET

2. Pinning information
Table 2. Pinning
Pin Symbol Description Simplified outline Graphic symbol
1 S source
mb D
2 S source
3 S source G
4 G gate
mbb076 S
mb D mounting base;
1 2 3 4
connected to drain
SOT669 (LFPAK)

3. Ordering information
Table 3. Ordering information
Type number Package
Name Description Version
BUK9Y40-55B LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669

4. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 55 V
VDGR drain-gate voltage RGS = 20 kΩ - 55 V
VGS gate-source voltage -15 15 V
ID drain current Tmb = 100 °C; VGS = 5 V; see Figure 1 - 18 A
Tmb = 25 °C; VGS = 5 V; see Figure 1 and 4 - 26 A
IDM peak drain current Tmb = 25 °C; tp ≤ 10 μs; pulsed; see Figure 4 - 106 A
Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 59 W
Tstg storage temperature -55 175 °C
Tj junction temperature -55 175 °C
Avalanche ruggedness
EDS(AL)S non-repetitive ID = 26 A; Vsup ≤ 55 V; RGS = 50 Ω; VGS = 5 V; - 36 mJ
drain-source avalanche Tj(init) = 25 °C; unclamped
energy
EDS(AL)R repetitive drain-source see Figure 3 [1][2] - - J
avalanche energy [3]

Source-drain diode
IS source current Tmb = 25 °C - 26 A
ISM peak source current tp ≤ 10 μs; pulsed; Tmb = 25 °C - 106 A

[1] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
[2] Repetitive avalanche rating limited by average junction temperature of 170 °C.
[3] Refer to application note AN10273 for further information.

BUK9Y40-55B_3 © Nexperia B.V. 2017. All rights reserved

Product data sheet Rev. 03 — 22 February 2008 2 of 12


Nexperia BUK9Y40-55B
N-channel TrenchMOS logic level FET

03nn93 03na19
30 120

ID Pder
(A) (%)

20 80

10 40

0 0
0 50 100 150 200 0 50 100 150 200
Tmb (°C) Tmb (°C)

VGS • 5V P tot
P der = × 100 %
P tot (25°C )

Fig 1. Continuous drain current as a function of Fig 2. Normalized total power dissipation as a
mounting base temperature function of mounting base temperature

03np80
102

IAV
(A)
(1)
10

(2)

(3)

10−1

10−2
10−3 10−2 10−1 1 10
tAV (ms)

(1) Singleípulse;T j = 25 °C.


(2) Singleípulse;T j = 150 °C.
(3) Repetitive.

Fig 3. Single-shot and repetitive avalanche rating; avalanche current as a function of avalanche period

BUK9Y40-55B_3 © Nexperia B.V. 2017. All rights reserved

Product data sheet Rev. 03 — 22 February 2008 3 of 12


Nexperia BUK9Y40-55B
N-channel TrenchMOS logic level FET

03nn94
103
ID
(A)
Limit RDSon = VDS / ID
102 tp = 10 μs

10 100 μs

1 1 ms
10 ms
100 ms
DC

10-1
1 10 VDS (V) 102

Tmb = 25 °C; IDM is single pulse

Fig 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

5. Thermal characteristics
Table 5. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-mb) thermal resistance see Figure 5 - - 2.5 K/W
from junction to
mounting base

03nn95
10

Zth (j-mb)
(K/W)

1 δ = 0.5

0.2

0.1
tp
0.05 P δ=
10-1 T
0.02

single shot tp t
T
10-2
10-6 10-5 10-4 10-3 10-2 10-1 tp (s) 1

Fig 5. Transient thermal impedance from junction to ambient as a function of pulse duration

BUK9Y40-55B_3 © Nexperia B.V. 2017. All rights reserved

Product data sheet Rev. 03 — 22 February 2008 4 of 12


Nexperia BUK9Y40-55B
N-channel TrenchMOS logic level FET

6. Characteristics
Table 6. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source ID = 0.25 mA; VGS = 0 V; 55 - - V
breakdown voltage Tj = 25 °C
ID = 0.25 mA; VGS = 0 V; 50 - - V
Tj = -55 °C
VGS(th) gate-source threshold ID = 1 mA; VDS = VGS; 0.5 - - V
voltage Tj = 175 °C; see Figure 11
ID = 1 mA; VDS = VGS; Tj = 25 °C; 1.1 1.5 2 V
see Figure 11
ID = 1 mA; VDS = VGS; - - 2.3 V
Tj = -55 °C; see Figure 11
IDSS drain leakage current VDS = 55 V; VGS = 0 V; Tj = 25 °C - 0.02 1 μA
VDS = 55 V; VGS = 0 V; - - 500 μA
Tj = 175 °C
IGSS gate leakage current VDS = 0 V; VGS = 15 V; Tj = 25 °C - 2 100 nA
VDS = 0 V; VGS = -15 V; - 2 100 nA
Tj = 25 °C
RDSon drain-source on-state VGS = 5 V; ID = 15 A; Tj = 175 °C; - - 84 mΩ
resistance see Figure 12 and 13
VGS = 10 V; ID = 15 A; Tj = 25 °C - 32 36 mΩ
VGS = 4.5 V; ID = 15 A; Tj = 25 °C - - 45 mΩ
VGS = 5 V; ID = 15 A; Tj = 25 °C; - 34 40 mΩ
see Figure 12 and 13
Source-drain diode
VSD source-drain voltage IS = 20 A; VGS = 0 V; Tj = 25 °C; - 0.85 1.2 V
see Figure 16
trr reverse recovery time IS = 20 A; dIS/dt = -100 A/μs; - 45 - ns
Qr recovered charge VGS = -10 V; VDS = 30 V; - 25 - nC
Tj = 25 °C
Dynamic characteristics
QG(tot) total gate charge ID = 15 A; VDS = 44 V; VGS = 5 V; - 11 - nC
QGS gate-source charge Tj = 25 °C; see Figure 14 - 2 - nC
QGD gate-drain charge - 5 - nC
Ciss input capacitance VGS = 0 V; VDS = 25 V; - 765 1020 pF
Coss output capacitance f = 1 MHz; Tj = 25 °C; - 123 148 pF
see Figure 15
Crss reverse transfer - 71 97 pF
capacitance
td(on) turn-on delay time VDS = 30 V; RL = 2.2 Ω; - 17 - ns
tr rise time VGS = 5 V; RG(ext) = 10 Ω; - 93 - ns
Tj = 25 °C
td(off) turn-off delay time - 35 - ns
tf fall time - 72 - ns

BUK9Y40-55B_3 © Nexperia B.V. 2017. All rights reserved

Product data sheet Rev. 03 — 22 February 2008 5 of 12


Nexperia BUK9Y40-55B
N-channel TrenchMOS logic level FET

03np10 03np09
60 50
VGS (V) = 10
6.0
ID RDSon
5.0
(A) (mΩ)
4.4
40 4.2 40
4.0
3.8
3.6
3.4
20 30
3.2

3.0
2.8
2.6
0 20
0 2 4 6 8 10 0 5 10 15
VDS (V) VGS (V)

T j = 25 °C; t p = 300 ȝs T j = 25 °C; ID = 15 A

Fig 6. Output characteristics: drain current as a Fig 7. Drain-source on-state resistance as a function
function of drain-source voltage; typical values of gate-source voltage; typical values

03ng53 03np07
10−1 30
ID
(A) gfs
(S)
10−2
25

min typ max


10−3

20

10−4

15
10−5

10−6 10
0 1 2 3 0 4 8 12 16
VGS (V) ID (A)

T j = 25 °C;VDS = VGS T j = 25 °C;VDS = 25V

Fig 8. Sub-threshold drain current as a function of Fig 9. Forward transconductance as a function of


gate-source voltage drain current; typical values

BUK9Y40-55B_3 © Nexperia B.V. 2017. All rights reserved

Product data sheet Rev. 03 — 22 February 2008 6 of 12


Nexperia BUK9Y40-55B
N-channel TrenchMOS logic level FET

03np08 03ng52
20 2.5
VGS(th)
ID
(V)
(A)
2.0
15 max

1.5
typ
10

1.0 min

5
Tj = 175 °C Tj = 25 °C 0.5

0 0
0 1 2 3 4 −60 0 60 120 180
VGS (V) Tj (°C)

VDS = 25V ID = 1 m A;VDS = VGS

Fig 10. Transfer characteristics: drain current as a Fig 11. Gate-source threshold voltage as a function of
function of gate-source voltage; typical values junction temperature

03np11 03nb25
90 2.4

3.0 3.2 3.4 3.6 3.8 5.0


RDSon a
(mΩ)

60 1.6

VGS (V) = 10
30 0.8

0 0
0 20 40 60 −60 0 60 120 180
ID (A) Tj (°C)

T j = 25 °C R DSon
a=
R DSon (25°C )

Fig 12. Drain-source on-state resistance as a function Fig 13. Normalized drain-source on-state resistance
of drain current; typical values factor as a function of junction temperature

BUK9Y40-55B_3 © Nexperia B.V. 2017. All rights reserved

Product data sheet Rev. 03 — 22 February 2008 7 of 12


Nexperia BUK9Y40-55B
N-channel TrenchMOS logic level FET

03np06 03np12
5 1400
VGS
C
(V) VDS = 14 V (pF)
4
VDS = 44 V 1050
Ciss

700

2
Coss
350
1
Crss

0 0
0 5 10 15 10−1 1 10 102
QG (nC) VDS (V)

T j = 25 °C; ID = 15 A VGS = 0V ; f = 1 M H z

Fig 14. Gate-source voltage as a function of gate Fig 15. Input, output and reverse transfer capacitances
charge; typical values as a function of drain-source voltage; typical
values

03np05
80

IS
(A)

60

40
Tj = 175 °C

Tj = 25 °C
20

0
0 0.5 1.0 1.5
VSD (V)

VGS = 0V

Fig 16. Source current as a function of source-drain voltage; typical values

BUK9Y40-55B_3 © Nexperia B.V. 2017. All rights reserved

Product data sheet Rev. 03 — 22 February 2008 8 of 12


Nexperia BUK9Y40-55B
N-channel TrenchMOS logic level FET

7. Package outline

Plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669

A2
E A C
b2 c2 E1

L1 b3
mounting
b4
base

D1

H D

L2
1 2 3 4
X
e b w M A c

1/2 e

A (A 3)
A1 C

L
detail X
y C

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)


D1(1) θ
UNIT A A1 A2 A3 b b2 b3 b4 c c2 D (1) E(1) E1(1) e H L L1 L2 w y
max

mm 1.20 0.15 1.10 0.50 4.41 2.2 0.9 0.25 0.30 4.10 5.0 3.3 6.2 0.85 1.3 1.3 8°
0.25 4.20 1.27 0.25 0.1
1.01 0.00 0.95 0.35 3.62 2.0 0.7 0.19 0.24 3.80 4.8 3.1 5.8 0.40 0.8 0.8 0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN


ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

04-10-13
SOT669 MO-235
06-03-16

Fig 17. Package outline SOT669 (LFPAK)

BUK9Y40-55B_3 © Nexperia B.V. 2017. All rights reserved

Product data sheet Rev. 03 — 22 February 2008 9 of 12


Nexperia BUK9Y40-55B
N-channel TrenchMOS logic level FET

8. Revision history
Table 7. Revision history
Document ID Release date Data sheet status Change notice Supersedes
BUK9Y40-55B_3 20080222 Product data sheet - BUK9Y40-55B_2
Modifications: • The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
BUK9Y40-55B_2 20060411 Product data sheet - BUK9Y40_55B-01
BUK9Y40_55B-01 20040528 Product data sheet - -

BUK9Y40-55B_3 © Nexperia B.V. 2017. All rights reserved

Product data sheet Rev. 03 — 22 February 2008 10 of 12


Nexperia BUK9Y40-55B
N-channel TrenchMOS logic level FET

9. Legal information

9.1 Data sheet status


Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.

9.2 Definitions damage. Nexperia accepts no liability for inclusion and/or use of
Nexperia products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in Applications — Applications that are described herein for any of these
modifications or additions. Nexperia does not give any products are for illustrative purposes only. Nexperia makes no
representations or warranties as to the accuracy or completeness of representation or warranty that such applications will be suitable for the
information included herein and shall have no liability for the consequences of specified use without further testing or modification.
use of such information. Quick reference data — The Quick reference data is an extract of the
Short data sheet — A short data sheet is an extract from a full data sheet product data given in the Limiting values and Characteristics sections of this
with the same product type number(s) and title. A short data sheet is intended document, and as such is not complete, exhaustive or legally binding.
for quick reference only and should not be relied upon to contain detailed and Limiting values — Stress above one or more limiting values (as defined in
full information. For detailed and full information see the relevant full data the Absolute Maximum Ratings System of IEC 60134) may cause permanent
sheet, which is available on request via the local Nexperia sales damage to the device. Limiting values are stress ratings only and operation of
office. In case of any inconsistency or conflict with the short data sheet, the the device at these or any other conditions above those given in the
full data sheet shall prevail. Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.

9.3 Disclaimers Terms and conditions of sale — Nexperia products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nexperia.com/profile/terms, including those pertaining to warranty,
General — Information in this document is believed to be accurate and
intellectual property rights infringement and limitation of liability, unless
reliable. However, Nexperia does not give any representations or
explicitly otherwise agreed to in writing by Nexperia. In case of
warranties, expressed or implied, as to the accuracy or completeness of such
any inconsistency or conflict between information in this document and such
information and shall have no liability for the consequences of use of such
terms and conditions, the latter will prevail.
information.
No offer to sell or license — Nothing in this document may be interpreted or
Right to make changes — Nexperia reserves the right to make
construed as an offer to sell products that is open for acceptance or the grant,
changes to information published in this document, including without
conveyance or implication of any license under any copyrights, patents or
limitation specifications and product descriptions, at any time and without
other industrial or intellectual property rights.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — Nexperia products are not designed, 9.4 Trademarks
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or Notice: All referenced brands, product names, service names and trademarks
malfunction of a Nexperia product can reasonably be expected are the property of their respective owners.
to result in personal injury, death or severe property or environmental

10. Contact information


For additional information, please visit: http://www.nexperia.com
For sales office addresses, send an email to: salesaddresses@nexperia.com

BUK9Y40-55B_3 © Nexperia B.V. 2017. All rights reserved

Product data sheet Rev. 03 — 22 February 2008 11 of 12


Nexperia BUK9Y40-55B
N-channel TrenchMOS logic level FET

11. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Thermal characteristics . . . . . . . . . . . . . . . . . . 4
6 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10
9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
9.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
10 Contact information. . . . . . . . . . . . . . . . . . . . . 11
11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

© Nexperia B.V. 2017. All rights reserved


For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 22 February 2008

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