SN54LVC08A, SN74LVC08A

SCAS283U – JANUARY 1993 – REVISED MARCH 2024

SNx4LVC08A Quadruple 2-Input Positive-AND Gates

1 Features 3 Description
• Latch-up performance exceeds 250mA The SN54LVC08A quadruple 2-input positive-AND
per JESD 17 gate is designed for 2.7V to 3.6V VCC operation,
• ESD protection exceeds JESD 22 and the SN74LVC08A quadruple 2-input positive-AND
– 2000V Human-Body Model (A114-A) gate is designed for 1.65V to 3.6V VCC operation.
– 1000V Charged-Device Model (C101) The SNx4LVC08A devices perform the Boolean
– On products compliant to MIL-PRF-38535,
function Y + A • B or Y + A ) B in positive logic.
All parameters are tested unless otherwise
noted. On all other products, production Inputs can be driven from either 3.3V or 5V devices.
processing does not necessarily include testing This feature allows the use of these devices as
of all parameters. translators in a mixed 3.3V/5V system environment.
• SN74LVC08A operates from 1.65V to 3.6V
Device Information
• SN54LVC08A operates from 2.0V to 3.6V
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
• SNx4LVC08A specified from –40°C to +85°C and
BQA (WQFN, 14) 3mm × 2.5mm 3mm × 2.5mm
–40°C to +125°C D (SOIC, 14) 8.65mm × 6mm 8.65 mm × 3.91 mm
• SN54LVC08A specified from –55°C to +125°C DB (SSOP, 14) 6.2mm × 7.8mm 6.20 mm × 5.30 mm
• Inputs accept voltages to 5.5V NS (SOP, 14) 10.2mm × 7.8mm 10.30 mm × 5.30 mm
• Max tpd of 4.1ns at 3.3V SNx4LVC08A PW (TSSOP, 14) 5mm × 4.4mm 5.00 mm × 4.40 mm
• Typical VOLP (output ground bounce) RGY (VQFN, 14) 3.5mm × 3.5mm 3.50 mm × 3.50 mm
<0.8V at VCC = 3.3V, TA = 25°C FK (LCCC, 20) 8.9mm x 8.9mm 8.89 mm × 8.89 mm
• Typical VOHV (output VOH undershoot) J (CDIP, 14) 19.55mm x 7.9mm 19.55 mm x 6.7mm
>2V at VCC = 3.3V, TA = 25°C W (CFP, 14) 9.21mm x 9mm 9.21mm x 6.28mm

2 Applications (1) For more information, see Section 11.

(2) The package size (length × width) is a nominal value and
• Servers includes pins, where applicable.
• LED Displays (3) The body size (length × width) is a nominal value and does
• Network Switches not include pins.
• I/O Expanders
A
• Base Station Processor Board Y
B
Logic Diagram, Each Gate
(Positive Logic)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7 Detailed Description...................................................... 11
2 Applications..................................................................... 1 7.1 Overview................................................................... 11
3 Description.......................................................................1 7.2 Functional Block Diagram......................................... 11
4 Pin Configuration and Functions...................................3 7.3 Feature Description...................................................11
5 Specifications.................................................................. 5 7.4 Device Functional Modes..........................................12
5.1 Absolute Maximum Ratings........................................ 5 8 Application and Implementation.................................. 13
5.2 ESD Ratings............................................................... 5 8.1 Application Information............................................. 13
5.3 Recommended Operating Conditions, 8.2 Typical Application.................................................... 13
SN54LVC08A................................................................ 5 8.3 Layout....................................................................... 14
5.4 Recommended Operating Conditions, 9 Device and Documentation Support............................16
SN74LVC08A................................................................ 6 9.1 Documentation Support (Analog)..............................16
5.5 Thermal Information....................................................6 9.2 Receiving Notification of Documentation Updates....16
5.6 Electrical Characteristics, SN54LVC08A.................... 7 9.3 Support Resources................................................... 16
5.7 Electrical Characteristics, SN74LVC08A.................... 7 9.4 Trademarks............................................................... 16
5.8 Switching Characteristics, SN54LVC08A....................8 9.5 Electrostatic Discharge Caution................................16
5.9 Switching Characteristics, SN74LVC08A....................8 9.6 Glossary....................................................................16
5.10 Operating Characteristics......................................... 8 10 Revision History.......................................................... 16
5.11 Typical Characteristics.............................................. 9 11 Mechanical, Packaging, and Orderable
6 Parameter Measurement Information.......................... 10 Information.................................................................... 18

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4 Pin Configuration and Functions

VCC
1A
1A 1 14 VCC
1B 2 13 4B 1 14
1Y 3 12 4A 1B 2 13 4B
2A 4 11 4Y 1Y 3 12 4A
2B 5 10 3B 2A 4 11 4Y
2Y 6 9 3A 2B 5 10 3B
GND 7 8 3Y 2Y 6 9 3A
7 8
Figure 4-1. D, DB, NS, J, W, or PW Package 14-Pin

GND

3Y
SOIC, SSOP, SOP, CDIP, or TSSOP (Top View)
Figure 4-2. BQA or RGY Package 14-Pin WQFN or
VQFN (Top View)

VCC
NC
1B
1A

4B
3 2 1 20 19
1Y 4 18 4A
NC 5 17 NC
2A 6 16 4Y
NC 7 15 NC
2B 8 14 3B
9 10 11 12 13
GND
NC
2Y

3Y
3A

Figure 4-3. FK Package 20-Pin LCCC (Top View)

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Table 4-1. Pin Functions

PIN
SOIC,
SSOP, SOP,
CDIP, TYPE DESCRIPTION
NAME LCCC
TSSOP,
VQFN,WQF
N
1A 1 2 I Channel 1 input A
1B 2 3 I Channel 1 input B
1Y 3 4 O Channel 1 output
2A 4 6 I Channel 2 input A
2B 5 8 I Channel 2 input B
2Y 6 9 O Channel 2 output
GND 7 10 Ground Ground
3Y 8 12 O Channel 3 output
3A 9 13 I Channel 3 input A
3B 10 14 I Channel 3 input B
4Y 11 16 O Channel 4 output
4A 12 18 I Channel 4 input A
4B 13 19 I Channel 4 input B
VCC 14 20 Power Positive supply
The thermal pad can be connected to GND or left floating. Do not connect to any
Thermal Information(1) —
other signal or supply.
1
5
7
NC(2) — — No connect
11
15
17

(1) For BQA package only.

(2) NC – No internal connection

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 6.5 V
VI Input voltage(2) –0.5 6.5 V
VO Output voltage(2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
Ptot Power dissipation(4) (5) TA = –40°C to +125°C 500 mW
TJ Junction temperature –65 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.
(4) For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K.
(5) For the DB, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5 mW/K.

5.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 V
Machine Model (MM) A115-A 200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions, SN54LVC08A

over operating free-air temperature range (unless otherwise noted)(1)
SN54LVC08A
–55°C to +125°C UNIT
MIN MAX
Operating 2 3.6
VCC Supply voltage V
Data retention only 1.5
VIH High-level input voltage VCC = 2.7V to 3.6V 2 V
VIL Low-level input voltage VCC = 2.7V to 3.6V 0.8 V
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 2.7V –12
IOH High-level output current mA
VCC = 3V –24
VCC = 2.7V 12
IOL Low-level output current mA
VCC = 3V 24
Δt/Δv Input transition rise or fall rate 8 ns/V

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.

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5.4 Recommended Operating Conditions, SN74LVC08A

See(1)
SN74LVC08A
TA = 25°C –40°C to +85°C –40°C to +125°C UNIT
MIN MAX MIN MAX MIN MAX
Operating 1.65 3.6 1.65 3.6 1.65 3.6
VCC Supply voltage V
Data retention only 1.5 1.5 1.5
VCC = 1.65V to 1.95V 0.65 × VCC 0.65 × VCC 0.65 × VCC
High-level
VIH VCC = 2.3V to 2.7V 1.7 1.7 1.7 V
input voltage
VCC = 2.7V to 3.6V 2 2 2
VCC = 1.65V to 1.95V 0.35 × VCC 0.35 × VCC 0.35 × VCC
Low-level
VIL VCC = 2.3V to 2.7V 0.7 0.7 0.7 V
input voltage
VCC = 2.7V to 3.6V 0.8 0.8 0.8
VI Input voltage 0 5.5 0 5.5 0 5.5 V
VO Output voltage 0 VCC 0 VCC 0 VCC V
VCC = 1.65V –4 –4 –4

High-level VCC = 2.3V –8 –8 –8

IOH mA
output current VCC = 2.7 V –12 –12 –12
VCC = 3V –24 –24 –24
VCC = 1.65V 4 4 4

Low-level VCC = 2.3V 8 8 8

IOL mA
output current VCC = 2.7V 12 12 12
VCC = 3V 24 24 24
Δt/Δv Input transition rise or fall rate 8 8 8 ns/V

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.

5.5 Thermal Information

SN74LVC08A
BQA D DB NS PW RGY
THERMAL METRIC(1) UNIT
(WQFN) (SOIC) (SSOP) (SO) (TSSOP) (LCCC)
14 PINS 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 102.3 98.6 112.8 95.1 127.7 51.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 96.8 56.0 65.3 52.7 56.0 56.6 °C/W
RθJB Junction-to-board thermal resistance 70.9 53.3 60.2 53.9 69.5 27.5 °C/W
ψJT Junction-to-top characterization parameter 16.6 16.4 25.3 17.9 8.9 4.5 °C/W
Junction-to-board characterization
ψJB 70.9 53.0 59.6 53.6 68.9 27.7 °C/W
parameter
RθJC(bot) Junction-to-case (bottom) thermal resistance 50.1 — — — — 19.1 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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5.6 Electrical Characteristics, SN54LVC08A

over recommended operating free-air temperature range (unless otherwise noted)
SN54LVC08A
PARAMETER TEST CONDITIONS VCC –55°C to +125°C UNIT
MIN TYP(1) MAX
IOH = –100 μA 2.7V to 3.6V VCC – 0.2
2.7V 2.2
VOH IOH = –12 mA V
3V 2.4
IOH = –24 mA 3V 2.2
IOL = 100 μA 2.7V to 3.6V 0.2
VOL IOL = 12 mA 2.7V 0.4 V
IOL = 24 mA 3V 0.55
II VI = 5.5 V or GND 3.6V ±5 μA
ICC VI = VCC or GND, IO = 0 3.6V 10 μA
ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND 2.7V to 3.6V 500 μA
Ci VI = VCC or GND 3.3V 5 pF

(1) TA = 25°C

5.7 Electrical Characteristics, SN74LVC08A

over recommended operating free-air temperature range (unless otherwise noted)
SN74LVC08A
PARAMETER TEST CONDITIONS VCC TA = 25°C –40°C to +85°C –40°C to +125°C UNIT
MIN TYP MAX MIN MAX MIN MAX
IOH = –100 μA 1.65V to 3.6V VCC – 0.2 VCC – 0.2 VCC – 0.3
IOH = –4 mA 1.65V 1.29 1.2 1.05
IOH = –8 mA 2.3V 1.9 1.7 1.55
VOH V
2.7V 2.2 2.2 2.05
IOH = –12 mA
3V 2.4 2.4 2.25
IOH = –24 mA 3V 2.3 2.2 2
IOL = 100 μA 1.65V to 3.6V 0.1 0.2 0.3
IOL = 4 mA 1.65V 0.24 0.45 0.6
VOL IOL = 8 mA 2.3V 0.3 0.7 0.75 V
IOL = 12 mA 2.7V 0.4 0.4 0.6
IOL = 24 mA 3V 0.55 0.55 0.8
II VI = 5.5 V or GND 3.6V ±1 ±5 ±20 μA
ICC VI = VCC or GND, IO = 0 3.6V 1 10 40 μA
One input at VCC – 0.6 V,
ΔICC 2.7V to 3.6V 500 500 5000 μA
Other inputs at VCC or GND
Ci VI = VCC or GND 3.3V 5 pF

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5.8 Switching Characteristics, SN54LVC08A

over recommended operating free-air temperature range (unless otherwise noted) (see Load Circuit and Voltage Waveforms)
SN54LVC08A
FROM TO –55°C to
PARAMETER VCC UNIT
(INPUT) (OUTPUT) +125°C
MIN MAX
2.7V 4.8
tpd A or B Y ns
3.3V ± 0.3V 1 4.1

5.9 Switching Characteristics, SN74LVC08A

over recommended operating free-air temperature range (unless otherwise noted) (see Load Circuit and Voltage Waveforms)
SN74LVC08A
FROM TO –40°C to –40°C to
PARAMETER VCC TA = 25°C UNIT
(INPUT) (OUTPUT) +85°C +125°C
MIN TYP MAX MIN MAX MIN MAX
1.8V ± 0.15V 1 5 9.3 1 9.8 1 11.3
2.5V ± 0.2V 1 2.9 6.4 1 6.9 1 9
tpd A or B Y ns
2.7V 1 3 4.6 1 4.8 1 6
3.3V ± 0.3V 1 2.6 3.9 1 4.1 1 5.5
tsk(o) 3.3V ± 0.3V 1 1.5 ns

5.10 Operating Characteristics

TA = 25°C
TEST
PARAMETER VCC TYP UNIT
CONDITIONS
1.8 V 7
Cpd Power dissipation capacitance per gate f = 10 MHz 2.5 V 9.8 pF
3.3 V 10

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5.11 Typical Characteristics

14 10
VCC = 3 V, VCC = 3 V,
TA = 25°C TA = 25°C
12

tpd – Propagation Delay Time – ns

One Output Switching
tpd – Propagation Delay Time – ns

One Output Switching

Four Outputs Switching 8 Four Outputs Switching
Eight Outputs Switching Eight Outputs Switching
10

8 6

6
4
4

2 2
0 50 100 150 200 250 300 0 50 100 150 200 250 300
CL – Load Capacitance – pF CL – Load Capacitance – pF
Figure 5-1. Propagation Delay (Low to High Figure 5-2. Propagation Delay (High to Low
Transition) Transition)
vs Load Capacitance vs Load Capacitance

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6 Parameter Measurement Information

Load Circuit and Voltage Waveforms

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
RL tPLZ/tPZL VLOAD
(see Note A)
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL VD
VI tr/tf
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V
2.7 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V
3.3 V ± 0.3 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V

VI
Timing Input VM
0V
tw

VI tsu th
VI
Input VM VM
Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
Output
VOH VLOAD/2
Waveform 1
Output VM VM VM
S1 at VLOAD VOL + VD
VOL (see Note B) VOL
tPLH tPZH tPHZ
tPHL
VOH Output
VOH
VM VM Waveform 2 VOH - VD
Output VM
S1 at GND
VOL ≈0 V
(see Note B)
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

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7 Detailed Description
7.1 Overview
The SN74LVC08 device contains four 2-input positive AND gate device and performs the Boolean function Y = A
× B. This device is useful when multiple AND function is used in the system.
7.2 Functional Block Diagram
A
Y
B
Figure 7-1. Logic Diagram, Each Gate (Positive Logic)

7.3 Feature Description

7.3.1 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and
damage due to over-current. The electrical and thermal limits defined the in the Section 5.1 must be followed at
all times.
7.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modelled as a resistor in parallel with the input
capacitance given in the Section 5.6 and Section 5.7. The worst case resistance is calculated with the maximum
input voltage, given in the Section 5.1, and the maximum input leakage current, given in theSection 5.6 and
Section 5.7, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Section 5.3 and Section
5.4 to avoid excessive currents and oscillations. If a slow or noisy input signal is required, a device with a
Schmitt-trigger input should be utilized to condition the input signal prior to the standard CMOS input.
7.3.3 Clamp Diodes
The inputs to this device have negative clamping diodes. The outputs to this device have both positive and
negative clamping diodes as shown in Figure 7-2.

CAUTION
Voltages beyond the values specified in the Section 5.1 table can cause damage to the device.
The input negative-voltage and output voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.

VCC
Device

Input Logic Output

-IIK -IOK

GND

Figure 7-2. Electrical Placement of Clamping Diodes for Each Input and Output

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7.3.4 Over-voltage Tolerant Inputs

Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Section 5.1.
7.4 Device Functional Modes
Table 7-1 lists the functional modes for the SN54LVC08A and SN74LVC08A devices.
Table 7-1. Truth Table
INPUTS OUTPUT
A B Y
L L L
L H L
H L L
H H H

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

The SN74LVC08A is used to drive CMOS device and used for implementing AND logic. The LVC family can
support current drive of about 24 mA at 3-V VCC. The inputs for SN74LVC08A are 5.5-V tolerant allowing it to
translate down to VCC.
8.2 Typical Application
A
Y
R
B C

Figure 8-1. Three Input AND Gate Implementation and Driving LED

8.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because
it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads
so routing and load conditions should be considered to prevent ringing.
8.2.2 Detailed Design Procedure
SN74LVC08A contains four AND gates in one package which can be used for individual AND function or to
implement complex Boolean logic. Figure 8-1 shows an example of implementing 3input AND function. AB are
inputs for AND gate which are connected to another AND gate. Z= A × B × C. SN74LVC08A support high drive
current of 24 mA which can be used to drive LEDs of even Drive low current signal FETs, an example is shown
in Figure 8-1 TI recommends to use a series resistance to limit the current. If VCC is 3 V, and LED current should
be 10 mA, and the forward-voltage of LED is 2.5 V, then R as shown in Figure 8-1 is calculated using Equation
1:

R = (VCC – VLED) / I (1)

R = (3 – 2.5) / 0.01 = 50 Ω

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8.2.3 Application Curves

100 60
TA = 25°C, VCC = 3 V, TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V, 40 VIH = 3 V, VIL = 0 V,
80 All Outputs Switching All Outputs Switching
20
60
0
I OL – mA

I OH – mA
40 –20

–40
20
–60
0
–80

–20 –100
–0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 –1 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VOL – V VOH – V

Figure 8-2. Output Drive Current (IOL) Figure 8-3. Output Drive Current (IOH)
vs LOW-level Output Voltage (VOL) vs HIGH-level Output Voltage (VOH)

Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table.
The VCC pin must have a good bypass capacitor to prevent power disturbance. TI recommends to use a 0.1-µF
capacitor. It is ok to parallel multiple bypass capacitors to reject different frequencies of noise. 0.1-µF and 1-µF
capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
8.3 Layout
8.3.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 8-4 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient.
Even low data rate digital signals can have high frequency signal components due to fast edge rates. When
a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the
change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. Figure 8-5 shows progressively better techniques of rounding corners. Only the last example
(BEST) maintains constant trace width and minimizes reflections.

14 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: SN54LVC08A SN74LVC08A

 SN54LVC08A, SN74LVC08A
www.ti.com SCAS283U – JANUARY 1993 – REVISED MARCH 2024

8.3.2 Layout Examples

GND VCC

Recommend GND flood fill for

improved signal isolation, noise Bypass capacitor
reduction, and thermal dissipation placed close to
0.1 F the device

1A 1 14 VCC
Unused inputs
1B 2 13 4B tied to VCC
1Y 3 12 4A
Unused output
2A 4 11 4Y
left floating
2B 5 10 3B
2Y 6 9 3A
Avoid 90°
corners for GND 7 8 3Y
signal lines

Figure 8-4. Example Layout

WORST BETTER BEST

2W

1W min.

Figure 8-5. Trace Example

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15

Product Folder Links: SN54LVC08A SN74LVC08A
SN54LVC08A, SN74LVC08A
SCAS283U – JANUARY 1993 – REVISED MARCH 2024 www.ti.com

9 Device and Documentation Support

9.1 Documentation Support (Analog)
9.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
9.1.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 9-1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER ORDER NOW
DOCUMENTS SOFTWARE COMMUNITY
SN54LVC08A Click here Click here Click here Click here Click here
SN74LVC08A Click here Click here Click here Click here Click here

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.3.1 Community Resources
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision T (July 2019) to Revision U (March 2024) Page
• Updated the structural layout of data sheet .......................................................................................................1
• Added BQA package to Device Information table.............................................................................................. 1
• Added BQA package to Pin Configuration and Functions section..................................................................... 3
• Removed Machine Model from Features section and ESD Ratings table..........................................................5

16 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: SN54LVC08A SN74LVC08A

 SN54LVC08A, SN74LVC08A
www.ti.com SCAS283U – JANUARY 1993 – REVISED MARCH 2024

• Added BQA package to Thermal Information table ........................................................................................... 6

• Updated Layout Example ................................................................................................................................ 15

Changes from Revision S (August 2015) to Revision T (July 2019) Page

• Changed the order and content of the Features list .......................................................................................... 1
• Deleted Ioff throughout data sheet...................................................................................................................... 1
• Deleted Device Options table, see Mechanical, Packaging, and Orderable Information at the end of the
data sheet...........................................................................................................................................................1
• Added VO > VCC to Output clamp current...........................................................................................................5
• Changed MAX value for Output clamp current, IOK and Continuous output current, IO from: –50 to: ±50......... 5
• Changed values in the Thermal Information table to align with JEDEC standards. .......................................... 6
• Added Balanced High-Drive CMOS Push-Pull Outputs, Standard CMOS Inputs, Clamp Diodes, and Over-
voltage Tolerant Inputs .....................................................................................................................................11
• Deleted sentence referencing "Ioff support......." in the Feature Description section. .......................................11
• Changed Inputs and Output in Truth Table ......................................................................................................12
• Added figure: Trace Example in Layout Examples ..........................................................................................14
• Added Related Documentation and Receiving Notification of Documentation Updates ................................. 16

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17

Product Folder Links: SN54LVC08A SN74LVC08A
SN54LVC08A, SN74LVC08A
SCAS283U – JANUARY 1993 – REVISED MARCH 2024 www.ti.com

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

18 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: SN54LVC08A SN74LVC08A

 PACKAGE OPTION ADDENDUM

www.ti.com 4-Mar-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-9753401Q2A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9753401Q2A
SNJ54LVC
08AFK
5962-9753401QCA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9753401QC Samples
& Green A
SNJ54LVC08AJ
5962-9753401QDA ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9753401QD Samples
& Green A
SNJ54LVC08AW
SN74LVC08AD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A Samples

SN74LVC08ADBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A Samples

SN74LVC08ADBRE4 ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A Samples

SN74LVC08ADE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A Samples

SN74LVC08ADG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A Samples

SN74LVC08ADR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LVC08A Samples

SN74LVC08ADRE4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A Samples

SN74LVC08ADRG3 ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LVC08A Samples

SN74LVC08ADRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A Samples

SN74LVC08ADT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A Samples

SN74LVC08ANSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A Samples

SN74LVC08ANSRE4 ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A Samples

SN74LVC08APW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A Samples

SN74LVC08APWG4 ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A Samples

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 4-Mar-2024

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74LVC08APWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LC08A Samples

SN74LVC08APWRE4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A Samples

SN74LVC08APWRG3 ACTIVE TSSOP PW 14 2000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LC08A Samples

SN74LVC08APWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A Samples

SN74LVC08APWT ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A Samples

SN74LVC08APWTG4 ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A Samples

SN74LVC08ARGYR ACTIVE VQFN RGY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LC08A Samples

SN74LVC08ARGYRG4 ACTIVE VQFN RGY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LC08A Samples

SNJ54LVC08AFK ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9753401Q2A
SNJ54LVC
08AFK
SNJ54LVC08AJ ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9753401QC Samples
& Green A
SNJ54LVC08AJ
SNJ54LVC08AW ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9753401QD Samples
& Green A
SNJ54LVC08AW

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 4-Mar-2024

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54LVC08A, SN74LVC08A :

• Catalog : SN74LVC08A
• Automotive : SN74LVC08A-Q1, SN74LVC08A-Q1
• Enhanced Product : SN74LVC08A-EP, SN74LVC08A-EP
• Military : SN54LVC08A

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 4-Mar-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC08ADBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
SN74LVC08ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC08ADRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.1 8.0 16.0 Q1
SN74LVC08ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC08ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC08ADT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC08ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LVC08APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC08APWRG3 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC08APWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC08APWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC08ARGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 4-Mar-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC08ADBR SSOP DB 14 2000 356.0 356.0 35.0
SN74LVC08ADR SOIC D 14 2500 333.2 345.9 28.6
SN74LVC08ADRG3 SOIC D 14 2500 364.0 364.0 27.0
SN74LVC08ADRG4 SOIC D 14 2500 356.0 356.0 35.0
SN74LVC08ADRG4 SOIC D 14 2500 340.5 336.1 32.0
SN74LVC08ADT SOIC D 14 250 210.0 185.0 35.0
SN74LVC08ANSR SO NS 14 2000 356.0 356.0 35.0
SN74LVC08APWR TSSOP PW 14 2000 356.0 356.0 35.0
SN74LVC08APWRG3 TSSOP PW 14 2000 364.0 364.0 27.0
SN74LVC08APWRG4 TSSOP PW 14 2000 356.0 356.0 35.0
SN74LVC08APWT TSSOP PW 14 250 356.0 356.0 35.0
SN74LVC08ARGYR VQFN RGY 14 3000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 4-Mar-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-9753401Q2A FK LCCC 20 55 506.98 12.06 2030 NA
5962-9753401QDA W CFP 14 25 506.98 26.16 6220 NA
SN74LVC08AD D SOIC 14 50 506.6 8 3940 4.32
SN74LVC08ADE4 D SOIC 14 50 506.6 8 3940 4.32
SN74LVC08ADG4 D SOIC 14 50 506.6 8 3940 4.32
SN74LVC08APW PW TSSOP 14 90 530 10.2 3600 3.5
SN74LVC08APWG4 PW TSSOP 14 90 530 10.2 3600 3.5
SNJ54LVC08AFK FK LCCC 20 55 506.98 12.06 2030 NA
SNJ54LVC08AW W CFP 14 25 506.98 26.16 6220 NA

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

www.ti.com
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 IMPORTANT NOTICE AND DISCLAIMER
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