SN74HC00, SN54HC00

SCLS181H – DECEMBER 1982 – REVISED AUGUST 2021

SNx4HC00 Quadruple 2-Input NAND Gates

1 Features 3 Description
• Buffered inputs This device contains four independent 2-input NAND
• Wide operating voltage range: 2 V to 6 V Gates. Each gate performs the Boolean function
• Wide operating temperature range: Y = A ● B in positive logic.
–40°C to +85°C
• Supports fanout up to 10 LSTTL loads Device Information
• Significant power reduction compared to LSTTL PART NUMBER PACKAGE(1) BODY SIZE (NOM)
logic ICs SN74HC00D SOIC (14) 8.70 mm × 3.90 mm

2 Applications SN74HC00DB SSOP (14) 6.50 mm × 5.30 mm

SN74HC00N PDIP (14) 19.30 mm × 6.40 mm
• Alarm / tamper detect circuit
• S-R latch SN74HC00NS SO (14) 10.20 mm × 5.30 mm
SN74HC00PW TSSOP (14) 5.00 mm × 4.40 mm
SN54HC00FK LCCC (20) 8.90 mm × 8.90 mm
SN54HC00J CDIP (14) 21.30 mm × 7.60 mm
SN54HC00W CFP (14) 9.20 mm × 6.29 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

1 14
1A VCC
2 13
1B 4B
3 12
1Y 4A
4 11
2A 4Y
5 10
2B 3B
6 9
2Y 3A
7 8
GND 3Y

Device Functional Pinout

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 8.4 Standard CMOS Inputs...............................................9
2 Applications..................................................................... 1 8.5 Clamp Diode Structure................................................9
3 Description.......................................................................1 8.6 Device Functional Modes..........................................10
4 Revision History.............................................................. 2 9 Application and Implementation.................................. 11
5 Pin Configuration and Functions...................................3 9.1 Application Information..............................................11
6 Specifications.................................................................. 4 9.2 Typical Application.................................................... 11
6.1 Absolute Maximum Ratings ....................................... 4 10 Power Supply Recommendations..............................14
6.2 ESD Ratings .............................................................. 4 11 Layout........................................................................... 14
6.3 Recommended Operating Conditions ........................4 11.1 Layout Guidelines................................................... 14
6.4 Thermal Information ...................................................5 11.2 Layout Example...................................................... 14
6.5 Electrical Characteristics - Commercial (74xx) .......... 5 12 Device and Documentation Support..........................15
6.6 Electrical Characteristics - Military (54xx) .................. 6 12.1 Documentation Support.......................................... 15
6.7 Switching Characteristics - Commercial (74xx) ......... 6 12.2 Receiving Notification of Documentation Updates..15
6.8 Switching Characteristics - Military (54xx) ................. 6 12.3 Support Resources................................................. 15
6.9 Typical Characteristics................................................ 7 12.4 Trademarks............................................................. 15
7 Parameter Measurement Information............................ 8 12.5 Electrostatic Discharge Caution..............................15
8 Detailed Description........................................................9 12.6 Glossary..................................................................15
8.1 Overview..................................................................... 9 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram........................................... 9 Information.................................................................... 15
8.3 Balanced CMOS Push-Pull Outputs........................... 9

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (January 2021) to Revision H (August 2021) Page
• Increased D and PW package thermal values...................................................................................................5

Changes from Revision F (July 2016) to Revision G (January 2021) Page

• Updated to new data sheet format......................................................................................................................1
• Updated D and PW package thermals to new standards................................................................................... 5

Changes from Revision E (August 2003) to Revision F (July 2016) Page

• Added Applications section, Device Information table, ESD Ratings table, Typical Characteristics section,
Feature Description section, Device Functional Modes, Application and Implementation section, Power
Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.............................................................................. 1
• Added Military Disclaimer to Features list...........................................................................................................1
• Removed Ordering Information table; see POA at the end of data sheet.......................................................... 1
• Changed values in the Thermal Information table to align with JEDEC standards............................................ 5
• Deleted Operating Characteristics table; moved Cpd row to Electrical Characteristics .................................... 5

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5 Pin Configuration and Functions

1B 1A NC VCC 4B
1A 1 14 VCC
1B 2 13 4B 3 2 1 20 19
1Y 4 18 4A
1Y 3 12 4A
2A NC 5 17 NC
4 11 4Y
2B 2A 6 16 4Y
5 10 3B
2Y 6 9 3A NC 7 15 NC
GND 7 8 3Y 2B 8 14 3B
9 10 11 12 13
D, DB, N, NS, PW, J, or W Package 2Y GND NC 3Y 3A
14-Pin SOIC, SSOP, PDIP, SO, TSSOP, CDIP, or CFP FK Package
Top View 20-Pin LCCC
Top View

Table 5-1. Pin Functions

PIN
D, DB, N, I/O DESCRIPTION
NAME NS, PW, J, FK
or W
1A 1 2 Input Channel 1, Input A
1B 2 3 Input Channel 1, Input B
1Y 3 4 Output Channel 1, Output Y
2A 4 6 Input Channel 2, Input A
2B 5 8 Input Channel 2, Input B
2Y 6 9 Output Channel 2, Output Y
3A 9 13 Input Channel 3, Input A
3B 10 14 Input Channel 3, Input B
3Y 8 12 Output Channel 3, Output Y
4A 12 18 Input Channel 4, Input A
4B 13 19 Input Channel 4, Input B
4Y 11 16 Output Channel 4, Output Y
GND 7 10 — Ground
1, 5, 7, 11, 15,
NC — Not internally connected
17
VCC 14 20 — Positive Supply

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
VI < –0.5 V or VI > VCC +
IIK Input clamp current(2) ±20 mA
0.5 V
VO < –0.5 V or VO > VCC +
IOK Output clamp current(2) ±20 mA
0.5 V
IO Continuous output current VO = 0 to VCC ±25 mA
Continuous current through VCC or GND ±50 mA
TJ Junction temperature(3) 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) Guaranteed by design.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/
±2000
JEDEC JS-001(1)
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC
±1000
specification JESD22-C101(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 2 5 6 V
VCC = 2 V 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 V
VCC = 6 V 4.2
VCC = 2 V 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 V
VCC = 6 V 1.8
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
VCC = 2 V 1000
tt Input transition rise and fall time VCC = 4.5 V 500 ns
VCC = 6 V 400
SN54HC00 –55 125
TA Operating free-air temperature °C
SN74HC00 –40 85

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6.4 Thermal Information

SN74HC00
THERMAL METRIC(1) D (SOIC) DB (SSOP) N (PDIP) NS (SOP) PW (TSSOP) UNIT
14 PINS 14 PINS 14 PINS 14 PINS 14 PINS
Junction-to-ambient thermal
RθJA 133.6 108.3 57.5 91.0 151.7 °C/W
resistance
Rθ Junction-to-case (top) thermal
89.0 60.3 45.1 48.8 79.4 °C/W
JC(top) resistance
Junction-to-board thermal
RθJB 89.5 55.7 37.3 49.8 94.7 °C/W
resistance
Junction-to-top characterization
ΨJT 45.5 25 30.3 18.4 25.2 °C/W
parameter
Junction-to-board
ΨJB 89.1 55.2 37.2 49.5 94.1 °C/W
characterization parameter
Rθ Junction-to-case (bottom)
N/A N/A N/A N/A N/A °C/W
JC(bot) thermal resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Electrical Characteristics - Commercial (74xx)

over operating free-air temperature range (unless otherwise noted) (1) (2)
Operating free-air temperature (TA)
PARAMETER TEST CONDITIONS VCC 25°C -40°C to 85°C UNIT
MIN TYP MAX MIN TYP MAX
2V 1.9 1.998 1.9
IOH = -20 µA 4.5 V 4.4 4.499 4.4
High-level VI = VIH
VOH 6V 5.9 5.999 5.9 V
output voltage or VIL
IOH = -4 mA 4.5 V 3.98 4.3 3.84
IOH = -5.2 mA 6V 5.48 5.8 5.34
2V 0.002 0.1 0.1
IOL = 20 µA 4.5 V 0.001 0.1 0.1
Low-level output VI = VIH
VOL 6V 0.001 0.1 0.1 V
voltage or VIL
IOL = 4 mA 4.5 V 0.17 0.26 0.33
IOL = 5.2 mA 6V 0.15 0.26 0.33
Input leakage
II VI = VCC or 0 6V ±0.1 ±100 ±1000 µA
current
VI = VCC
ICC Supply current VI = VCC or 0 6V 2 20 µA
or 0
Input
Ci 2 V to 6 V 3 10 10 pF
capacitance
Power
dissipation
Cpd No load 2 V to 6 V 20 pF
capacitance per
gate

(1) VCCI is the VCC associated with the input port.

(2) VCCO is the VCC associated with the output port.

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6.6 Electrical Characteristics - Military (54xx)

over operating free-air temperature range (unless otherwise noted) (1) (2)
Operating free-air temperature (TA)
PARAMETER TEST CONDITIONS VCC 25°C -55°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX
2V 1.9 1.998 1.9
IOH = -20 µA 4.5 V 4.4 4.499 4.4
High-level VI = VIH
VOH 6V 5.9 5.999 5.9 V
output voltage or VIL
IOH = -4 mA 4.5 V 3.98 4.3 3.7
IOH = -5.2 mA 6V 5.48 5.8 5.2
2V 0.002 0.1 0.1
IOL = 20 µA 4.5 V 0.001 0.1 0.1
Low-level output VI = VIH
VOL 6V 0.001 0.1 0.1 V
voltage or VIL
IOL = 4 mA 4.5 V 0.17 0.26 0.4
IOL = 5.2 mA 6V 0.15 0.26 0.4
Input leakage
II VI = VCC or 0 6V ±0.1 ±100 ±1000 nA
current
VI = VCC
ICC Supply current VI = VCC or 0 6V 2 40 µA
or 0
Input
Ci 2 V to 6 V 3 10 10 pF
capacitance
Power
dissipation
Cpd No load 2 V to 6 V 20 pF
capacitance per
gate

(1) VCCI is the VCC associated with the input port.

(2) VCCO is the VCC associated with the output port.

6.7 Switching Characteristics - Commercial (74xx)

over operating free-air temperature range (unless otherwise noted)
Operating free-air temperature (TA)
PARAMETER FROM TO VCC 25°C –40°C to 85°C UNIT
MIN TYP MAX MIN TYP MAX
2V 45 90 115
tpd Propagation delay A or B Y 4.5 V 9 18 23 ns
6V 8 15 20
2V 38 75 95
tt Transition-time Y 4.5 V 8 15 19 ns
6V 6 13 16

6.8 Switching Characteristics - Military (54xx)

over operating free-air temperature range (unless otherwise noted)
Operating free-air temperature (TA)
PARAMETER FROM TO VCC 25°C –55°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX
2V 45 90 135
tpd Propagation delay A or B Y 4.5 V 9 18 27 ns
6V 8 15 23

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over operating free-air temperature range (unless otherwise noted)

Operating free-air temperature (TA)
PARAMETER FROM TO VCC 25°C –55°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX
2V 38 75 110
tt Transition-time Y 4.5 V 8 15 22 ns
6V 6 13 19

6.9 Typical Characteristics

TA = 25°C

7 0.3
2-V
6 4.5-V
0.25 6-V
VOH Output High Voltage (V)

VOL Output Low Voltage (V)

5
0.2
4
0.15
3
0.1
2

2-V 0.05
1 4.5-V
6-V
0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
IOH Output High Current (mA) IOL Output Low Current (mA)
Figure 6-1. Typical Output Voltage in the High State (VOH) Figure 6-2. Typical Output Voltage in the Low State (VOL)

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7 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.

Test VCC
Point
Input 50% 50%
0V
From Output
tPLH(1) tPHL(1)
Under Test
VOH
CL(1)
Output 50% 50%
VOL
(1) CL includes probe and test-fixture capacitance.
tPHL(1) tPLH(1)
Figure 7-1. Load Circuit for Push-Pull Outputs
VOH
Output 50% 50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-2. Voltage Waveforms Propagation Delays
VCC
90% 90%
Input
10% 10%
0V
tr(1) tf(1)

VOH
90% 90%
Output
10% 10%
VOL
tr(1) tf(1)
(1) The greater between tr and tf is the same as tt.
Figure 7-3. Voltage Waveforms, Input and Output Transition Times

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8 Detailed Description
8.1 Overview
This device contains four independent 2-input NAND gates. Each gate performs the Boolean function Y = A ● B
in positive logic.
8.2 Functional Block Diagram

xA

xY

xB

8.3 Balanced CMOS Push-Pull Outputs

This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
8.4 Standard CMOS Inputs
This device includes standard CMOS inputs. Standard CMOS inputs are high impedance and are typically
modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst
case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the
maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I).
Standard CMOS inputs require that input signals transition between valid logic states quickly, as defined
by the input transition time or rate in the Recommended Operating Conditions table. Failing to meet this
specification will result in excessive power consumption and could cause oscillations. More details can be found
in Implications of Slow or Floating CMOS Inputs.
Do not leave standard CMOS inputs floating at any time during operation. Unused inputs must be terminated
at VCC or GND. If a system will not be actively driving an input at all times, a pull-up or pull-down resistor can
be added to provide a valid input voltage during these times. The resistor value will depend on multiple factors,
however a 10-kΩ resistor is recommended and will typically meet all requirements.
8.5 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Electrical
Placement of Clamping Diodes for Each Input and Output.

CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage
to the device. The input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.

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VCC
Device

+IIK +IOK

Input Logic Output

-IIK -IOK

GND

Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output

8.6 Device Functional Modes

Table 8-1. Function Table
INPUTS OUTPUT
A B Y
H H L
L X H
X L H

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

In this application, the SN74HC00 is used to create an active-low SR latch. The two additional gates can be
used for a second active-low SR latch, individually used for their logic function, or the inputs can be grounded
and both channels left unused. This device is used to drive the tamper indicator LED and provide one bit of
data to the system controller. When the tamper switch outputs LOW, the output Q becomes HIGH. This output
remains HIGH until the system controller addresses the event and sends a LOW signal to the R input which
returns the Q output back to LOW.

9.2 Typical Application

R1 System
R Controller

Tamper Q
Switch S
R2

Tamper
Indicato r

Figure 9-1. Typical Application Diagram

9.2.1 Design Requirements

9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the SN74HC00 plus the maximum static supply current, ICC, listed in Electrical Characteristics and
any transient current required for switching. The logic device can only source as much current as is provided by
the positive supply source. Be sure not to exceed the maximum total current through VCC listed in the Absolute
Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74HC00 plus the maximum supply current, ICC, listed in Electrical Characteristics, and any transient current
required for switching. The logic device can only sink as much current as can be sunk into its ground connection.
Be sure not to exceed the maximum total current through GND listed in the Absolute Maximum Ratings.
The SN74HC00 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all of the
data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to exceed 50
pF.

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The SN74HC00 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and
current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the high state, the
output voltage in the equation is defined as the difference between the measured output voltage and the supply
voltage at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.

CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.

9.2.1.2 Input Considerations

Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74HC00, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ resistor
value is often used due to these factors.
The SN74HC00 has CMOS inputs and thus requires fast input transitions to operate correctly, as defined in
the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power
consumption, and reduction in device reliability.
Refer to the Feature Description section for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Feature Description section for additional information regarding the outputs for this device.

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9.2.2 Detailed Design Procedure

1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the SN74HC00
to one or more of the receiving devices.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in MΩ; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.2.3 Application Curve

Figure 9-2. Application Timing Diagram

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10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
given example layout image.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example

VCC GND
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation

0.1
F Bypass capacitor

1OE VCC placed close to the
device
1 20
1A1 2 19 2OE
2Y4 3 18 1Y1
Unused input
tied to GND 1A2 2A4
4 17

2Y3 5 16 1Y2 Unused output

left floating
1A3 6 GND 15 2A3
2Y2 7 14 1Y3
1A4 8 13 2A2

2Y1 9 12 1Y4
10 11
Avoid 90° GND 2A1
corners for
signal lines

Figure 11-1. Example layout for the SN74HC00 in the RKS Package

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12 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15

Product Folder Links: SN74HC00 SN54HC00
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Jul-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-8403701VCA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8403701VC Samples
& Green A
SNV54HC00J
5962-8403701VDA ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8403701VD Samples
& Green A
SNV54HC00W
84037012A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 84037012A Samples
& Green SNJ54HC
00FK
8403701CA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8403701CA Samples
& Green SNJ54HC00J
8403701DA ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8403701DA Samples
& Green SNJ54HC00W
JM38510/65001B2A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65001B2A
JM38510/65001BCA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65001BCA
JM38510/65001BDA ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65001BDA
M38510/65001B2A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65001B2A
M38510/65001BCA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65001BCA
M38510/65001BDA ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65001BDA
SN54HC00J ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 SN54HC00J Samples
& Green
SN74HC00D OBSOLETE SOIC D 14 TBD Call TI Call TI -40 to 85 HC00
SN74HC00DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC00 Samples

SN74HC00DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC00 Samples

SN74HC00DRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC00 Samples

SN74HC00DT OBSOLETE SOIC D 14 TBD Call TI Call TI -40 to 85 HC00

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Jul-2024

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74HC00N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC00N Samples

SN74HC00NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC00N Samples

SN74HC00NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC00 Samples

SN74HC00PW OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 85 HC00

SN74HC00PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC00 Samples

SN74HC00PWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC00 Samples

SN74HC00PWT OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 85 HC00

SNJ54HC00FK ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 84037012A Samples
& Green SNJ54HC
00FK
SNJ54HC00J ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8403701CA Samples
& Green SNJ54HC00J
SNJ54HC00W ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8403701DA Samples
& Green SNJ54HC00W

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Jul-2024

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54HC00, SN54HC00-SP, SN74HC00 :

• Catalog : SN74HC00, SN54HC00

• Automotive : SN74HC00-Q1, SN74HC00-Q1
• Military : SN54HC00
• Space : SN54HC00-SP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Mar-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC00DBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
SN74HC00DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC00DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC00NSR SO NS 14 2000 330.0 16.4 8.45 10.55 2.5 12.0 16.2 Q1
SN74HC00PWR TSSOP PW 14 2000 330.0 12.4 6.85 5.45 1.6 8.0 12.0 Q1
SN74HC00PWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Mar-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC00DBR SSOP DB 14 2000 356.0 356.0 35.0
SN74HC00DR SOIC D 14 2500 367.0 367.0 38.0
SN74HC00DRG4 SOIC D 14 2500 367.0 367.0 38.0
SN74HC00NSR SO NS 14 2000 356.0 356.0 35.0
SN74HC00PWR TSSOP PW 14 2000 366.0 364.0 50.0
SN74HC00PWRG4 TSSOP PW 14 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Mar-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-8403701VDA W CFP 14 25 506.98 26.16 6220 NA
84037012A FK LCCC 20 55 506.98 12.06 2030 NA
8403701DA W CFP 14 25 506.98 26.16 6220 NA
JM38510/65001B2A FK LCCC 20 55 506.98 12.06 2030 NA
JM38510/65001BDA W CFP 14 25 506.98 26.16 6220 NA
M38510/65001B2A FK LCCC 20 55 506.98 12.06 2030 NA
M38510/65001BDA W CFP 14 25 506.98 26.16 6220 NA
SN74HC00N N PDIP 14 25 506 13.97 11230 4.32
SN74HC00N N PDIP 14 25 506 13.97 11230 4.32
SN74HC00NE4 N PDIP 14 25 506 13.97 11230 4.32
SN74HC00NE4 N PDIP 14 25 506 13.97 11230 4.32
SNJ54HC00FK FK LCCC 20 55 506.98 12.06 2030 NA
SNJ54HC00W W CFP 14 25 506.98 26.16 6220 NA

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

www.ti.com
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
 PACKAGE OUTLINE
PW0014A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
12X 0.65
14
1

2X
5.1 3.9
4.9
NOTE 3

4X (0 -12 )
7
8
0.30
14X
0.17
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220202/B 12/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0014A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

14X (1.5) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220202/B 12/2023
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0014A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

14X (1.5) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220202/B 12/2023
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
D0014A SCALE 1.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

C
6.2
TYP SEATING PLANE
5.8

A PIN 1 ID 0.1 C
AREA
12X 1.27
14
1

8.75 2X
8.55 7.62
NOTE 3

7
8
0.51
14X
4.0 0.31
B 1.75 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.13
SEE DETAIL A
0.25
GAGE PLANE

0.25
0 -8 1.27 0.10
0.40

DETAIL A
TYPICAL

4220718/A 09/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side.
5. Reference JEDEC registration MS-012, variation AB.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(R0.05)
TYP
(5.4)

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220718/A 09/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(5.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:8X

4220718/A 09/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DB0014A SCALE 2.000
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C
PIN 1 INDEX AREA SEATING
PLANE
12X 0.65
14
1

2X
6.5
3.9
5.9
NOTE 3

7
8 0.38
14X
0.22
0.15 C A B
5.6
B
5.0
NOTE 4

0.25
0.09

SEE DETAIL A
2 MAX
0.25
GAGE PLANE

0.95 0.05 MIN

0 -8 0.55

DETAIL A
A 15

TYPICAL

4220762/A 05/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-150.

www.ti.com
 EXAMPLE BOARD LAYOUT
DB0014A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

14X (1.85) SYMM

1 (R0.05) TYP

14X (0.45) 14

SYMM

12X (0.65)

7 8

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4220762/A 05/2024
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DB0014A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

14X (1.85) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220762/A 05/2024
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
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