SN74LVC4245A

ZHCSRE6J – MARCH 1994 – REVISED DECEMBER 2022

SN74LVC4245A 具有三态输出的
八路总线收发器和 3.3V 至 5V 移位器

1 特性 3 说明
• 双向电压转换器 这款 8 位（八路）同相总线收发器包含两个独立的电
• A 端口的电压为 5.5V，B 端口的电压范围为 2.7V 源轨；B 端口具有 VCCB ，设置为 3.3V；A 端口具有
至 3.6V VCCA，设置为 5V。这样可实现从 3.3V 到 5V 的环境
• 控制输入 VIH/VIL 电平以 VCCA 电压为基准 转换，反之亦然。
• 闩锁性能超过 250mA，符合 JESD 17 规范
SN74LVC4245A 器件旨在实现数据总线之间的异步通
• ESD 保护性能超过 JESD 22 规范要求
信。根据方向控制 (DIR) 输入上的逻辑电平，此器件将
– 2000V 人体模型
数据从 A 总线发送至 B 总线，或者将数据从 B 总线发
– 1000V 充电器件模型
送至 A 总线。输出使能 (OE) 输入可用于禁用器件，这
2 应用 样 可 有 效 隔 离 总 线 。 控 制 电 路 （ DIR ， OE ） 由
VCCA 供电。
• ATCA 解决方案
• CPAP 呼吸机 设计人员可将 SN74LVC4245A 器件端子输出切换到正
• 摄像头：监控模拟 常的全 3.3V 或全 5V 20 端子 SN74LVC4245 器件，而
• 化学或气体传感器 无 需 重 新 布 局 电 路 板 。 设 计 人 员 可 使 用
• CT 扫描仪 SN74LVC4245A 器件的 2 到 11 和 14 到 23 引脚的数
• DLP 3D 机器视觉和光纤网络 据路径来与传统的 245 端子输出保持一致。
• 数字标牌
封装信息(1)
• ECG：心电图
器件型号 封装 封装尺寸（标称值）
• 现场变送器：压力传感器和温度传感器
DB (SSOP, 24) 8.20mm × 5.30mm
• 高速数据采集和生成
• HMI（人机界面） DW（SOIC，24） 15.40mm × 7.50mm
SN74LVC4245A
• RF4CE 远程控制 PW（TSSOP，
7.80mm × 4.40mm
24）
• 服务器主板
• 软件定义无线电 (SDR) (1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
• 无线 LAN 卡和数据访问卡 录。
• X 射线：医疗、牙科和行李扫描仪

2
DIR

22
OE

3
A1

21
B1

To Seven Other Channels

简化原理图

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCAS375
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Table of Contents
1 特性................................................................................... 1 8.1 Overview................................................................... 10
2 应用................................................................................... 1 8.2 Functional Block Diagram......................................... 10
3 说明................................................................................... 1 8.3 Feature Description...................................................10
4 Revision History.............................................................. 2 8.4 Device Functional Modes..........................................10
5 Pin Configuration and Functions...................................3 9 Application and Implementation.................................. 11
6 Specifications.................................................................. 4 9.1 Application Information..............................................11
6.1 Absolute Maximum Ratings........................................ 4 9.2 Typical Application.................................................... 11
6.2 Absolute Maximum Ratings........................................ 4 10 Power Supply Recommendations..............................13
6.3 ESD Ratings............................................................... 4 10.1 Power-Up Consideration.........................................13
6.4 Recommended Operating Conditions.........................5 11 Layout........................................................................... 13
6.5 Recommended Operating Conditions.........................5 11.1 Layout Guidelines................................................... 13
6.6 Thermal Information....................................................5 11.2 Layout Example...................................................... 13
6.7 Electrical Characteristics.............................................6 12 Device and Documentation Support..........................14
6.8 Electrical Characteristics.............................................6 12.1 Documentation Support.......................................... 14
6.9 Switching Characteristics............................................7 12.2 接收文档更新通知................................................... 14
6.10 Operating Characteristics......................................... 7 12.3 支持资源..................................................................14
6.11 Typical Characteristics.............................................. 7 12.4 Trademarks............................................................. 14
7 Parameter Measurement Information............................ 8 12.5 Electrostatic Discharge Caution..............................14
7.1 A Port.......................................................................... 8 12.6 术语表..................................................................... 14
7.2 B Port.......................................................................... 9 13 Mechanical, Packaging, and Orderable
8 Detailed Description......................................................10 Information.................................................................... 14

4 Revision History
Changes from Revision I (January 2015) to Revision J (December 2022) Page
• 更新了整个文档中的表格、图和交叉参考的编号格式......................................................................................... 1
• Updated thermals for DB and PW package........................................................................................................5

Changes from Revision H (March 2005) to Revision I (January 2015) Page

• 添加了应用、器件信息 表、引脚功能 表、ESD 等级 表、热性能信息 表、典型特性、特性说明 部分、器件功
能模式、应用和实施 部分、电源相关建议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信
息 部分................................................................................................................................................................ 1
• 删除了订购信息 表.............................................................................................................................................. 1

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5 Pin Configuration and Functions

VCCA 1 24 VCCB

DIR 2 23 NC,VCCB

A1 3 22 OE

A2 4 21 B1

A3 5 20 B2

A4 6 19 B3

A5 7 18 B4

A6 8 17 B5

A7 9 16 B6

A8 10 15 B7

GND 11 14 B8

GND 12 13 GND

Not to scale

图 5-1. DB, DW, or PW Package, SOP, TSSOP, (Top View)

表 5-1. Pin Functions

PIN
TYPE(1) DESCRIPTION
NAME NO.
VCCA 1 — Power supply for side A
DIR 2 I Direction control
A1 3 I/O Transceiver I/O pin
A2 4 I/O Transceiver I/O pin
A3 5 I/O Transceiver I/O pin
A4 6 I/O Transceiver I/O pin
A5 7 I/O Transceiver I/O pin
A6 8 I/O Transceiver I/O pin
A7 9 I/O Transceiver I/O pin
A8 10 I/O Transceiver I/O pin
GND 11 — Ground
GND 12 — Ground
GND 13 — Ground
B8 14 I/O Transceiver I/O pin
B7 15 I/O Transceiver I/O pin
B6 16 I/O Transceiver I/O pin
B5 17 I/O Transceiver I/O pin
B4 18 I/O Transceiver I/O pin
B3 19 I/O Transceiver I/O pin
B2 20 I/O Transceiver I/O pin
B1 21 I/O Transceiver I/O pin
OE 22 I Output Enable
VCCB 23 — Power supply for side B
VCCB 24 — Power supply for side B

(1) I = input, O = output

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range for VCCA = 4.5 V to 5.5 V (unless otherwise noted)(1)
MIN MAX UNIT
VCCA Supply voltage range –0.5 6.5 V
A port(2) –0.5 VCCA + 0.5
VI Input voltage range V
Control inputs –0.5 6
VO Output voltage range A port(2) –0.5 VCCA + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through each VCCA or GND ±100 mA
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under 节 6.4 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) This value is limited to 6 V maximum.

6.2 Absolute Maximum Ratings

over operating free-air temperature range for VCCB = 2.7 V to 3.6 V (unless otherwise noted)(1)
MIN MAX UNIT
VCCB Supply voltage range –0.5 4.6 V
VI Input voltage range B port(2) –0.5 VCCB + 0.5 V
VO Output voltage range B port(2) –0.5 VCCB + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCCB or GND ±100 mA
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under 节 6.4 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) This value is limited to 4.6 V maximum.

6.3 ESD Ratings

PARAMETER DEFINITION VALUE UNIT

Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) 2000 V
V(ESD)
discharge Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) 1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.4 Recommended Operating Conditions

for VCCA = 4.5 V to 5.5 V(1)
MIN MAX UNIT
VCCA Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIA Input voltage 0 VCCA V
VOA Output voltage 0 VCCA V
IOH High-level output current –24 mA
IOL Low-level output current 24 mA
TA Operating free-air temperature –40 85 °C

(1) All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI
application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

6.5 Recommended Operating Conditions

for VCCB = 2.7 V to 3.6 V(1)
MIN MAX UNIT
VCCB Supply voltage 2.7 3.6 V
VIH High-level input voltage VCCB = 2.7 V to 3.6 V 2 V
VIL Low-level input voltage VCCB = 2.7 V to 3.6 V 0.8 V
VIB Input voltage 0 VCCB V
VOB Output voltage 0 VCCB V
VCCB = 2.7 V –12
IOH High-level output current mA
VCCB = 3 V –24
VCCB = 2.7 V 12
IOL Low-level output current mA
VCCB = 3 V 24
TA Operating free-air temperature –40 85 °C

(1) All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI
application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

6.6 Thermal Information

SN74LVC4245A
THERMAL METRIC(1) DB PW UNIT
24 PINS
RθJA Junction-to-ambient thermal resistance 90.7 100.6 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 51.9 44.7 °C/W

RθJB Junction-to-board thermal resistance 49.7 55.8 °C/W

ψJT Junction-to-top characterization parameter 18.8 6.8 °C/W

ψJB Junction-to-board characterization parameter 49.3 55.4 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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6.7 Electrical Characteristics

over recommended operating free-air temperature range for VCCA = 4.5 V to 5.5 V (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCCA MIN TYP(2) MAX UNIT
4.5 V 4.3
IOH = –100 μA
5.5 V 5.3
VOH V
4.5 V 3.7
IOH = –24 mA
5.5 V 4.7
4.5 V 0.2
IOL = 100 μA
5.5 V 0.2
VOL V
4.5 V 0.55
IOL = 24 mA
5.5 V 0.55
II Control inputs VI = VCCA or GND 5.5 V ±1 μA
IOZ (3) A port VO = VCCA or GND 5.5 V ±5 μA
ICCA VI = VCCA or GND, IO = 0 5.5 V 80 μA
ΔICCA (4) One input at 3.4 V, Other inputs at VCCA or GND 5.5 V 1.5 mA
Ci Control inputs VI = VCCA or GND Open 5 pF
Cio A port VO = VCCA or GND 5V 11 pF

(1) VCCB = 2.7 V to 3.6 V.

(2) All typical values are measured at VCC = 5 V, TA = 25°C.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
(4) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or the associated
VCC.

6.8 Electrical Characteristics

over recommended operating free-air temperature range for VCCB = 2.7 V to 3.6 V (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCCB MIN TYP(4) MAX UNIT
IOH = –100 μA 2.7 V to 3.6 V VCC – 0.2
2.7 V 2.2
VOH IOH = –12 mA V
3V 2.4
IOH = –24 mA 3V 2
IOL = 100 μA 2.7 V to 3.6 V 0.2
VOL IOL = 12 mA 2.7 V 0.4 V
IOL = 24 mA 3V 0.55
IOZ (2) B port VO = VCCB or GND 3.6 V ±5 μA
ICCB VI = VCCB or GND, IO = 0 3.6 V 50 μA
One input at VCCB – 0.6
ΔICCB (3) Other inputs at VCCB or GND 2.7 V to 3.6 V 0.5 mA
V,
Cio B port VO = VCCB or GND 3.3 V 11 pF

(1) VCCA = 5 V ± 0.5 V.

(2) For I/O ports, the parameter IOZ includes the input leakage current.
(3) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or the associated
VCC.
(4) All typical values are measured at VCC = 3.3 V, TA = 25°C.

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6.9 Switching Characteristics

over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see 图 7-1 and 图 7-2)
VCCA = 5 V ± 0.5 V,
FROM TO VCCB = 2.7 V to 3.6 V
PARAMETER UNIT
(INPUT) (OUTPUT)
MIN MAX
tPHL 1 6.3
A B ns
tPLH 1 6.7
tPHL 1 6.1
B A ns
tPLH 1 5
tPZL 1 9
OE A ns
tPZH 1 10

tPZL 1 10.3
OE B ns
tPZH 1 9.8
tPLZ 1 7
OE A ns
tPHZ 1 5.8
tPLZ 1 7.7
OE B ns
tPHZ 1 7.8

6.10 Operating Characteristics

VCCA = 4.5 V to 5.5 V, VCCB = 2.7 V to 3.6 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Outputs enabled 39.5
Cpd Power dissipation capacitance per transceiver CL = 0, f = 10 MHz pF
Outputs disabled 5

6.11 Typical Characteristics

14 10
VCC = 3 V, VCC = 3 V,
TA = 25°C TA = 25°C
12
tpd – Propagation Delay Time – ns

One Output Switching

tpd – Propagation Delay Time – ns

One Output Switching

Four Outputs Switching 8 Four Outputs Switching
Eight Outputs Switching Eight Outputs Switching
10

8 6

6
4
4

2 2
0 50 100 150 200 250 300 0 50 100 150 200 250 300
CL – Load Capacitance – pF CL – Load Capacitance – pF
图 6-1. Propagation Delay (Low to High Transition) 图 6-2. Propagation Delay (High to Low Transition)
vs Load Capacitance vs Load Capacitance

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7 Parameter Measurement Information

7.1 A Port
2 × VCC
500 Ω S1 Open
From Output
TEST S1
Under Test GND
tPLH/tPHL Open
CL = 50 pF tPLZ/tPZL 2 × VCC
(see Note A) 500 Ω
tPHZ/tPZH GND

LOAD CIRCUIT

tw

VCC
Input 1.5 V 1.5 V
3V
0V Output 1.5 V 1.5 V
VOLTAGE WAVEFORMS Control
0V
PULSE DURATION
tPZL tPLZ
Output VCC
VCC Waveform 1 50% VCC
1.5 V 1.5 V S1 at 2 × VCC VOL + 0.3 V
Input VOL
0V (see Note B)
tPZH tPHZ
tPLH tPHL Output
VOH Waveform 2 VOH
VOH - 0.3 V
Output 50% VCC 50% VCC S1 at GND 50% VCC
VOL (see Note B) ≈0 V

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.

图 7-1. Load Circuit and Voltage Waveforms

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7.2 B Port
7V
500 Ω S1 Open
From Output
TEST S1
Under Test GND
tPLH/tPHL Open
CL = 50 pF tPLZ/tPZL 7V
(see Note A) 500 Ω
tPHZ/tPZH GND

LOAD CIRCUIT

tw

3V
Input 1.5 V 1.5 V
0V 3V
Output 1.5 V 1.5 V
VOLTAGE WAVEFORMS Control
0V
PULSE DURATION
tPZL tPLZ
Output 3.5 V
3V Waveform 1 1.5 V
1.5 V 1.5 V S1 at 7 V VOL + 0.3 V
Input VOL
0V (see Note B)
tPZH tPHZ
tPLH tPHL
VOH Output VOH
VOH - 0.3 V
Output 1.5 V 1.5 V Waveform 2 1.5 V
VOL S1 at GND ≈0 V
(see Note B)
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.

图 7-2. Load Circuit and Voltage Waveforms

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8 Detailed Description
8.1 Overview
SN74LVC4245A is an 8-bit (octal) noninverting bus transceiver contains two separate supply rails; B port has
VCCB, which is set at 3.3 V, and A port has VCCA, which is set at 5 V. This allows for translation from a 3.3-V to a
5-V environment, and vice versa, designed for asynchronous communication between data buses. The device
transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable ( OE) input can be used to disable the device so the buses are
effectively isolated. The control circuitry (DIR, OE) is powered by VCCA.
8.2 Functional Block Diagram

2
DIR

22
OE

3
A1

21
B1

To Seven Other Channels

8.3 Feature Description
• 24 mA drive at 3-V supply
– Good for heavier loads and longer traces
• Low VIH
– Allows 3.3-V to 5-V translation
8.4 Device Functional Modes
表 8-1. Function Table
INPUTS
OPERATION
OE DIR
L L B data to A bus
L H A data to B bus
H X Isolation

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9 Application and Implementation

备注
以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The SN74LVC4245A device pinout allows the designer to switch to a normal all-3.3-V or all-5-V 20-pin '245
device without board re-layout. The designer uses the data paths for pins 2 – 11 and 14 – 23 of the
SN74LVC4245A to align with the conventional SN74LVC4245 device's pinout. SN74LVC4245A is a high drive
CMOS device that can be used for a multitude of bus interface type applications where output drive or PCB trace
length is a concern.
9.2 Typical Application
5V 3V

VCCA VCCB
DIR
B1
C/System
OE
Logic/LEDs
C or System
B8
Logic A1

A8
GND

图 9-1. Typical Application Schematic

9.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.

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9.2.2 Detailed Design Procedure

1. Recommended Input Conditions:
• For rise time and fall time specifcations, see (Δt/ΔV) in the 节 6.4 table.
• For specified high and low levels, see (VIH and VIL) in the 节 6.4 table.
2. Recommend Output Conditions:
• Load currents should not exceed (IO max) per output and should not exceed (Continuous current through
VCC or GND) total current for the part. These limits are located in the 节 6.1 table.
• Outputs should not be pulled above VCC.
• Series resistors on the output may be used if the user desires to slow the output edge signal or limit the
output current.
9.2.3 Application Curves

100 60
TA = 25°C, VCC = 3 V, TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V, 40 VIH = 3 V, VIL = 0 V,
80 All Outputs Switching All Outputs Switching
20
60
0
I OL – mA

I OH – mA
40 –20

–40
20
–60
0
–80

–20 –100
–0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 –1 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VOL – V VOH – V

图 9-2. Output Drive Current (IOL) 图 9-3. Output Drive Current (IOH)
vs LOW-level Output Voltage (VOL) vs HIGH-level Output Voltage (VOH)

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10 Power Supply Recommendations

10.1 Power-Up Consideration
TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up
sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other
anomalies caused by improperly biased device terminals. Take these precautions to guard against such power-
up problems:
1. Connect ground before any supply voltage is applied.
2. Power up the control side of the device (VCCA for all four of these devices).
3. Tie OE to VCCA with a pullup resistor so that it ramps with VCCA.
4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus),
ramp it with VCCA. Otherwise, keep DIR low.
For more information, refer to the Voltage-Level-Translation Devices application note.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in 图 11-1 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient.
11.2 Layout Example
VCC Input
Unused Input Output Unused Input Output

Input

图 11-1. Layout Diagram

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13

Product Folder Links: SN74LVC4245A
SN74LVC4245A
ZHCSRE6J – MARCH 1994 – REVISED DECEMBER 2022 www.ti.com.cn

12 Device and Documentation Support

12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Voltage-Level-Translation Devices application note
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.6 术语表
TI 术语表 本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: SN74LVC4245A

 PACKAGE OPTION ADDENDUM

www.ti.com 31-Jan-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74LVC4245ADBR ACTIVE SSOP DB 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LJ245A Samples

SN74LVC4245ADBRE4 ACTIVE SSOP DB 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LJ245A Samples

SN74LVC4245ADW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC4245A Samples

SN74LVC4245ADWE4 ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC4245A Samples

SN74LVC4245ADWG4 ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC4245A Samples

SN74LVC4245ADWR ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 LVC4245A Samples

SN74LVC4245ADWRE4 ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC4245A Samples

SN74LVC4245ADWRG4 ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC4245A Samples

SN74LVC4245APW ACTIVE TSSOP PW 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LJ245A Samples

SN74LVC4245APWG4 ACTIVE TSSOP PW 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LJ245A Samples

SN74LVC4245APWR ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LJ245A Samples

SN74LVC4245APWRE4 ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LJ245A Samples

SN74LVC4245APWRG4 ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LJ245A Samples

SN74LVC4245APWT ACTIVE TSSOP PW 24 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LJ245A Samples

SN74LVC4245APWTG4 ACTIVE TSSOP PW 24 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LJ245A Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 31-Jan-2023

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC4245A :

• Enhanced Product : SN74LVC4245A-EP

NOTE: Qualified Version Definitions:

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Dec-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC4245ADBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1
SN74LVC4245ADWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
SN74LVC4245ADWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
SN74LVC4245ADWRG4 SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
SN74LVC4245APWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
SN74LVC4245APWT TSSOP PW 24 250 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Dec-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC4245ADBR SSOP DB 24 2000 356.0 356.0 35.0
SN74LVC4245ADWR SOIC DW 24 2000 350.0 350.0 43.0
SN74LVC4245ADWR SOIC DW 24 2000 364.0 361.0 36.0
SN74LVC4245ADWRG4 SOIC DW 24 2000 350.0 350.0 43.0
SN74LVC4245APWR TSSOP PW 24 2000 356.0 356.0 35.0
SN74LVC4245APWT TSSOP PW 24 250 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Dec-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN74LVC4245ADW DW SOIC 24 25 506.98 12.7 4826 6.6
SN74LVC4245ADWE4 DW SOIC 24 25 506.98 12.7 4826 6.6
SN74LVC4245ADWG4 DW SOIC 24 25 506.98 12.7 4826 6.6
SN74LVC4245APW PW TSSOP 24 60 530 10.2 3600 3.5
SN74LVC4245APW PW TSSOP 24 60 530 10.2 3600 3.5
SN74LVC4245APWG4 PW TSSOP 24 60 530 10.2 3600 3.5
SN74LVC4245APWG4 PW TSSOP 24 60 530 10.2 3600 3.5

Pack Materials-Page 3
 PACKAGE OUTLINE
PW0024A SCALE 2.000
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1

2X
7.9 7.15
7.7
NOTE 3

12
13
0.30
24X
4.5 0.19 1.2 MAX
B
4.3 0.1 C A B
NOTE 4

0.25
GAGE PLANE
0.15
0.05

(0.15) TYP
SEE DETAIL A 0.75
0 -8 0.50
DETAIL A
A 20

TYPICAL

4220208/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0024A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

24X (1.5) SYMM

1 (R0.05) TYP

24X (0.45) 24

22X (0.65)
SYMM

12 13

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4220208/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0024A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

24X (1.5) SYMM

(R0.05) TYP
1
24X (0.45) 24

22X (0.65)
SYMM

12 13

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220208/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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