LM5017

ZHCS812K – JANUARY 2012 – REVISED AUGUST 2021

LM5017 100V、600mA 恒定导通时间同步降压/Fly-Buck™ 稳压器

1 特性 3 描述
• 7.5V 至 100V 宽输入范围 LM5017 是一款 100V、600mA 同步降压稳压器，集成
• 集成式 100V 高侧和低侧开关 了高侧和低侧 MOSFET。LM5017 所采用的恒定导通
• 无需肖特基二极管 时间 (COT) 控制方案无需环路补偿，可提供出色的瞬
• 恒定导通时间控制 态响应，并且可实现超高降压比。导通时间与输入电压
• 无需环路补偿 成反比，因此在整个输入电压范围内，频率几乎保持恒
• 超快瞬态响应 定。高压启动稳压器为 IC 的内部运行以及集成栅极驱
• 接近恒定的运行频率 动器提供了偏置电源。
• 智能峰值电流限制
• 可调节输出电压（以 1.225V 为基准电压） 峰值电流限制电路可防止出现过载情况。欠压锁定
• 精度为 2% 的反馈基准电压 (UVLO) 电路支持对输入欠压阈值和迟滞进行单独编
• 频率可调至 1MHz 程。其他的保护特性包括：热关断和偏置电源欠压锁定
• 可调欠压锁定 (UVLO) (VCC UVLO)。
• 远程关断 LM5017 器件采用 WSON-8 和 HSOP PowerPAD-8 塑
• 热关断 料封装。
• 封装：
– WSON-8 器件信息
器件型号 封装(1) 封装尺寸（标称值）
– SO PowerPAD™-8
SO PowerPAD (8) 4.89mm × 3.90mm
• 使用 WEBENCH® Power Designer 创建定制稳压器 LM5017
设计方案 WSON (8) 4.00mm × 4.00mm

2 应用 (1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 工业可编程逻辑控制器 (PLC)
• 智能电表
• 电信初级侧和次级侧偏置
• 低功耗隔离式直流/直流 (Fly-Buck™)
VIN = 7.5 V...100 V VOUT(SEC)
VIN BST VIN = 7.5 V...100 V
VIN
BST
LM5017 VOUT
SW
LM5017
RON VOUT(PRI)
RON SW

UVLO FB
UVLO FB
VCC
VCC

RTN
RTN

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Copyright © 2018, Texas Instruments Incorporated

典型同步降压应用电路
典型 Fly-Buck 应用电路

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVS783
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Table of Contents
1 特性................................................................................... 1 8 Application and Implementation.................................. 15
2 应用................................................................................... 1 8.1 Application Information............................................. 15
3 描述................................................................................... 1 8.2 Typical Application.................................................... 15
4 Revision History.............................................................. 2 9 Power Supply Recommendations................................25
5 Pin Configuration and Functions...................................3 10 Layout...........................................................................26
6 Specifications.................................................................. 4 10.1 Layout Guidelines................................................... 26
6.1 Absolute Maximum Ratings........................................ 4 10.2 Layout Example...................................................... 26
6.2 ESD Ratings............................................................... 4 11 Device and Documentation Support..........................27
6.3 Recommended Operating Conditions.........................4 11.1 Device Support........................................................27
6.4 Thermal Information....................................................4 11.2 Documentation Support.......................................... 27
6.5 Electrical Characteristics.............................................5 11.3 接收文档更新通知................................................... 28
6.6 Timing Requirements.................................................. 5 11.4 支持资源..................................................................28
6.7 Typical Characteristics................................................ 7 11.5 Trademarks............................................................. 28
7 Detailed Description........................................................9 11.6 静电放电警告...........................................................28
7.1 Overview..................................................................... 9 11.7 术语表..................................................................... 28
7.2 Functional Block Diagram........................................... 9 12 Mechanical, Packaging, and Orderable
7.3 Feature Description...................................................10 Information.................................................................... 29
7.4 Device Functional Modes..........................................14

4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision J (November 2017) to Revision K (August 2021) Page
• 在标题中添加了“同步 Fly-Buck”..................................................................................................................... 1
• 更新了整个文档中的表格、图和交叉参考的编号格式。..................................................................................... 1
• 更新了应用 要点并添加了超链接........................................................................................................................ 1
• Changed Overview ............................................................................................................................................ 9
• Changed Functional Block Diagram .................................................................................................................. 9
• Changed Power Supply Recommendations .................................................................................................... 25
• Updated Related Documentation .....................................................................................................................27

Changes from Revision I (October 2015) to Revision J (November 2017) Page

• Deleted the lead temperature from the Absolute Maximum Ratings table......................................................... 4

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5 Pin Configuration and Functions

RTN 1 8 SW

VIN 2 7 BST
SO
PowePAD-8
UVLO 3 Exp Pad 6 VCC

RON 4 5 FB

图 5-1. DDA Package 8-Pin SO PowerPAD Top View

RTN 1 8 SW

VIN 2 7 BST
WSON-8
UVLO 3 6 VCC
Exp Pad

RON 4 5 FB

图 5-2. NGU Package 8-Pin WSON With Exposed Thermal Pad Top View

表 5-1. Pin Functions

PIN
I/O DESCRIPTION APPLICATION INFORMATION
NO. NAME
1 RTN — Ground Ground connection of the integrated circuit.
2 VIN P Input voltage Operating input range is 7.5 V to 100 V.
Resistor divider from VIN to UVLO to GND programs the undervoltage
detection threshold. An internal current source is enabled when UVLO is
3 UVLO I Undervoltage comparator input
above 1.225 V to provide hysteresis. When UVLO pin is pulled below 0.66
V externally, the regulator is in shutdown mode.
A resistor between this pin and VIN sets the buck switch on-time as a
4 RON I On-time control function of VIN. Minimum recommended on-time is 100 ns at maximum
input voltage.
This pin is connected to the inverting input of the internal regulation
5 FB I Feedback
comparator. The regulation level is 1.225 V.
Output from the internal high-voltage
The internal VCC regulator provides bias supply for the gate drivers and
6 VCC O series pass regulator. Regulated at
other internal circuitry. A 1-μF decoupling capacitor is recommended.
7.6 V.
An external capacitor is required between the BST and SW pins (0.01-μF
7 BST I Bootstrap capacitor ceramic). The BST capacitor is charged by the VCC regulator through an
internal diode when SW is low.
Power switching node. Connect to the output inductor and bootstrap
8 SW P Switching node
capacitor.
Exposed pad must be connected to the RTN pin. Solder to the system
EP — Exposed Pad
ground plane on application board for reduced thermal resistance.

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6 Specifications
6.1 Absolute Maximum Ratings
See (1)
MIN MAX UNIT
VIN, UVLO to RTN –0.3 100 V
SW to RTN –1.5 VIN + 0.3 V
SW to RTN (100-ns transient) –5 VIN + 0.3 V
BST to VCC 100 V
BST to SW 13 V
RON to RTN –0.3 100 V
VCC to RTN –0.3 13 V
FB to RTN –0.3 5 V
Maximum Junction Temperature(2) 150 °C
Storage temperature, Tstg –55 150 °C

(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. 节 6.3 are conditions under which operation of
the device is intended to be functional. For ensured specifications and test conditions, see the 节 6.5. The RTN pin is the GND
reference electrically connected to the substrate.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±750
C101(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN Voltage(1) 7.5 100 V
Operating Junction Temperature(2) –40 125 °C

(1) Recommended Operating Conditions are conditions under the device is intended to be functional. For specifications and test
conditions, see 节 6.5.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

6.4 Thermal Information

LM5017
THERMAL METRIC(1) NGU (WSON) DDA (SO PowerPAD™) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 41.3 41.1 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance 3.2 2.4 °C/W
ΨJB Junction-to-board thermal characteristic parameter 19.2 24.4 °C/W
RθJB Junction-to-board thermal resistance 19.1 30.6 °C/W
RθJCtop Junction-to-case (top) thermal resistance 34.7 37.3 °C/W
ΨJT Junction-to-top thermal characteristic parameter 0.3 6.7 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature
range, unless otherwise stated. VIN = 48 V, unless otherwise stated. See(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC SUPPLY
VCC VCC regulator output VIN = 48 V, ICC = 20 mA 6.25 7.6 8.55 V
ILIM-VCC VCC current limit VIN = 48 V(2) 26 mA
VCC undervoltage lockout
VCC-UV –40°C ≤ TJ ≤ 125°C 4.15 4.5 4.9 V
voltage (VVCC increasing)
VCC-UV-HYS VCC undervoltage hysteresis 300 mV
VCC-LDO VIN – VCC dropout voltage VIN = 9 V, ICC = 20 mA 2.3 V
IOP IIN operating current Non-switching, VFB = 3 V 1.75 mA
ISHD IIN shutdown current VUVLO = 0 V 50 225 µA
SWITCH CHARACTERISTICS
RDS(ON)1 Buck switch RDS(on) ITEST = 200 mA, VBST – VSW = 7 V 0.8 1.8 Ω
RDS(ON)2 Synchronous switch RDS(on) ITEST = 200 mA 0.45 1 Ω
BSTUV Gate drive UVLO VBST − VSW rising 2.4 3 3.6 V
BSTUV-HYS Gate drive UVLO hysteresis 260 mV
CURRENT LIMIT
ILIM -HS Current limit threshold –40°C ≤ TJ ≤ 125°C 0.7 1.02 1.3 A
tRES Current limit response time Time to switch off 150 ns
tOFF1 OFF-time generator (test 1) VFB = 0.1 V, VIN = 48 V 12 µs
tOFF2 OFF-time generator (test 2) VFB = 1 V, VIN = 48 V 2.5 µs
REGULATION AND OVERVOLTAGE COMPARATORS
Internal reference trip point for
VFB FB regulation level 1.2 1.225 1.25 V
switch ON
VFB-OV FB overvoltage threshold Trip point for switch OFF 1.62 V
IFB-BIAS FB bias current 60 nA
UNDERVOLTAGE SENSING FUNCTION
VUVLO-TH UVLO threshold Voltage at UVLO rising 1.19 1.225 1.26 V
IUVLO-HYS UVLO hysteresis input current VUVLO = 2.5 V –10 –20 –29 µA
VSD-TH Remote shutdown threshold Voltage at UVLO falling 0.32 0.66 V
VSD-HYS Remote shutdown hysteresis 110 mV
THERMAL SHUTDOWN
TSD Thermal shutdown temperature 165 °C
TSD-HYS Thermal shutdown hysteresis 20 °C

(1) All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying
statistical process control.
(2) VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading.

6.6 Timing Requirements

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature
range unless otherwise stated. VIN = 48 V unless otherwise stated.
MIN NOM MAX UNIT
ON-TIME GENERATOR
tON1 tON test 1 VIN = 32 V, RON = 100 kΩ 270 350 460 ns
tON2 tON test 2 VIN = 48 V, RON = 100 kΩ 188 250 336 ns
tON3 tON test 3 VIN = 75 V, RON = 250 kΩ 250 370 500 ns

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Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature
range unless otherwise stated. VIN = 48 V unless otherwise stated.
MIN NOM MAX UNIT
tON4 tON test 4 VIN = 10 V, RON = 250 kΩ 1880 3200 4425 ns
MINIMUM OFF-TIME
tOFF(min) Minimum off-timer VFB = 0 V 144 ns

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6.7 Typical Characteristics

图 6-1. Efficiency at 200 kHz, 10 V 图 6-2. VCC vs VIN

图 6-3. VCC vs ICC 图 6-4. ICC vs External VCC

图 6-5. TON vs VIN and RON 图 6-6. TOFF (ILIM) vs VFB and VIN

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图 6-7. IIN vs VIN (Operating, Non-Switching) 图 6-8. IIN vs VIN (Shutdown)

图 6-9. Switching Frequency vs VIN

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7 Detailed Description
7.1 Overview
The LM5017 step-down synchronous switching converter features all the functions needed to implement a low-
cost, efficient buck regulator capable of supplying 600 mA to the load. This high-voltage regulator contains 100-V
N-channel buck and synchronous rectifier switches and is available in 8-pin thermally-enhanced WSON and SO
packages with pin pitches of 0.8 mm and 1.27 mm, respectively. The regulator operation is based on an adaptive
constant on-time control architecture where the on-time is inversely proportional to input voltage V IN. This feature
maintains a relatively constant operating frequency with load and input voltage variations. A constant on-time
switching regulator requires no loop compensation resulting in fast load transient response.
The LM5017 can be applied in numerous end equipment systems requiring efficient step-down regulation from
higher input voltages. This regulator is well-suited for 24-V industrial systems as well as 48-V communications
and PoE voltage ranges. The LM5017 integrates an undervoltage lockout (UVLO) circuit to prevent faulty
operation of the device at low input voltages and features intelligent current limit and thermal shutdown to protect
the device during overload or short circuit. Peak current limit detection circuit is implemented with a forced off-
time during current limiting that is inversely proportional to VOUT and directly proportional to VIN. Varying the
current limit off-time with VOUT and VIN ensures short-circuit protection with minimal current limit foldback.
Additional protection features include thermal shutdown with automatic recovery, VCC and gate drive UVLO,
minimum forced off-time, and remote shutdown.
7.2 Functional Block Diagram

VIN LM5017
VIN VCC VCC
REGULATOR
VCC UVLO
RUV2 20µA
CIN CVCC
UVLO

THERMAL
RUV1 VIN
SHUTDOWN
1.225V
SHUTDOWN BIAS BST
REGULATOR

RON 0.66V
VIN

RON ON/OFF DISABLE CBST

TIMERS

VOUT COT L VOUT

FEEDBACK CONTROL SW
COMPARATOR
LOGIC
VCC
1.225V RESR
RFB2
COUT
FB 1.62V
CURRENT LIMIT
OVERVOLTAGE COMPARATOR
COMPARATOR
RFB1
CURRENT +
LIMIT TIMER -
RTN
VILIM

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7.3 Feature Description

7.3.1 Control Overview
The LM5017 buck regulator employs a control principle based on a comparator and a one-shot on-timer, with the
output voltage feedback (FB) compared to an internal reference (1.225 V). If the FB voltage is below the
reference the internal buck switch is turned on for the one-shot timer period, which is a function of the input
voltage and the programming resistor (RON). Following the on-time the switch remains off until the FB voltage
falls below the reference, but never before the minimum off-time forced by the minimum off-time one-shot timer.
When the FB pin voltage falls below the reference and the minimum off-time one-shot period expires, the buck
switch is turned on for another on-time one-shot period. This will continue until regulation is achieved and the FB
voltage is approximately equal to 1.225 V (typ).
In a synchronous buck converter, the low-side (sync) FET is on when the high-side (buck) FET is off. The
inductor current ramps up when the high-side switch is on and ramps down when the high-side switch is ‘off’.
There is no diode emulation feature in this IC, and therefore, the inductor current may ramp in the negative
direction at light load. This causes the converter to operate in continuous conduction mode (CCM) regardless of
the output loading. The operating frequency remains relatively constant with load and line variations. Calculate
the operating frequency as shown in 方程式 1.

VOUT
gSW =
K x RON (1)

where
• K = 9 x 10–11
The output voltage (VOUT) is set by two external resistors (RFB1, RFB2). The regulated output voltage is
calculated as shown in 方程式 2.

RFB2 + RFB1
VOUT = 1.225V x
RFB1 (2)

This regulator regulates the output voltage based on ripple voltage at the feedback input, requiring a minimum
amount of ESR for the output capacitor (COUT). A minimum of 25 mV of ripple voltage at the feedback pin (FB) is
required for the LM5017. In cases where the capacitor ESR is too small, additional series resistance may be
required (RC in 图 7-1).
For applications where lower output voltage ripple is required the output can be taken directly from a low ESR
output capacitor, as shown in 图 7-1. However, RC slightly degrades the load regulation.
L1
SW VOUT

LM5017 RFB2 RC
FB VOUT
+ (low ripple)
RFB1 COUT

图 7-1. Low Ripple Output Configuration

7.3.2 VCC Regulator

The LM5017 device contains an internal high-voltage linear regulator with a nominal output of 7.6 V. The input
pin (VIN) can be connected directly to the line voltages up to 100 V. The VCC regulator is internally current limited
to 30 mA. The regulator sources current into the external capacitor at VCC. This regulator supplies current to
internal circuit blocks including the synchronous MOSFET driver and the logic circuits. When the voltage on the
VCC pin reaches the undervoltage lockout (VCC UVLO) threshold of 4.5 V, the IC is enabled.
An internal diode connected from VCC to the BST pin replenishes the charge in the gate drive bootstrap
capacitor when SW pin is low.

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At high input voltages, the power dissipated in the high voltage regulator is significant and can limit the overall
achievable output power. As an example, with the input at 48 V and switching at high frequency, the VCC
regulator may supply up to 7 mA of current resulting in 48 V × 7 mA = 336 mW of power dissipation. If the VCC
voltage is driven externally by an alternate voltage source between 8.55 V and 13 V, the internal regulator is
disabled. This reduces the power dissipation in the IC.
7.3.3 Regulation Comparator
The feedback voltage at FB is compared to an internal 1.225 V reference. In normal operation, when the output
voltage is in regulation, an on-time period is initiated when the voltage at FB falls below 1.225 V. The high side
switch will stay on for the on-time, causing the FB voltage to rise above 1.225 V. After the on-time period, the
high side switch will stay off until the FB voltage again falls below 1.225 V. During start-up, the FB voltage will be
below 1.225 V at the end of each on-time, causing the high side switch to turn on immediately after the minimum
forced off-time of 144 ns. The high side switch can be turned off before the on-time is over if the peak current in
the inductor reaches the current limit threshold.
7.3.4 Overvoltage Comparator
The feedback voltage at FB is compared to an internal 1.62 V reference. If the voltage at FB rises above 1.62 V
the on-time pulse is immediately terminated. This condition can occur if the input voltage and/or the output load
changes suddenly. The high side switch will not turn on again until the voltage at FB falls below 1.225 V.
7.3.5 On-Time Generator
The on-time for the LM5017 device is determined by the RON resistor and is inversely proportional to the input
voltage (VIN), resulting in a nearly constant frequency as VIN is varied over the operating range. The on-time for
the LM5017 can be calculated using 方程式 3.

10-10 x RON
TON =
VIN (3)

See 图 6-5. RON should be selected for a minimum on-time (at maximum VIN) greater than 100 ns for proper
operation. This requirement limits the maximum switching frequency for high VIN.
7.3.6 Current Limit
The LM5017 device contains an intelligent current limit off-timer. If the current in the buck switch exceeds 1.02 A,
the present cycle is immediately terminated, and a non-resetable off-timer is initiated. The length of the off-time
is controlled by the FB voltage and the input voltage VIN. As an example, when FB = 0 V and VIN = 48 V, the off-
time is set to 16 μs. This condition occurs when the output is shorted and during the initial part of start-up. This
VIN dependent off-time ensures safe short circuit operation up to the maximum input voltage of 100 V.
In cases of overload where the FB voltage is above zero volts (not a short circuit) the current limit off-time is
reduced. Reducing the off-time during less severe overloads reduces the amount of foldback, recovery time, and
start-up time. The off-time is calculated from 方程式 4.

0.07 x VIN
TOFF(ILIM) = Ps
VFB + 0.2 V (4)

The current limit protection feature is peak limited. The maximum average output current will be less than the
peak.
7.3.7 N-Channel Buck Switch and Driver
The LM5017 device integrates an N-Channel Buck switch and associated floating high voltage gate driver. The
gate driver circuit works in conjunction with an external bootstrap capacitor and an internal high voltage diode. A
0.01 uF ceramic capacitor connected between the BST pin and the SW pin provides the voltage to the driver
during the on-time. During each off-time, the SW pin is at approximately 0 V, and the bootstrap capacitor charges
from VCC through the internal diode. The minimum off-timer, set to 144 ns, ensures a minimum time each cycle
to recharge the bootstrap capacitor.

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7.3.8 Synchronous Rectifier

The LM5017 provides an internal synchronous N-Channel MOSFET rectifier. This MOSFET provides a path for
the inductor current to flow when the high-side MOSFET is turned off.
The synchronous rectifier has no diode emulation mode, and is designed to keep the regulator in continuous
conduction mode even with light loads which would otherwise result in discontinuous operation.
7.3.9 Undervoltage Detector
The LM5017 device contains a dual level undervoltage lockout (UVLO) circuit. A summary of threshold voltages
and operational states is provided in 节 7.4. When the UVLO pin voltage is below 0.66 V, the regulator is in a low
current shutdown mode. When the UVLO pin voltage is greater than 0.66V but less than 1.225 V, the regulator is
in standby mode. In standby mode the VCC bias regulator is active while the regulator output is disabled. When
the VCC pin exceeds the VCC undervoltage threshold and the UVLO pin voltage is greater than 1.225 V, normal
operation begins. An external set-point voltage divider from VIN to GND can be used to set the minimum
operating voltage of the regulator.
UVLO hysteresis is accomplished with an internal 20-μA current source that is switched on or off into the
impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to
quickly raise the voltage at the UVLO pin. The hysteresis is equal to the value of this current times the resistance
RUV2.
If the UVLO pin is connected directly to the VIN pin, the regulator will begin operation once the VCC undervoltage
is satisfied.
VIN
2
VIN
+
CIN RUV2 LM5017
3
UVLO

RUV1

图 7-2. UVLO Resistor Setting

7.3.10 Thermal Protection

The LM5017 device should be operated so the junction temperature does not exceed 150°C during normal
operation. An internal Thermal Shutdown circuit is provided to protect the LM5017 in the event of a higher than
normal junction temperature. When activated, typically at 165°C, the regulator is forced into a low power reset
state, disabling the buck switch and the VCC regulator. This feature prevents catastrophic failures from accidental
device overheating. When the junction temperature falls below 145°C (typical hysteresis = 20°C), the VCC
regulator is enabled, and normal operation is resumed.
7.3.11 Ripple Configuration
LM5017 uses Constant-On-Time (COT) control in which the on-time is terminated by an on-timer and the off-time
is terminated by the feedback voltage (VFB) falling below the reference voltage (VREF). Therefore, for stable
operation, the feedback voltage must decrease monotonically, in phase with the inductor current during the off-
time. Furthermore, this change in feedback voltage (VFB) during off-time must be larger than any noise
component present at the feedback node.
表 7-1 shows three different methods for generating appropriate voltage ripple at the feedback node. Type 1 and
Type 2 ripple circuits couple the ripple at the output of the converter to the feedback node (FB). The output
voltage ripple has two components:
1. Capacitive ripple caused by the inductor current ripple charging/discharging the output capacitor.
2. Resistive ripple caused by the inductor current ripple flowing through the ESR of the output capacitor.
The capacitive ripple is not in phase with the inductor current. As a result, the capacitive ripple does not
decrease monotonically during the off-time. The resistive ripple is in phase with the inductor current and
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decreases monotonically during the off-time. The resistive ripple must exceed the capacitive ripple at the output
node (VOUT) for stable operation. If this condition is not satisfied unstable switching behavior is observed in COT
converters, with multiple on-time bursts in close succession followed by a long off-time.
Type 3 ripple method uses Rr and Cr and the switch node (SW) voltage to generate a triangular ramp. This
triangular ramp is ac coupled using Cac to the feedback node (FB). Since this circuit does not use the output
voltage ripple, it is ideally suited for applications where low output voltage ripple is required. For more
information on each ripple generation method, refer to the AN-1481 Controlling Output Ripple and Achieving
ESR Independence in Constant On-Time (COT) Regulator Designs application report.
表 7-1. Ripple Configuration
TYPE 1 TYPE 2 TYPE 3
LOWEST COST CONFIGURATION REDUCED RIPPLE CONFIGURATION MINIMUM RIPPLE CONFIGURATION
VOUT VOUT
VOUT
L1 L1
L1
Cac Rr COUT
R FB2 R FB2 Cr
RC RC R FB2

Cac
To FB To FB
GND
C OUT C OUT To FB
R FB1 R FB1
R FB1

GND GND

25 mV VOUT 5 Cr = 3300 pF
RC > x C>
ûIL(MIN) VREF gsw (RFB2||RFB1) Cac = 100 nF
(5)
25 mV (VIN(MIN) - VOUT) x TON
RC > RrCr <
ûIL(MIN) (6) 25 mV (7)

7.3.12 Soft-Start
A soft-start feature can be implemented with the LM5017 using an external circuit. As shown in 图 7-3, the soft-
start circuit consists of one capacitor, C1, two resistors, R1 and R2, and a diode, D. During the initial start-up, the
VCC voltage is established prior to the VOUT voltage. Capacitor C1 is discharged and D is thereby forward biased
to pull up the FB voltage. The FB voltage exceeds the reference voltage (1.225 V) and switching is therefore
disabled. As capacitor C1 charges, the voltage at node B gradually decreases and switching commences. VOUT
will gradually rise to maintain the FB voltage at the reference voltage. Once the voltage at node B is less than a
diode drop above FB voltage, the soft-start is finished and D is reverse biased.
During the initial part of the start-up, the FB voltage can be approximated as follows. Please note that the effect
of R1 has been ignored to simplify the calculation shown in 方程式 8.

RFB1 x RFB2
VFB = (VCC - VD) x
R2 x (RFB1 + RFB2) + RFB1 x RFB2 (8)

C1 is charged after the first start up. Diode D1 is optional and can be added to discharge C1 when the input
voltage experiences a momentary drop to initialize the soft-start sequence.

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To achieve the desired soft-start, the following design guidance is recommended:

(1) R2 is selected so that VFB is higher than 1.225 V for a VCC of 4.5 V, but is lower than 5 V when VCC is 8.55 V.
If an external VCC is used, VFB should not exceed 5 V at maximum VCC.
(2) C1 is selected to achieve the desired start-up time that can be determined from 方程式 9.

RFB1 x RFB2
tS = C1 x (R2 + )
RFB1 + RFB2 (9)

(3) R1 is used to maintain the node B voltage at zero after the soft-start is finished. A value larger than the
feedback resistor divider is preferred. Note that the effect of R1 is ignored in the previous equations.
Based on the schematic shown in 图 8-1, selecting C1 = 1 uF, R2 = 1 kΩ, R1 = 30 kΩ results in a soft-start time of
about 2 ms.
VOUT VCC

C1
RFB2

R2
To FB D D1
B

RFB1 R1

图 7-3. Soft-Start Circuit

7.4 Device Functional Modes

表 7-2. UVLO Modes
UVLO VCC Regulator MODE DESCRIPTION
VCC regulator disabled.
< 0.66 V Disabled Shutdown
Switching disabled.
VCC regulator enabled
0.66 V – 1.225 V Enabled Standby
Switching disabled.
VCC regulator enabled.
VCC < 4.5 V Standby
Switching disabled.
> 1.225 V
VCC enabled.
VCC > 4.5 V Operating
Switching enabled.

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8 Application and Implementation

Note
以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The LM5017 device is step-down DC-DC converter. The device is typically used to convert a higher DC voltage
to a lower DC voltage with a maximum available output current of 650 mA. Use the following design procedure to
select component values for the LM5017 device. Alternately, use the WEBENCH® software to generate a
complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive
database of components when generating a design. This section presents a simplified discussion of the design
process.
8.2 Typical Application
8.2.1 Application Circuit: 12.5-V to 95-V Input and 10-V, 600-mA Output Buck Converter
The application schematic of a buck supply is shown in 图 8-1. For output voltage (VOUT) more than one diode
drop above the maximum regulation threshold of VCC (8.55 V, see 节 6.5), the VCC pin can be connected to V OUT
through a diode (D2), as shown in 图 8-1, for higher efficiency and lower power dissipation in the IC.
The design example below uses equations from the 节 7.3 with component names provided . Corresponding
component designators from 图 8-1 are also provided for each selected value.
SW
12.5 V±95 V (TP6)
VIN LM5017
(TP1) 7 0.01 F
2 BST 220 H 0Ÿ
VIN +
C1 L1 R8 VOUT
8
C4 + C5 + R5 4
RON
SW
2.2 F 0.47 F 127 NŸ (TP3)
R3
499 NŸ R4 C6 3300 pF R2
GND 3 46.4 NŸ 0Ÿ
UVLO C8
(TP2)
0.1 F
VCC R1 +
(TP4) 6 D2 6.98 NŸ C9
R7
UVLO/SD 14 NŸ FB 22 F
5
EXP RTN R6
+
1 U1 C7 1 NŸ GND
1 F (TP5)

图 8-1. Final Schematic for 12.5-V to 95-V Input, and 10-V, 600-mA Output Buck Converter

8.2.1.1 Design Requirements

Selection of external components is illustrated through a design example. The design example specifications are
shown in 表 8-1.
表 8-1. Buck Converter Design Specifications
DESIGN PARAMETERS VALUE
Input voltage range 12.5 V to 95 V
Output voltage 10 V
Maximum Load current 600 mA
Switching Frequency ≈ 225 kHz

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Custom Design with WEBENCH Tools
Click here to create a custom design using the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT and IOUT requirements.

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2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real
time pricing and component availability.
4. In most cases, you will also be able to:
• Run electrical simulations to see important waveforms and circuit performance,
• Run thermal simulations to understand the thermal performance of your board,
• Export your customized schematic and layout into popular CAD formats,
• Print PDF reports for the design, and share your design with colleagues.
8.2.1.2.2 RFB1, RFB2
VOUT = VFB x (RFB2/RFB1 + 1), and because VFB = 1.225 V, the ratio of RFB2 to RFB1 calculates as 7 : 1. Standard
values are chosen with RFB2 = R1 = 6.98 kΩ and RFB1 = R6 = 1 kΩ. Other values could be used as long as the
7 : 1 ratio is maintained.
8.2.1.2.3 Frequency Selection
At the minimum input voltage, the maximum switching frequency of LM5017 is restricted by the forced minimum
off-time (TOFF(MIN)) as given by 方程式 10.

1 - DMAX 1 - 10/12.5
gSW(MAX) = = = 1 MHz
TOFF(MIN) 200 ns (10)

Similarly, at maximum input voltage, the maximum switching frequency of LM5017 is restricted by the minimum
TON as given by 方程式 11.

DMIN 10/95
gSW(MAX) = = = 1.05 MHz
TON(MIN) 100 ns (11)

Resistor RON sets the nominal switching frequency based on 方程式 12.

VOUT
gSW =
K x RON (12)

where
• K = 9 x 10–11
Operation at high switching frequency results in lower efficiency while providing the smallest solution. For this
example a conservative 225 kHz was selected, resulting in RON = 493 kΩ. A standard value for RON = R3 = 499
kΩ is selected.
8.2.1.2.4 Inductor Selection
The minimum inductance is selected to limit the output ripple to 15 to 40 percent of the maximum load current. In
addition, the peak inductor current at maximum load should be smaller than the minimum current limit as given in
节 6.5 table.
The inductor current ripple is given by 方程式 13.

VIN - VOUT VOUT

ûIL = x
L1 x gSW VIN (13)

The maximum ripple is observed at maximum input voltage. Substituting VIN = 95 V and ΔIL = 40 percent ×
IOUT (max) results in L1 = 198 μH. The next higher standard value of 220 μH is chosen. The peak-to-peak
minimum and maximum inductor current ripple are 40 mA and 181 mA at the minimum and maximum input
voltages respectively. The peak inductor and switch current is given by 方程式 14.

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ûIL(MAX)
ILI(peak) = IOUT + = 690 mA
2 (14)

690 mA is less than the minimum current limit threshold of 0.7 A. The selected inductor should be able to
withstand the maximum current limit of 1.3 A during startup and overload conditions without saturating.
8.2.1.2.5 Output Capacitor
The output capacitor is selected to minimize the capacitive ripple across it. The maximum ripple is observed at
maximum input voltage and is given by:

ûIL
COUT =
8 x gsw x ûVripple (15)

where
• ΔVripple is the voltage ripple across the capacitor.
Assuming VIN = 95 V and substituting ΔVripple = 10 mV gives COUT = 10.1 μF. A 22-μF standard value is
selected for COUT = C9. An X5R or X7R type capacitor with a voltage rating 16 V or higher should be selected.
8.2.1.2.6 Type III Ripple Circuit

Type III ripple circuit as described in 节 7.3.11 is chosen for this example. For a constant on-time converter to be
stable, the injected in-phase ripple should be larger than the capacitive ripple on COUT.
Using the type III ripple circuit equation, the target ripple will be greater than the capacitive ripple generated at
the primary-side output if the following condition is satisfied:
Cr = C6 = 3300 pF
Cac = C8 = 100 nF

(VIN(MIN) VOUT ) u TON(VINMIN)

Rr d
(25 mV u Cr ) (16)

For TON, refer to 方程式 3.

Ripple resistor Rr is calculated to be 57.6 kΩ. This value provides the minimum ripple for stable operation. A
smaller resistance should be selected to allow for variations in TON, COUT, and other components. Rr = R4 = 46.4
kΩ is selected for this example application.
8.2.1.2.7 VCC and Bootstrap Capacitors
The VCC capacitor provides charge to bootstrap capacitor as well as internal circuitry and low side gate driver.
The Bootstrap capacitor provides charge to high side gate driver. The recommended value for CVCC = C7 = 1
μF. A good value for CBST = C1 = 0.01 μF.
8.2.1.2.8 Input Capacitor

Input capacitor should be large enough to limit the input voltage ripple as shown in 方程式 17.

IOUT(MAX)
CIN >
4 x gSW x ûVIN (17)

Choosing a ΔVIN = 0.5 V gives a minimum CIN = 1.3 μF. A standard value of 2.2 μF is selected for CIN = C4.
The input capacitor should be rated for the maximum input voltage under all conditions. A 100-V, X7R dielectric
should be selected for this design.

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The input capacitor should be placed directly across VIN and RTN (pin 1 and 2) of the IC. If it is not possible to
place all of the input capacitor close to the IC, a 0.47-μF capacitor should be placed near the IC to provide a
bypass path for the high frequency component of the switching current.
8.2.1.2.9 UVLO Resistors
The UVLO resistors RFB1 and RFB2 set the UVLO threshold and hysteresis according to the relationship shown
in 方程式 18 and 方程式 19.

VIN(HYS) = IHYS x RUV2 (18)

where
• IHYS = 20 μA

R
VIN (UVLO,rising) = 1.225 V x ( RUV2
UV1
+ 1)
(19)

Setting UVLO hysteresis of 2.5 V and UVLO rising threshold of 12 V results in RUV1 = 14.53 kΩ and
RUV2 = 125 kΩ. Selecting standard values of RUV1 = R7 = 14 kΩ and RUV2 = R5 = 127 kΩ results in UVLO
threshold and hysteresis of 12.4 V and 2.5 V respectively.

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8.2.1.3 Application Curves

图 8-2. Efficiency vs Load Current 图 8-3. Frequency vs Input Voltage

图 8-4. Typical Switching Waveform (VIN = 48 V, IOUT = 200 mA)

8.2.2 Isolated DC/DC Converter Using LM5017

An isolated supply using the LM5017 is shown in 图 8-5. Inductor (L) in a typical buck circuit is replaced with a
coupled inductor (X1). A diode (D1) is used to rectify the voltage on a secondary output. The nominal voltage at
the secondary output (VOUT2) is given by 方程式 20.

NS
VOUT2 = VOUT1 x - VF
NP (20)

where
• VF is the forward voltage drop of D1
• NP and NS are the number of turns on the primary and secondary of coupled inductor X1.
For output voltage (VOUT1) more than one diode drop above the maximum VCC (8.55 V), the VCC pin can be
diode connected to VOUT1 for higher efficiency and low dissipation in the IC. For a complete isolated bias design
with LM5017, refer to the AN-2204 LM5017 Isolated Supply Evaluation Board application report.

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D1 VOUT2

+
COUT2
N2 1 µF

1:1 X1
LM5017 0.01 µF
BST N1 33 µH
+ VOUT1
CBST
VIN
SW
20V-95V 46.4 NŸ 1 nF
VIN Rr Cr
+ + +
CBYP RUV2 RON COUT1
CIN Cac
0.47 µF RON 0.1 µF 1 µF
2.2 µF 127 NŸ
130 NŸ RFB2
UVLO VCC
D2 7.32 NŸ
FB
RUV1 RTN
8.25 NŸ +
CVCC RFB1
1 µF 1 NŸ

图 8-5. Typical Isolated Application Schematic

8.2.2.1 Design Requirements

DESIGN PARAMETERS VALUE
Input Voltage Range 20 V – 100 V
Primary Output Voltage 10 V
Secondary (Isolated) Output Voltage 9.5 V
Maximum Load Current (Primary + Secondary) 300 mA
Maximum Power Output 3W
Nominal Switching Frequency 750 kHz

8.2.2.2 Detailed Design Procedure

8.2.2.2.1 Transformer Turns Ratio
The transformer turns ratio is selected based on the ratio of the primary output voltage to the secondary
(isolated) output voltage. In this design example, the two outputs are nearly equal and a 1 : 1 turns ratio
transformer is selected. Therefore, N2 / N1 = 1.
If the secondary (isolated) output voltage is significantly higher or lower than the primary output voltage, a turns
ratio less than or greater than 1 is recommended. The primary output voltage is normally selected based on the
input voltage range such that the duty cycle of the converter does not exceed 50% at the minimum input voltage.
This condition is satisfied if VOUT1 < VIN_MIN / 2.
8.2.2.2.2 Total IOUT
Calculate the total primary-referred load current by multiplying the isolated output loads by the turns ratio of the
transformer as shown in 方程式 21.

N2
IOUT(MAX) IOUT1 IOUT2 u 0.3 A
N1 (21)

8.2.2.2.3 RFB1, RFB2

The feedback resistors are selected to set the primary output voltage. The selected value for RFB1 is 1 kΩ. RFB2
can be calculated using the following equations to set VOUT1 to the specified value of 10 V. A standard resistor
value of 7.32 kΩ is selected for RFB2.

RFB2
VOUT1 = 1.225V x (1 + )
RFB1 (22)

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VOUT1
: RFB2 = ( 1.225 - 1) x RFB1 = 7.16 k:
(23)

8.2.2.2.4 Frequency Selection

Calculate the value of RON to achieve the desired switching frequency using 方程式 24.

VOUT1
f SW =
. x RON (24)

where
• K = 9 × 10–11
For VOUT1 of 10 V and fSW of 750 kHz, the calculated value of RON is 148 kΩ. A lower value of 130 kΩ is
selected for this design to allow for second-order effects at high switching frequency that are not included in 方程
式 24.
8.2.2.2.5 Transformer Selection
A coupled inductor or a flyback-type transformer is required for this topology. Energy is transferred from primary
to secondary when the low-side synchronous switch of the buck converter is conducting.
The maximum inductor primary ripple current that can be tolerated without exceeding the buck switch peak
current limit threshold (0.7 A minimum) is given by 方程式 25.

§ N2 ·
'IL1 ¨ 0.7 IOUT1 IOUT2 u N1 ¸ u 2 0.8 A
© ¹ (25)

Using the maximum peak-to-peak inductor ripple current ΔIL1 from 方程式 25, the minimum inductor value is
given by 方程式 26.

VIN(MAX) VOUT VOUT

L1 u 14.9 PH
'IL1 u ¦SW VIN(MAX) (26)

A higher value of 33 µH is selected to insure the high-side switch current does not exceed the minimum peak
current limit threshold. With this inductance, the inductor current ripple is ΔIL1= 0.36 A at the maximum VIN.
8.2.2.2.6 Primary Output Capacitor

In a conventional buck converter the output ripple voltage is calculated as shown in 方程式 27.

'IL1
'VOUT =
f

x f x COUT1 (27)

To limit the primary output ripple voltage ΔVOUT1 to approximately 50 mV, an output capacitor COUT1 of 1.2 µF
would be required for a conventional buck.
图 8-6 shows the primary winding current waveform (IL1) of a Fly-Buck ™ converter. The reflected secondary
winding current adds to the primary winding current during the buck switch off-time. Because of this increased
current, the output voltage ripple is not the same as in conventional buck converter. The output capacitor value
calculated in 方程式 27 should be used as the starting point. Optimization of output capacitance over the entire
line and load range must be done experimentally. If the majority of the load current is drawn from the secondary
isolated output, a better approximation of the primary output voltage ripple is given by 方程式 28.

§ N2 ·
¨ IOUT2 u N1 ¸ u TON(MAX)
'VOUT1 © ¹ | 67 mV
COUT1 (28)

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TON(MAX) x IOUT2 x N2/N1

IL1 IOUT2
IL2

TON(MAX) x IOUT2

图 8-6. Current Waveforms for COUT1 Ripple Calculation

A standard 1-µF, 25 V capacitor is selected for this design. If lower output voltage ripple is required, a higher
value should be selected for COUT1 and/or COUT2.
8.2.2.2.7 Secondary Output Capacitor

A simplified waveform for secondary output current (IOUT2) is shown in 图 8-7.

IOUT2
IL2
TON(MAX) x IOUT2

图 8-7. Secondary Current Waveforms for COUT2 Ripple Calculation

The secondary output current (IOUT2) is sourced by COUT2 during on-time of the buck switch, TON. Ignoring the
current transition times in the secondary winding, the secondary output capacitor ripple voltage can be
calculated using 方程式 29.

IOUT2 x TON (MAX)

'VOUT2 =
COUT2 (29)

For a 1 : 1 transformer turns ratio, the primary and secondary voltage ripple equations are identical. Therefore,
COUT2 is chosen to be equal to COUT1 (1 µF) to achieve comparable ripple voltages on primary and secondary
outputs.
If lower output voltage ripple is required, a higher value should be selected for COUT1 and/or COUT2.
8.2.2.2.8 Type III Feedback Ripple Circuit

Type III ripple circuit as described in 节 7.3.11 is required for the Fly-Buck topology. Type I and Type II ripple
circuits use series resistance and the triangular inductor ripple current to generate ripple at VOUT and the FB pin.
The primary ripple current of a Fly-Buck is the combination or primary and reflected secondary currents as
illustrated in 图 8-6. In the Fly-Buck topology, Type I and Type II ripple circuits suffer from large jitter as the
reflected load current affects the feedback ripple.
VOUT
L1

Rr Cr C OUT

R FB2
Cac

GND
To FB
R FB1

图 8-8. Type III Ripple Circuit

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Selecting the Type III ripple components using the equations from 节 7.3.11 will ensure that the FB pin ripple is
be greater than the capacitive ripple from the primary output capacitor COUT1. The feedback ripple component
values are chosen as shown in 方程式 30.

Cr = 1000 pF
Cac = 0.1 PF
(VIN (MIN) - VOUT) x TON
RrCr d
50 mV (30)

The calculated value for Rr is 66 kΩ. This value provides the minimum ripple for stable operation. A smaller
resistance should be selected to allow for variations in TON, COUT1 and other components. For this design, Rr
value of 46.4 kΩ is selected.
8.2.2.2.9 Secondary Diode
The reverse voltage across secondary-rectifier diode D1 when the high-side buck switch is off can be calculated
using 方程式 31.

N2
VD1 = VIN
N1 (31)

For a VIN_MAX of 95 V and the 1:1 turns ratio of this design, a 100 V Schottky is selected.
8.2.2.2.10 VCC and Boostrap Capacitor
A 1-µF capacitor of 16 V or higher rating is recommended for the VCC regulator bypass capacitor. A good value
for the BST pin bootstrap capacitor is 0.01-µF with a 16 V or higher rating.
8.2.2.2.11 Input Capacitor
The input capacitor is typically a combination of a smaller bypass capacitor located near the regulator IC and a
larger bulk capacitor. The total input capacitance should be large enough to limit the input voltage ripple to a
desired amplitude. For input ripple voltage ΔVIN, CIN can be calculated using 方程式 32.

IOUT(MAX)
CIN t
4 u ¦ u '9IN (32)

Choosing a ΔVIN of 0.5 V gives a minimum CIN of 0.2 μF. A standard value of 0.47 μF is selected for CBYP in
this design. A bulk capacitor of higher value reduces voltage spikes due to parasitic inductance between the
power source to the converter. A standard value of 2.2 μF is selected for CIN in this design. The voltage ratings
of the two input capacitors should be greater than the maximum input voltage under all conditions.
8.2.2.2.12 UVLO Resistors

UVLO resistors RUV1 and RUV2 set the undervoltage lockout threshold and hysteresis according to 方程式 33
and 方程式 34.

VIN (HYS) = IHYS x RUV2 (33)

where
• IHYS = 20 μA, typical.

R
VIN (UVLO, rising) = 1.225V x ( RUV2 + 1)
UV1 (34)

For a UVLO hysteresis of 2.5 V and UVLO rising threshold of 20 V, 方程式 33 and 方程式 34 require RUV1 of
8.25 kΩ and RUV2 of 127 kΩ and these values are selected for this design example.

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8.2.2.2.13 VCC Diode

Diode D2 is an optional diode connected between VOUT1 and the VCC regulator output pin. When VOUT1 is more
than one diode drop greater than the VCC voltage, the VCC bias current is supplied from VOUT1. This results in
reduced power losses in the internal VCC regulator which improves converter efficiency. VOUT1 must be set to a
voltage at least one diode drop higher than 8.55 V (the maximum VCC voltage) if D2 is used to supply bias
current.
8.2.2.3 Application Curves

图 8-9. Steady State Waveform (VIN = 48 V, IOUT1 =

图 8-10. Step Load Response (VIN = 48 V, IOUT1 = 0
100 mA, IOUT2 = 200 mA)
A, Step Load on IOUT2 = 100 mA to 200 mA)

图 8-11. Efficiency at 750 kHz, VOUT1 = 10 V

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9 Power Supply Recommendations

The LM5017 DC/DC converter is designed to operate from a wide input voltage range of 7.5 V to 100 V. The
characteristics of the input supply must be compatible with the 节 6.1 and 节 6.3 tables. In addition, the input
supply must be capable of delivering the required input current to the fully-loaded regulator. Estimate the
average input current with 方程式 35.

POUT
IIN
VIN ˜ K
(35)

where
• η is the efficiency
If the regulator is connected to an input supply through long wires or PCB traces with a large impedance, take
special care to achieve stable performance. The parasitic inductance and resistance of the input cables may
have an adverse affect on converter operation, particularly during operation at low input voltage. The parasitic
inductance in combination with the low-ESR ceramic input capacitors form an underdamped resonant circuit.
This circuit can cause overvoltage transients at VIN each time the input supply is cycled on and off. The parasitic
resistance causes the input voltage to dip during a load transient. The best way to solve such issues is to reduce
the distance from the input supply to the regulator and use an aluminum or tantalum input capacitor in parallel
with the ceramics. The moderate ESR of the electrolytic capacitors helps to damp the input resonant circuit and
reduce any voltage overshoots. A capacitance in the range of 4.7 µF to 22 µF is usually sufficient to provide
input parallel damping and helps to hold the input voltage steady during large load transients.
An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as
well as some of the effects mentioned above. The application report Simple Success with Conducted EMI for
DC-DC Converters (SNVA489) provides helpful suggestions when designing an input filter for any switching
regulator.

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25

Product Folder Links: LM5017
LM5017
ZHCS812K – JANUARY 2012 – REVISED AUGUST 2021 www.ti.com.cn

10 Layout
10.1 Layout Guidelines
A proper layout is essential for optimum performance of the circuit. In particular, the following guidelines should
be observed:
1. CIN: The loop consisting of input capacitor (CIN), VIN pin, and RTN pin carries switching currents. Therefore,
the input capacitor should be placed close to the IC, directly across VIN and RTN pins and the connections to
these two pins should be direct to minimize the loop area. In general it is not possible to accommodate all of
input capacitance near the IC. A good practice is to use a 0.1-μF or 0.47-μF capacitor directly across the
VIN and RTN pins close to the IC, and the remaining bulk capacitor as close as possible (see 图 10-1).
2. CVCC and CBST: The VCC and bootstrap (BST) bypass capacitors supply switching currents to the high and
low side gate drivers. These two capacitors should also be placed as close to the IC as possible, and the
connecting trace length and loop area should be minimized (see 图 10-1).
3. The Feedback trace carries the output voltage information and a small ripple component that is necessary
for proper operation of LM5017. Therefore, care should be taken while routing the feedback trace to avoid
coupling any noise to this pin. In particular, feedback trace should not run close to magnetic components, or
parallel to any other switching trace.
4. SW trace: The SW node switches rapidly between VIN and GND every cycle and is therefore a possible
source of noise. The SW node area should be minimized. In particular, the SW node should not be
inadvertently connected to a copper plane or pour.
10.2 Layout Example

RTN 1 8 SW
CIN

VIN 2 7 BST
SO
PowerPAD-
8
UVLO 3 6 VCC

CVCC
RON 4 5 FB

图 10-1. Placement of Bypass Capacitors

26 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: LM5017

 LM5017
www.ti.com.cn ZHCS812K – JANUARY 2012 – REVISED AUGUST 2021

11 Device and Documentation Support

11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.1.2 Development Support
For development support, see the following:
• LM5017 Buck Converter Quick-start Calculator
• Fly-Buck Converter Quick-start Calculator
• LM5017 PSPICE Transient Model
• LM5017 TINA-TI Transient Spice Model
• LM5017 TINA-TI Transient Reference Design
• For TI's reference design library, visit TI Reference Designs
• For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center.
• To view a related device of this product, see the LM5018 100-V, 300-mA synchronous buck converter.
• Power House Blogs:
– Fly-Buck: Frequently Asked Questions (FAQs)
– Lower EMI and Quiet Switching With the Fly-Buck Topology
– Fly-Buck Converter PCB Layout Tips
– When is Fly-Buck the Right Choice for Your Isolated Power Needs?
– How to Design for EMC and Isolation With Fly-Buck Converters
– Create a Fly-Buck Converter in WEBENCH® Power Designer
11.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5017 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• AN-2200 LM5017 Evaluation Board (SNVA612)
• AN-2204 LM5017 Isolated Supply Evaluation Board (SNVA611)
• AN-2292 Designing an Isolated Buck (Fly-Buck) Converter (SNVA674)
• AN-1481 Controlling Output Ripple & Achieving ESR Independence in Constant ON-Time Regulator Designs
(SNVA166)
• TI Reference Designs:
– Dual Channel-to-Channel Isolated Universal Analog Input Module for PLC Reference Design (TIDUBI1)

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 27

Product Folder Links: LM5017
LM5017
ZHCS812K – JANUARY 2012 – REVISED AUGUST 2021 www.ti.com.cn

– High Voltage Stepper Driver Reference Design (TIDUCR6)

– Reference Design for Voltage, Current & Temp Monitoring for Solar Module Level Power Electronics
(TIDUCM3)
– High Resolution, Fast Startup Analog Front End for Air Circuit Breaker Reference Design (TIDUB80)
– Signal Processing Front End for Electronic Trip Units Used in ACBs/MCCBs reference design (TIDUA09)
– Ultra-Small 1W, 12V-36V Iso Power Supply for Analog Prog Logic Controller Modules Reference Design
(TIDU855)
– 16-Bit Analog Output Module Reference Design for Programmable Logic Controllers (PLCs) (TIDU189)
– 2.5W Bipolar Isolated Fly-Buck Ultra-Compact Reference Design (TIDUCA3)
– Class 3 Isolated Fly-Buck Power Module for PoE Application Reference Design (TIDU779)
– Wide-Input Isolated IGBT Gate-Drive Fly-Buck Power Supply for Three-Phase Inverters (TIDU670)
– Isolated RS-485 to Wi-Fi Bridge with 24 VAC Power Reference Design (TIDUA49)
– Dual-Output Isolated Fly-Buck Reference Design With an Ultra-Small Coupled Inductor (TIDUC31)
– Small Footprint Isolated DC/DC Converter for Analog Input Module Reference Design (TIDUBR7)
– Leakage Current Measurement Reference Design for Determining Insulation Resistance (TIDU873)
– Thermal Protection Reference Design of IGBT Modules for HEV/EV Traction Inverters (TIDUBJ2)
• White Papers:
– Designing Isolated Rails on the Fly With Fly-Buck Converters
– Valuing Wide VIN, Low-EMI Synchronous Buck Circuits for Cost-Effective, Demanding Applications
– An Overview of Conducted EMI Specifications for Power Supplies
– An Overview of Radiated EMI Specifications for Power Supplies
• AN-2162: Simple Success with Conducted EMI from DC-DC Converters (SNVA489)
• Using New Thermal Metrics (SBVA025)
• Semiconductor and IC Package Thermal Metrics (SPRA953)
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.5 Trademarks
PowerPAD™ and are trademarks of Texas Instruments.
Fly-Buck™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® are registered trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。

11.7 术语表
TI 术语表 本术语表列出并解释了术语、首字母缩略词和定义。

28 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: LM5017

 LM5017
www.ti.com.cn ZHCS812K – JANUARY 2012 – REVISED AUGUST 2021

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 29

Product Folder Links: LM5017
 重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款 (https:www.ti.com/legal/termsofsale.html) 或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。重要声明

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Copyright © 2021，德州仪器 (TI) 公司
 PACKAGE OPTION ADDENDUM

www.ti.com 23-May-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

LM5017MR/NOPB Active Production SO PowerPAD 95 | TUBE Yes NIPDAU | SN Level-3-260C-168 HR -40 to 125 L5017
(DDA) | 8 MR
LM5017MR/NOPB.A Active Production SO PowerPAD 95 | TUBE Yes NIPDAU Level-3-260C-168 HR -40 to 125 L5017
(DDA) | 8 MR
LM5017MR/NOPB.B Active Production SO PowerPAD 95 | TUBE Yes NIPDAU Level-3-260C-168 HR -40 to 125 L5017
(DDA) | 8 MR
LM5017MRE/NOPB Active Production SO PowerPAD 250 | SMALL T&R Yes NIPDAU | SN Level-3-260C-168 HR -40 to 125 L5017
(DDA) | 8 MR
LM5017MRE/NOPB.A Active Production SO PowerPAD 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 L5017
(DDA) | 8 MR
LM5017MRE/NOPB.B Active Production SO PowerPAD 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 L5017
(DDA) | 8 MR
LM5017MRX/NOPB Active Production SO PowerPAD 2500 | LARGE T&R Yes NIPDAU | SN Level-3-260C-168 HR -40 to 125 L5017
(DDA) | 8 MR
LM5017MRX/NOPB.A Active Production SO PowerPAD 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 L5017
(DDA) | 8 MR
LM5017MRX/NOPB.B Active Production SO PowerPAD 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 L5017
(DDA) | 8 MR
LM5017SD/NOPB Active Production WSON (NGU) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5017
LM5017SD/NOPB.A Active Production WSON (NGU) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5017
LM5017SD/NOPB.B Active Production WSON (NGU) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5017
LM5017SDE/NOPB Active Production WSON (NGU) | 8 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5017
LM5017SDX/NOPB Active Production WSON (NGU) | 8 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5017
LM5017SDX/NOPB.A Active Production WSON (NGU) | 8 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5017
LM5017SDX/NOPB.B Active Production WSON (NGU) | 8 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5017

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 23-May-2025

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 23-May-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5017MRE/NOPB SO DDA 8 250 178.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PowerPAD
LM5017MRE/NOPB SO DDA 8 250 330.0 12.5 6.4 5.2 2.1 8.0 12.0 Q1
PowerPAD
LM5017MRX/NOPB SO DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PowerPAD
LM5017MRX/NOPB SO DDA 8 2500 330.0 12.5 6.4 5.2 2.1 8.0 12.0 Q1
PowerPAD
LM5017SD/NOPB WSON NGU 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5017SDX/NOPB WSON NGU 8 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 23-May-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5017MRE/NOPB SO PowerPAD DDA 8 250 208.0 191.0 35.0
LM5017MRE/NOPB SO PowerPAD DDA 8 250 353.0 353.0 32.0
LM5017MRX/NOPB SO PowerPAD DDA 8 2500 356.0 356.0 36.0
LM5017MRX/NOPB SO PowerPAD DDA 8 2500 353.0 353.0 32.0
LM5017SD/NOPB WSON NGU 8 1000 208.0 191.0 35.0
LM5017SDX/NOPB WSON NGU 8 4500 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 23-May-2025

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
LM5017MR/NOPB DDA HSOIC 8 95 507.79 8 630 4.32
LM5017MR/NOPB DDA HSOIC 8 95 495 8 4064 3.05
LM5017MR/NOPB.A DDA HSOIC 8 95 507.79 8 630 4.32
LM5017MR/NOPB.A DDA HSOIC 8 95 495 8 4064 3.05
LM5017MR/NOPB.B DDA HSOIC 8 95 507.79 8 630 4.32
LM5017MR/NOPB.B DDA HSOIC 8 95 495 8 4064 3.05

Pack Materials-Page 3
 PACKAGE OUTLINE
DDA0008B SCALE 2.400
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

C
6.2
TYP SEATING PLANE
5.8
A
PIN 1 ID
AREA 0.1 C
6X 1.27
8
1

5.0 2X
4.8 3.81
NOTE 3

4
5
0.51
8X
4.0 0.31
B 1.7 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.10

SEE DETAIL A

4 5
EXPOSED
THERMAL PAD

3.4 0.25
9 GAGE PLANE
2.8

0.15
0 -8 1.27 0.00
1 8
0.40
DETAIL A
2.71 TYPICAL
2.11

4214849/A 08/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.

www.ti.com
 EXAMPLE BOARD LAYOUT
DDA0008B PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.95)
NOTE 9
(2.71) SOLDER MASK
DEFINED PAD
SOLDER MASK
OPENING
8X (1.55) SEE DETAILS

1
8

8X (0.6)

(3.4)
SYMM 9 SOLDER MASK
(1.3)
TYP OPENING

(4.9)
NOTE 9
6X (1.27)

4 5
(R0.05) TYP
SYMM METAL COVERED
( 0.2) TYP BY SOLDER MASK
VIA
(1.3) TYP
(5.4)

LAND PATTERN EXAMPLE

SCALE:10X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK METAL SOLDER MASK METAL UNDER

OPENING OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

PADS 1-8

4214849/A 08/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
DDA0008B PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.71)
BASED ON
0.125 THICK
STENCIL
8X (1.55) (R0.05) TYP
1
8

8X (0.6)

(3.4)
SYMM 9 BASED ON
0.125 THICK
STENCIL

6X (1.27)

5
4

METAL COVERED
SYMM SEE TABLE FOR
BY SOLDER MASK
DIFFERENT OPENINGS
FOR OTHER STENCIL
(5.4)
THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 3.03 X 3.80
0.125 2.71 X 3.40 (SHOWN)
0.150 2.47 X 3.10
0.175 2.29 X 2.87

4214849/A 08/2016

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
NGU0008B SCALE 3.000
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

4.1 B
A
3.9

PIN 1 INDEX AREA

4.1
3.9

0.8
0.7
C

SEATING PLANE
0.05
0.00 0.08 C

EXPOSED (0.1) TYP

1.98 0.05
THERMAL PAD

4 5

2X SYMM
9
2.4 3 0.05

8
1
6X 0.8
0.35
8X
SYMM 0.25
PIN 1 ID
0.1 C A B
0.5 0.05 C
8X
0.3
4214936/A 12/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
NGU0008B WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(1.98)
8X (0.6) SYMM

1
8X (0.3) 8

SYMM 9
(3)

(1.25)
6X (0.8)
4 5

(R0.05) TYP
( 0.2) VIA
TYP (0.74)
(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

EXPOSED EXPOSED
METAL METAL

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214936/A 12/2023

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

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 EXAMPLE STENCIL DESIGN
NGU0008B WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

SYMM
METAL
8X (0.6) TYP

1
8X (0.3) 8

(0.755)
9
SYMM

6X (0.8) (1.31)

5
4

(R0.05) TYP
(1.75)

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:
77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X

4214936/A 12/2023

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

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