LM317L

SLCS144F – JULY 2004 – REVISED DECEMBER 2024

LM317L 100mA Adjustable Floating Voltage Regulator

1 Features 3 Description
• Output voltage range (VO): The LM317L is an adjustable, 3-terminal, positive-
– Adjustable 1.25V to 37V (for new chip) voltage regulator capable of supplying up to 100 mA
– Adjustable 1.25V to 32V (for legacy chip) over an output-voltage range of 1.25V to 37V. The
• Output current: Up to 100mA device is exceptionally easy to use and requires only
• Accuracy: two external resistors to set the output voltage.
– Input regulation typically 0.01% per input For the legacy chip, the LM317LC series is
voltage change characterized for the junction temperature range
– Output regulation typically 0.5% of 0°C to +125°C and the LM317LI device is
• Ripple rejection typically: characterized for the operating junction temperature
– 80 dB at 120Hz range of –40°C to +125°C. For the new chip, the both
– 65 dB at 100kHz LM317LC and LM317LI series are characterized for
• For higher output current requirements, the junction temperature range of –40°C to +125°C.
see LM317M (500mA) and LM317 (1.5A)
Package Information
2 Applications PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
D (SOIC, 8) 4.9mm × 6mm
• Electronic points of sale
• Medical, health, and fitness applications LP (TO-92, 3) 4.8mm × 3.68mm
LM317L
• Printers PK (SOT-89, 3) 4.5mm × 4.095mm
• Appliances and white goods PW (TSSOP, 8) 3mm × 6.4mm
• TV
(1) For more information, see the Mechanical, Packaging, and
Orderable Information.
(2) The package size (length × width) is a nominal value and
includes pins, where applicable.

LM317L
VI VO
Input Output

Adjustment R1
470 W
C1 = 0.1 µF C2 = 1 µF

R2

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7.1 Application Information............................................... 9
2 Applications..................................................................... 1 7.2 Typical Application...................................................... 9
3 Description.......................................................................1 7.3 System Examples..................................................... 11
4 Pin Configuration and Functions...................................3 7.4 Power Supply Recommendations.............................15
5 Specifications.................................................................. 4 7.5 Layout....................................................................... 15
5.1 Absolute Maximum Ratings........................................ 4 7.6 Estimating Junction Temperature..............................15
5.2 ESD Ratings............................................................... 4 8 Device and Documentation Support............................17
5.3 Recommended Operating Conditions.........................4 8.1 Device Support......................................................... 17
5.4 Thermal Information....................................................4 8.2 Receiving Notification of Documentation Updates....17
5.5 Electrical Characteristics.............................................5 8.3 Support Resources................................................... 17
5.6 Typical Characteristics................................................ 6 8.4 Trademarks............................................................... 17
6 Detailed Description........................................................7 8.5 Electrostatic Discharge Caution................................17
6.1 Overview..................................................................... 7 8.6 Glossary....................................................................17
6.2 Functional Block Diagram........................................... 7 9 Revision History............................................................ 17
6.3 Feature Description.....................................................8 10 Mechanical, Packaging, and Orderable
6.4 Device Functional Modes............................................8 Information.................................................................... 18
7 Application and Implementation.................................... 9

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4 Pin Configuration and Functions

D PACKAGE PW PACKAGE
(TOP VIEW) (TOP VIEW)

INPUT 1 8 NC INPUT 1 8 NC
OUTPUT 2 7 OUTPUT NC 2 7 NC
OUTPUT 3 6 OUTPUT NC 3 6 OUTPUT
ADJUSTMENT 4 5 NC ADJUSTMENT 4 5 NC

NC – No internal connection NC – No internal connection

OUTPUT terminals are all internally connected.

PK PACKAGE LP PACKAGE
(TOP VIEW) (TOP VIEW)

3 INPUT 1 INPUT

2 OUTPUT 2 OUTPUT

1 ADUSTMENT 3 ADUSTMENT

Table 4-1. Pin Functions

NAME D PW LP PK TYPE(1) DESCRIPTION
ADJUSTMENT 4 4 3 1 I Output feedback voltage
INPUT 1 1 1 3 I Input supply voltage
No connect. Recommended to ground pins
NC 5, 8 2, 3, 5, 7, 8 — — — for improved thermal performance but not
required.
OUTPUT 2, 3, 6, 7 6 2 2 O Regulated output voltage

(1) I = Input; O = Output

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5 Specifications
5.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Legacy chip 35
Vl – VO Input-to-output differential voltage V
New chip 40
TJ Operating virtual-junction temperature 150 °C
Legacy chip –65 150
Tstg Storage temperature °C
New chip –55 150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

5.2 ESD Ratings

VALUE UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC Legacy chip ±3000

JS-001, all pins(1) New chip ±2000
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
±2000
pins(2)

(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

MIN MAX UNIT
Legacy chip 1.25 32
VO Output voltage V
New chip 1.25 37
Legacy chip 2.5 32
VI – VO Input-to-output voltage differential V
New chip 2.5 37
IO Output current 2.5 100 mA
Legacy chip 0 125
Operating virtual-junction LM317LC
TJ New chip –40 125 °C
temperature
LM317LI Legacy and new chip –40 125

5.4 Thermal Information

LM317L
D LP PK PW
THERMAL METRIC(1) 8 PINS 3 PINS 3 PINS 8 PINS UNIT
Legacy New Legacy New Legacy New Legacy
Chip(2) Chip Chip(2) Chip Chip(2) Chip Chip(2)
RθJA Junction-to-ambient thermal resistance 97.1 96.5 139.5 156.7 51.5 44 149.4
RθJC(top) Junction-to-case (top) thermal resistance 48.6 80.6 86.9
RθJB Junction-to-board thermal resistance 34.8 8.5
ΨJT Junction-to-top characterization parameter 5.9 24.7 4.5 °C/W

ΨJB Junction-to-board characterization 34.2 135.8 8.5

parameter
RθJC(bot) Junction-to-case (bottom) thermal resistance 6.9

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
note.
(2) Legacy chip only RθJA values reported.

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5.5 Electrical Characteristics

Unless otherwise noted, specifications over recommended operating virtual-junction temperature range, VI – VO = 5V and IO
= 40mA, P ≤ rated dissipation, measured with a 0.1μF capacitor across the input and a 1μF capacitor across the output.
PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
TJ = 25°C Legacy and new chip 0.01 0.02
Line regulation VI – VO = 5V to 35V IO = 2.5mA to %/V
Legacy and new chip 0.02 0.05
100mA
VO = 10V, f = 120Hz Legacy and new chip 65
Ripple rejection VO = 10V, 10μF capacitor between dB
Legacy and new chip 66 80
ADJUSTMENT and ground
VI – VO = 5V to 35V, TJ = VO ≤ 5V Legacy and new chip 25 mV
25°C,
IO = 2.5mA to 100mA VO ≥ 5V Legacy and new chip 5 mV/V
Output voltage regulation
VI – VO = 5V to 35V, VO ≤ 5V Legacy and new chip 50 mV
IO = 2.5mA to 100mA VO ≥ 5V Legacy and new chip 10 mV/V
Output voltage change with
TJ = 0°C to 125°C Legacy and new chip 10 mV/V
temperature
After 1000 hours at TJ = 125°C and VI –
Output voltage long-term drift Legacy and new chip 3 10 mV/V
VO = 35V
Output noise voltage f = 10Hz to 10kHz, TJ = 25°C Legacy and new chip 30 μV/V

Minimum output current to Legacy chip 1.5 2.5

VI – VO = 35V mA
maintain regulation New chip 3.5 5
3V ≤ VI – VO ≤ 13V Legacy and new chip 100 200
Peak output current Legacy chip 100 200 mA
VI – VO = 35V
New chip 25 50 150
ADJUSTMENT current Legacy and new chip 50 100 μA
Change in ADJUSTMENT
VI – VO = 5V, IO = 40 mA 0.2 5 μA
current
Legacy and new chip
Reference voltage (output to
VI – VO = 5V, IO = 40 mA 1.2 1.25 1.3 V
ADJUSTMENT)

(1) For all tests unless otherwise noted, power dissipation ≤ 1.4W in PK, D, and PW packages and ≤ 0.625W for LP package. Pulse-
testing techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.

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5.6 Typical Characteristics

Unless otherwise noted, specifications over recommended operating virtual-junction temperature range, VI – VO = 5V and IO
= 40mA, P ≤ rated dissipation.
70 70

65 65
Adjustable Pin Current (A)

Adjustable Pin Current (A)

60 60

55 55

50 50

45 45

40 40

35 35

30 30
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Te mperature (°C) Te mperature (C)

Figure 5-1. Change in Adjustment Current Over Temperature Figure 5-2. Change in Adjustment Current Over Temperature
(Legacy Chip) (New Chip)

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6 Detailed Description
6.1 Overview
The LM317L is a 100mA linear regulator with high voltage tolerance up to 37V. The device has a feedback
voltage that is relative to the output instead of ground. This ungrounded design allows the LM317L device to
have superior line and load regulation. This design also allows the LM317L device to be used as a current
source or current sink using a single resistor. Any output voltage from 1.25V to 32V can be obtained by using
two resistors. The bias current of the device, up to 2.5mA, flows to the output; this current must be used by the
load or the feedback resistors. The power dissipation is the product of pass transistor voltage and current, which
is calculated as shown in Equation 1.

PD = (VIN – VOUT) × IOUT (1)

The application heat sink must be able to absorb the power calculated in Equation 1.
In addition to higher performance than fixed regulators, this regulator offers full overload protection, available
only in integrated circuits. Included on the chip are current-limiting and thermal-overload protection. All overload-
protection circuitry remains fully functional even when ADJUSTMENT is disconnected. Normally, no capacitors
are needed unless the device is situated far from the input filter capacitors, in which case an input bypass
is needed. An optional output capacitor can be added to improve transient response. ADJUSTMENT can
be bypassed to achieve very high ripple rejection, which is difficult to achieve with standard three-terminal
regulators.
In addition to replacing fixed regulators, the LM317L regulator is useful in a wide variety of other applications.
Because the regulator is floating and observes only the input-to-output differential voltage, supplies of several
hundred volts can be regulated as long as the maximum input-to-output differential is not exceeded. The primary
application is that of a programmable output regulator, but by connecting a fixed resistor between ADJUSTMENT
and OUTPUT, this device can be used as a precision current regulator. Supplies with electronic shutdown can be
achieved by clamping ADJUSTMENT to ground, programming the output to 1.25V, where most loads draw little
current.
The LM317LC is characterized for operation over the virtual junction temperature range of 0°C to 125°C. The
LM317LI is characterized for operation over the virtual junction temperature range of –40°C to 125°C.
6.2 Functional Block Diagram
Input

Iadj

1.25V
Over Temp &
Over Current
Protection
Adj.

Output

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6.3 Feature Description

6.3.1 NPN Darlington Output Drive
The NPN Darlington output topology provides naturally low output impedance and an output capacitor is
optional. To support maximum current and lowest temperature, a 2.5V headroom is recommended (VI – VO).
6.3.2 Overload Block
Overcurrent and overtemperature shutdown protects the device against overload or damage from operating in
excessive heat.
6.3.3 Programmable Feedback
An op amp with a 1.25V offset input at the ADJUST pin provides easy output voltage or current (not both)
programming. For current regulation applications, use a single resistor whose resistance value is 1.25V / IOUT
and power rating is greater than (1.25V)2 / R. For voltage regulation applications, two resistors set the output
voltage. See the Typical Application section for a schematic and the resistor formula.
6.4 Device Functional Modes
6.4.1 Normal operation
The device OUTPUT pin sources current necessary to make the OUTPUT pin 1.25V greater than the ADJUST
terminal to provide output regulation.
6.4.2 Operation With Low Input Voltage
The device requires up to a 2.5V headroom (VI – VO) to operate in regulation. With less headroom, the device
can drop out and the OUTPUT voltage is the INPUT voltage minus the dropout voltage.
6.4.3 Operation at Light Loads
The device passes the bias current to the OUTPUT pin. The load or feedback must consume this minimum
current for regulation or the output can be too high.
6.4.4 Operation In Self Protection
When an overload occurs, the device shuts down the Darlington NPN output stage or reduces the output current
to prevent device damage. The device automatically restarts when the over current is removed. The output can
be reduced or cycle thermal shutdown on and off until the overload is removed.

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7 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

7.1 Application Information

The two output resistors are the only components required to adjust VOUT.
7.2 Typical Application
LM317L
VI VO
Input Output

Adjustment R1
470 W
C1 = 0.1 µF C2 = 1 µF

R2

Figure 7-1. Typical Application Schematic

7.2.1 Design Requirements

1. Use an input bypass capacitor if the regulator is far from the filter capacitors.
2. For this design example, use the parameters listed in Table 7-1.
3. Using an output capacitor improves transient response, but is optional.
Table 7-1. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Input voltage range (Output voltage + 2.5V) to 32V
Output voltage VREF × (1 + R2 / R1) + IADJ × R2

7.2.2 Detailed Design Procedure

7.2.2.1 Input Capacitor
An input capacitor is not required, but is recommended, particularly if the regulator is not in close proximity
to the power-supply filter capacitors. A 0.1µF ceramic or 1µF tantalum provides sufficient bypassing for most
applications, especially when adjustment and output capacitors are used.
7.2.2.2 Output Capacitor
An output capacitor improves transient response, but is not needed for stability.
7.2.2.3 Feedback Resistors
The feedback resistor sets the output voltage using Equation 2.

VREF × (1 + R2 / R1) + IADJ × R2 (2)

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7.2.2.4 Adjustment Terminal Capacitor

The optional adjustment pin capacitor improves ripple rejection by preventing the amplification of the ripple.
When this capacitor is used and VOUT > 6V, a protection diode from adjust to output is recommended.
7.2.2.5 Design Options and Parameters
Common linear regulator designs are concerned with the following parameters:
• Input voltage range
• Input capacitor range
• Output voltage
• Output current rating
• Output capacitor range
• Input short protection
• Stability
• Ripple rejection
7.2.2.6 Output Voltage
VO is calculated as shown in Equation 3.

æ R ö
VOUT = VREF ´ ç 1 + 2 ÷ + (IADJ ´ R2 )
è R1 ø (3)

Because IADJ typically is 50µA, this parameter is negligible in most applications.

7.2.2.7 Ripple Rejection
CADJ is used to improve ripple rejection. This capacitor prevents amplification of the ripple when the output
voltage is adjusted higher. If CADJ is used, include protection diodes to prevent ADJ from reverse-biasing when
VOUT collapses quickly.
7.2.2.8 Input Short Protection
If the input is shorted to ground during a fault condition, protection diodes provide measures to prevent
the possibility of external capacitors discharging through low-impedance paths in the device. By providing
low-impedance discharge paths for C3 and C2, respectively, a protection diode across the input to the output
and a protection diode across ADJ to the output prevent the capacitors from discharging into the output of the
regulator.
7.2.3 Application Curve

1.3
40qC
0qC
1.28 25qC
125qC
VADJUSTMENT (V)

1.26

1.24

1.22

1.2
0 6.25 12.5 18.75 25 31.25 37.5 42.5
VI VO (V) D001

Figure 7-2. Adjustment Voltage Relative to Output Over Temperature (Legacy Chip)

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7.3 System Examples

7.3.1 Regulator Circuit With Improved Ripple Rejection
C2 helps stabilize the voltage at the adjustment pin, which helps reject noise. Diode D1 exists to discharge C2 in
case the output is shorted to ground.
LM317L

VI Input Output VO
D1†
Adjustment R1 =
1N4002
C1 = 470 W
0.1 µF +
R2 = + C3 = 1 µF
10 kW C2 = 10 µF −
−

Figure 7-3. Regulator Circuit With Improved Ripple Rejection

7.3.2 0V to 30V Regulator Circuit

In the 0V to 30V regulator circuit application, the output voltage is determined by Equation 4.

æ R + R3 ö
VOUT = VREF ç 1 + 2 ÷ - 10 V
è R1 ø (4)
LM317L
35 V Input Output VO

Adjustment
R1 = 120 W

C1 = 0.1 µF −10 V
R3 = R2 = 3 kW
820 W

1N4002

Figure 7-4. 0V to 30V Regulator Circuit

7.3.3 Precision Current-Limiter Circuit

This application limits the output current to the ILIMIT shown in Figure 7-5.
LM317L
VI Input Output Ilimit = 1.25
R1
R1
Adjustment

Figure 7-5. Precision Current-Limiter Circuit

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7.3.4 Tracking Preregulator Circuit

The tracking preregulator circuit application keeps a constant voltage across the second LM317L in the circuit.
R2 = 1.5 kΩ

R1 = 470 Ω
Adjustment

VI Input Output
LM317L
LM317L
Input Output VO
Adjustment R3 = 240 Ω
C1 = 0.1 µF
C2 = 1 µF

Output R4 = 2 kΩ
Adjust

Figure 7-6. Tracking Preregulator Circuit

7.3.5 Slow-Turn On 15V Regulator Circuit

The capacitor C1, in combination with the PNP transistor, helps the circuit to slowly start supplying voltage. In
the beginning, the capacitor is not charged. Therefore, output voltage starts at 1.9V, as determined by Equation
5. As the capacitor voltage rises, VOUT rises at the same rate. When the output voltage reaches the value
determined by R1 and R2, the PNP is turned off.

VC1 + VBE + 1.25V = 0V + 0.65V + 1.25V = 1.9V (5)

LM317L

VI Input Output VO = 15 V
Adjustment R1 =
470 Ω 1N4002

R3 = 50 kΩ

R2 = 5.1 kΩ
2N2905 C1 = 25 µF

Figure 7-7. Slow-Turn On of the 15V Regulator Circuit

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7.3.6 50mA Constant-Current, Battery-Charger Circuit

The current-limit operation mode can be used to trickle charge a battery at a fixed current as determined by
Equation 6. VI must be greater than VBAT + 3.75V.

ICHG = 1.25V ÷ 24Ω (6)

(1.25V [VREF] + 2.5V [headroom]) (7)

LM317L
24 Ω
VI Input Output
Adjustment

Figure 7-8. 50mA Constant-Current, Battery-Charger Circuit

7.3.7 Current-Limited 6V Charger

As the charge current increases, the voltage at the bottom resistor increases until the NPN starts sinking
current from the adjustment pin. The voltage at the adjustment pin drops, and consequently the output voltage
decreases until the NPN stops conducting.
LM317L
VI Input Output
Adjustment
240 Ω

1.1 kΩ ICHG

VBE
VBE R =
I CHG
V−

Figure 7-9. Current-Limited 6V Charger

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7.3.8 High-Current Adjustable Regulator

This application allows higher currents at VOUT than the LM317L can provide, while still keeping the output
voltage at levels determined by the adjustment-pin resistor divider of the LM317L.
TIP73

2N2905
500 W

VI 5 kW
LM317L
22 W
Input Output VO
Adjustment
120 W 1N4002

10 µF
RL 47 µF
5 kW
10 µF

Figure 7-10. High-Current Adjustable Regulator

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7.4 Power Supply Recommendations

The LM317L is designed to operate from an input voltage supply range between 2.5V to 32V greater than the
output voltage. If the device is more than six inches from the input filter capacitors, an input bypass capacitor,
0.1µF or greater, of any type is needed for stability.
7.5 Layout
7.5.1 Layout Guidelines
• Bypass the input pin to ground with a bypass capacitor.
• The optimum placement is closest to the VIN of the device and the GND of the system. Care must be taken
to minimize the loop area formed by the bypass capacitor connection, the INPUT pin, and the GND pin of the
system.
• For operation at a full-rated load, use wide trace lengths to eliminate IR drop and heat dissipation.
7.5.2 Layout Example

COUT OUTPUT
Ground

R2
Power
OUTPUT
ADJ/GND

INPUT

High
High Input
Frequency
Bypass
Bypass
Capacitor 0.1μF 10μF Capacitor
Cadj R1
Ground

Figure 7-11. Layout Diagram

7.6 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the linear regulator when in circuit on a typical PCB board application. These metrics are not thermal
resistance parameters and instead offer a practical and relative way to estimate junction temperature. These
psi metrics are determined to be significantly independent of the copper area available for heat-spreading. The
Section 5.4 table lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT)
and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating
the junction temperature (TJ), as described in the following equations. Use the junction-to-top characterization
parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate the junction
temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1mm
from the device package (TB) to calculate the junction temperature.

T J = TT + Ψ JT × PD (8)

TJ = TT + ψJT × PD (9)

where:
• PD is the dissipated power
• TT is the temperature at the center-top of the device package

T J = TB + Ψ JB × PD (10)

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where:
• TB is the PCB surface temperature measured 1mm from the device package and centered on the package
edge
For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package
Thermal Metrics application note.

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8 Device and Documentation Support

8.1 Device Support
8.1.1 Device Nomenclature

Device Nomenclature
PRODUCT(1) VOUT
x is the operating temperature range designator.
yyy is the package designator.
z is the package quantity designator.
LM317Lxyyyz Devices ship with either the legacy chip (CSO: SHE) or the new chip (CSO:
TID). The reel packaging label provides CSO information to distinguish which
chip is used. Device performance for new and legacy chips is denoted
throughout the data sheet.

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
8.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

8.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (October 2014) to Revision F (December 2024) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Added terminology to identify legacy and new chip information throughout document......................................1
• Updated Pin Functions table to include correct pin information......................................................................... 3
• Added 3V ≤ VI – VO ≤ 13V rows to Peak output current parameter in Electrical Characteristics table.............. 5
• Deleted second footnote from Electrical Characteristics table........................................................................... 5
• Added Device Support section......................................................................................................................... 17

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Changes from Revision D (October 2011) to Revision E (October 2014) Page

• Added Device Information table, Pin Functions table, Handling Ratings table, Thermal Information table,
Typical Characteristics, Detailed Description, Application and Implementation, Power Supply
Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable
Information sections............................................................................................................................................1
• Deleted Ordering Information table.................................................................................................................... 1

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

18 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: LM317L

 PACKAGE OPTION ADDENDUM

www.ti.com 8-Mar-2025

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LM317LCD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 L317LC Samples

LM317LCDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM 0 to 125 L317LC Samples

LM317LCDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 L317LC Samples

LM317LCLP ACTIVE TO-92 LP 3 1000 RoHS & Green SN N / A for Pkg Type 0 to 125 L317LC Samples

LM317LCLPR ACTIVE TO-92 LP 3 2000 RoHS & Green SN N / A for Pkg Type 0 to 125 L317LC Samples

LM317LCLPRE3 ACTIVE TO-92 LP 3 2000 RoHS & Green SN N / A for Pkg Type 0 to 125 L317LC Samples

LM317LCPK ACTIVE SOT-89 PK 3 1000 RoHS & Green SN Level-2-260C-1 YEAR 0 to 125 LA Samples

LM317LCPKG3 ACTIVE SOT-89 PK 3 1000 RoHS & Green SN Level-2-260C-1 YEAR 0 to 125 LA Samples

LM317LCPW ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 L317LC Samples

LM317LCPWE4 ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 L317LC Samples

LM317LCPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 L317LC Samples

LM317LCPWRG4 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 125 L317LC Samples

LM317LID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 L317LI Samples

LM317LIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 L317LI Samples

LM317LIDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 L317LI Samples

LM317LILP ACTIVE TO-92 LP 3 1000 RoHS & Green SN N / A for Pkg Type -40 to 125 L317LI Samples

LM317LILPR ACTIVE TO-92 LP 3 2000 RoHS & Green SN N / A for Pkg Type -40 to 125 L317LI Samples

LM317LIPK ACTIVE SOT-89 PK 3 1000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 LB Samples

LM317LIPKG3 ACTIVE SOT-89 PK 3 1000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 LB Samples

LM317LIPW ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 L317LI Samples

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 8-Mar-2025

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LM317LIPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 L317LI Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Feb-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM317LCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
LM317LCDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
LM317LCPK SOT-89 PK 3 1000 180.0 12.4 4.91 4.52 1.9 8.0 12.0 Q3
LM317LCPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
LM317LIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
LM317LIDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
LM317LIPK SOT-89 PK 3 1000 180.0 12.4 4.91 4.52 1.9 8.0 12.0 Q3
LM317LIPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Feb-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM317LCDR SOIC D 8 2500 340.5 338.1 20.6
LM317LCDRG4 SOIC D 8 2500 340.5 338.1 20.6
LM317LCPK SOT-89 PK 3 1000 340.0 340.0 38.0
LM317LCPWR TSSOP PW 8 2000 367.0 367.0 35.0
LM317LIDR SOIC D 8 2500 353.0 353.0 32.0
LM317LIDRG4 SOIC D 8 2500 353.0 353.0 32.0
LM317LIPK SOT-89 PK 3 1000 340.0 340.0 38.0
LM317LIPWR TSSOP PW 8 2000 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Feb-2025

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
LM317LCD D SOIC 8 75 507 8 3940 4.32
LM317LCPW PW TSSOP 8 150 530 10.2 3600 3.5
LM317LCPWE4 PW TSSOP 8 150 530 10.2 3600 3.5
LM317LID D SOIC 8 75 507 8 3940 4.32
LM317LIPW PW TSSOP 8 150 530 10.2 3600 3.5

Pack Materials-Page 3
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
PW0008A SCALE 2.800
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

C
6.6 SEATING PLANE
TYP
6.2

A PIN 1 ID 0.1 C
AREA
6X 0.65
8
1

3.1 2X
2.9
NOTE 3 1.95

4
5
0.30
8X
0.19
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE

0.75 0.15
0 -8 0.05
0.50

DETAIL A
TYPICAL

4221848/A 02/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

8X (1.5)
8X (0.45) SYMM
(R0.05)
1 TYP
8

SYMM

6X (0.65)
5
4

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221848/A 02/2015
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

8X (1.5)
SYMM (R0.05) TYP
8X (0.45)
1
8

SYMM

6X (0.65)
5
4

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:10X

4221848/A 02/2015
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
LP0003A SCALE 1.200 SCALE 1.200
TO-92 - 5.34 mm max height
TO-92

5.21
4.44

EJECTOR PIN
OPTIONAL
5.34
4.32

(1.5) TYP

(2.54) SEATING
2X NOTE 3 PLANE
4 MAX
(0.51) TYP
6X
0.076 MAX
SEATING
PLANE
3X
12.7 MIN

0.43
2X 0.55 3X
3X 0.35
2.6 0.2 0.38
2X 1.27 0.13
FORMED LEAD OPTION
OTHER DIMENSIONS IDENTICAL STRAIGHT LEAD OPTION
TO STRAIGHT LEAD OPTION

2.67
3X
2.03 4.19
3.17
3 2 1

3.43 MIN

4215214/B 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Lead dimensions are not controlled within this area.
4. Reference JEDEC TO-226, variation AA.
5. Shipping method:
a. Straight lead option available in bulk pack only.
b. Formed lead option available in tape and reel or ammo pack.
c. Specific products can be offered in limited combinations of shipping medium and lead options.
d. Consult product folder for more information on available options.

www.ti.com
 EXAMPLE BOARD LAYOUT
LP0003A TO-92 - 5.34 mm max height
TO-92

FULL R
0.05 MAX (1.07) TYP
ALL AROUND METAL 3X ( 0.85) HOLE
TYP TYP

2X
METAL
(1.5) 2X (1.5)

2X
SOLDER MASK
OPENING
1 2 3
(R0.05) TYP 2X (1.07)
(1.27)
SOLDER MASK
(2.54)
OPENING

LAND PATTERN EXAMPLE

STRAIGHT LEAD OPTION
NON-SOLDER MASK DEFINED
SCALE:15X

0.05 MAX ( 1.4) 2X ( 1.4)

ALL AROUND METAL
TYP 3X ( 0.9) HOLE

METAL

2X
1 2 3 SOLDER MASK
(R0.05) TYP
(2.6) OPENING
SOLDER MASK
OPENING (5.2)

LAND PATTERN EXAMPLE

FORMED LEAD OPTION
NON-SOLDER MASK DEFINED
SCALE:15X

4215214/B 04/2017

www.ti.com
 TAPE SPECIFICATIONS
LP0003A TO-92 - 5.34 mm max height
TO-92

13.7
11.7

32
23

(2.5) TYP 0.5 MIN

16.5
15.5

11.0 9.75
8.5 8.50

19.0
17.5

2.9 6.75 3.7-4.3 TYP

TYP
2.4 5.95
13.0
12.4

FOR FORMED LEAD OPTION PACKAGE

4215214/B 04/2017

www.ti.com
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