SN74HCS573

ZHCSP24A – OCTOBER 2021 – REVISED DECEMBER 2022

具有施密特触发输入、三态输出和直通引脚排列的 SN74HCS573 八路透明 D

类锁存器

1 特性 3 说明
• 宽工作电压范围：2V 至 6V SN74HCS573 包含八路 D 类锁存器所有输入均包括施
• 施密特触发输入可实现慢速或高噪声输入信号 密特触发架构。所有通道共享锁存器使能 (LE) 输入和
• 低功耗 输出使能 (OE) 输入。此器件具有直通引脚排列，便于
– ICC 典型值为 100nA 进行总线布线。
– 输入漏电流典型值为 ±100nA
• 电压为 6V 时，输出驱动为 ±7.8mA 器件信息
• 更宽泛的工作环境温度范围： –40°C 至 +125°C， 器件型号 封装(1) 封装尺寸（标称值）
TA RKS (VQFN, 4.50 mm × 2.50 mm
20)
2 应用 SN74HCS573
DGS (VSSOP, 5.10 mm × 3.00 mm
20)
• 并行数据存储
• 数字总线缓冲器 (1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

Low Power Noise Rejection Supports Slow Inputs

Voltage
Voltage

Voltage

Input Voltage

Input
Input

Input

Waveforms
Input Voltage Time Time

Voltage
Standard
Voltage
Supply Current

CMOS Input
Output
Output

Current
Current

Response
Waveforms Input Voltage Time Time

Schmitt-trigger
Voltage

Voltage
Supply Current

CMOS Input
Output

Output
Current

Current

Response
Waveforms Time Time
Input Voltage

施密特触发输入的优势

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCLS876
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Table of Contents
1 特性................................................................................... 1 8.2 Functional Block Diagram........................................... 9
2 应用................................................................................... 1 8.3 Feature Description.....................................................9
3 说明................................................................................... 1 8.4 Device Functional Modes..........................................10
4 Revision History.............................................................. 2 9 Application and Implementation.................................. 11
5 Pin Configuration and Functions...................................3 9.1 Application Information..............................................11
Pin Functions.................................................................... 3 9.2 Typical Application.................................................... 11
6 Specifications.................................................................. 4 10 Power Supply Recommendations..............................14
6.1 Absolute Maximum Ratings ....................................... 4 11 Layout........................................................................... 14
6.2 ESD Ratings .............................................................. 4 11.1 Layout Guidelines................................................... 14
6.3 Recommended Operating Conditions ........................4 11.2 Layout Example...................................................... 14
6.4 Thermal Information....................................................4 12 Device and Documentation Support..........................15
6.5 Electrical Characteristics ............................................5 12.1 Documentation Support.......................................... 15
6.6 Timing Characteristics ................................................5 12.2 接收文档更新通知................................................... 15
6.7 Switching Characteristics ...........................................6 12.3 支持资源..................................................................15
6.8 Operating Characteristics .......................................... 6 12.4 Trademarks............................................................. 15
6.9 Typical Characteristics................................................ 7 12.5 Electrostatic Discharge Caution..............................15
7 Parameter Measurement Information............................ 8 12.6 术语表..................................................................... 15
8 Detailed Description........................................................9 13 Mechanical, Packaging, and Orderable
8.1 Overview..................................................................... 9 Information.................................................................... 16

4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (October 2021) to Revision A (December 2022) Page
• 将“应用信息”更改为“量产数据”.................................................................................................................. 1
• Added DGS (SSOP) Package Information......................................................................................................... 3
• Added DGS package Thermal Information.........................................................................................................4
• Updated the Detailed Design Procedure section..............................................................................................13

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5 Pin Configuration and Functions

OE VCC
OE 1 20 VCC
1 20
1D 2 19 1Q 1D 2 19 1Q
2D 3 18 2Q 2D 3 18 2Q
3D 4 17 3Q 3D 4 17 3Q
4D 5 16 4Q 4D 5 16 4Q
5D 6 15 5Q
5D 6 PAD 15 5Q
6D 7 14 6Q
6D 7 14 6Q
7D 8 13 7Q
7D 8 13 7Q
8D 9 12 8Q
GND 11 8D 9 12 8Q
10 LE 10 11
GND LE
图 5-1. DGS Package 图 5-2. RKS Package
20-Pin VSSOP 20-Pin VQFN
Top View Top View

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
OE 1 Input Output enable for all channels, active low
D1 2 Input Input for channel 1
D2 3 Input Input for channel 2
D3 4 Input Input for channel 3
D4 5 Input Input for channel 4
D5 6 Input Input for channel 5
D6 7 Input Input for channel 6
D7 8 Input Input for channel 7
D8 9 Input Input for channel 8
GND 10 — Ground
LE 11 Input Latch enable
Q8 12 Output Output for channel 8
Q7 13 Output Output for channel 7
Q6 14 Output Output for channel 6
Q5 15 Output Output for channel 5
Q4 16 Output Output for channel 4
Q3 17 Output Output for channel 3
Q2 18 Output Output for channel 2
Q1 19 Output Output for channel 1
VCC 20 — Postive supply
The thermal pad can be connect to GND or left floating. Do not connect to any other signal
Thermal Pad — or supply.

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
IIK Input clamp current(2) VI < 0 or VI > VCC ±20 mA
IOK Output clamp current(2) VO < 0 or VO > VCC ±20 mA
IO Continuous output current VO = 0 to VCC ±35 mA
ICC Continuous current through VCC or GND ±70 mA
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/
±4000
JEDEC JS-001(1)
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per ANSI/ESDA/
±1500
JEDEC JS-002(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 2 6 V
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
TA Ambient temperature –40 125 °C

6.4 Thermal Information

SN74HCS573
THERMAL METRIC(1) RKS (VQFN) DGS (VSSOP) UNIT
20 PINS 20 PINS
RθJA Junction-to-ambient thermal resistance 83.2 130.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 82.6 68.7 °C/W
RθJB Junction-to-board thermal resistance 57.4 85.4 °C/W
ΨJT Junction-to-top characterization parameter 14.5 10.5 °C/W
ΨJB Junction-to-board characterization parameter 56.4 85.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 40.0 N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
2V 0.7 1.5
VT+ Positive switching threshold 4.5 V 1.7 3.15 V
6V 2.1 4.2
2V 0.3 1
VT- Negative switching threshold 4.5 V 0.9 2.2 V
6V 1.2 3
2V 0.2 1
ΔVT Hysteresis (VT+ - VT-) 4.5 V 0.4 1.4 V
6V 0.6 1.6
IOH = -20 µA 2 V to 6 V VCC – 0.1 VCC – 0.002
VOH High-level output voltage VI = VIH or VIL IOH = -6 mA 4.5 V 4 4.3 V
IOH = -7.8 mA 6V 5.4 5.75
IOL = 20 µA 2 V to 6 V 0.002 0.1
VOL Low-level output voltage VI = VIH or VIL IOL = 6 mA 4.5 V 0.18 0.3 V
IOL = 7.8 mA 6V 0.22 0.33
II Input leakage current VI = VCC or 0 6V ±100 ±1000 nA
ICC Supply current VI = VCC or 0, IO = 0 6V 0.1 2 µA
Ci Input capacitance 2 V to 6 V 5 pF

6.6 Timing Characteristics

over operating free-air temperature range (unless otherwise noted), CL = 50 pF
PARAMETER CONDITION VCC MIN MAX UNIT
2V 12 ns
tw Pulse duration LE high 4.5 V 6 ns
6V 6 ns
2V 18 ns
tsu Setup time Data before LE↓ 4.5 V 6 ns
6V 6 ns
2V 0 ns
th Hold time, Data before LE↓ 4.5 V 0 ns
6V 0 ns

OE

LE

xD

xQ

图 6-1. Timing diagram

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6.7 Switching Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See Parameter
Measurement Information. CL = 50 pF.
PARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN TYP MAX UNIT
2V 14.6 19.4
tt Transition-time Any Q 4.5 V 7.7 9.6 ns
6V 7.4 10.4
2V 24.5 33
D Q 4.5 V 9.9 14
6V 9.6 11
tpd Propogation delay ns
2V 24.5 33
LE Any Q 4.5 V 9.9 14
6V 9.6 11
2V 15 44
ten Enable time OE Any Q 4.5 V 7 22 ns
6V 6 18
Any Q 2V 12 30
tdis Disable time OE Any Q 4.5 V 9 20 ns
Any Q 6V 8 19

6.8 Operating Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Cpd Power dissipation capacitance per gate No load 20 pF

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6.9 Typical Characteristics

TA = 25°C

46 70
VCC = 2 V VCC = 2 V
44 VCC = 3.3 V 65 VCC = 3.3 V
42 VCC = 4.5 V VCC = 4.5 V
VCC = 6 V 60 VCC = 6 V
Output Resistance (:)

Output Resistance (:)

40
38 55

36 50
34 45
32
40
30
28 35

26 30
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25
Output Sink Current (mA) Output Source Current (mA)

图 6-2. Output Driver Resistance in LOW State 图 6-3. Output Driver Resistance in HIGH State
0.2 0.65
VCC = 2 V 0.6 VCC = 4.5 V
0.18
VCC = 2.5 V 0.55 VCC = 5 V
0.16
ICC ± Supply Current (mA)

ICC ± Supply Current (mA)

0.5
0.14 VCC = 3.3 V 0.45 VCC = 6 V
0.12 0.4
0.35
0.1
0.3
0.08 0.25
0.06 0.2
0.15
0.04
0.1
0.02 0.05
0 0
0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
VI ± Input Voltage (V) VI ± Input Voltage (V)

图 6-4. Supply Current Across Input Voltage, 2-, 图 6-5. Supply Current Across Input Voltage, 4.5-,
2.5-, and 3.3-V Supply 5-, and 6-V Supply

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7 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 2.5 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.

Test VCC tw
Point VCC
S1 Input 50% 50%
RL
From Output 0V
Under Test
图 7-2. Voltage Waveforms, Pulse Duration
CL(1) S2

(1) CL includes probe and test-fixture capacitance.

图 7-1. Load Circuit for 3-State Outputs
VCC VCC
Clock
50% Input 50% 50%
Input
0V 0V
tPLH(1) tPHL(1)
tsu th
VCC VOH
Data
50% 50% Output 50% 50%
Input
0V VOL

图 7-3. Voltage Waveforms, Setup and Hold Times tPHL(1) tPLH(1)

VOH
Output 50% 50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
图 7-4. Voltage Waveforms Propagation Delays
VCC VCC
90% 90%
Output
50% 50% Input
Control
10% 10%
0V 0V
tr(1) tf(1)
tPZL(3) tPLZ(4)
§ 9CC VOH
Output 90% 90%
Waveform 1 50% Output
S1 at VLOAD(1) 10% 10% 10%
VOL VOL
(3) (4)
tr(1) tf(1)
tPZH tPHZ
(1) The greater between tr and tf is the same as tt.
VOH
Output 90% 图 7-6. Voltage Waveforms, Input and Output
Waveform 2 50%
S1 at GND(2)
Transition Times
§0V

图 7-5. Voltage Waveforms Propagation Delays

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8 Detailed Description
8.1 Overview
The SN74HCS573 contains eight D-type latches. All inputs include Schmitt-trigger architecture. All channels
share a latch enable (LE) and output enable (OE) input.
When the latch is enabled (LE is high), data is allowed to pass through from the D inputs to the Q outputs.
When the latch is disabled (LE is low), the Q outputs hold the last state they had regardless of changes at the D
inputs.
If the latch enable (LE) input is held low during startup, the output state of all channels is unknown until the latch
enable (LE) input is driven high with valid input signals at all data (D) inputs.
When the outputs are enabled (OE is low), the outputs are actively driving low or high.
When the outputs are disabled (OE is high), the outputs are set into the high-impedance state.
The active low output enable (OE) does not have any impact on the stored state in the latches.
8.2 Functional Block Diagram
Shared Control Logic

OE

LE

LE
xD D Q xQ

One of Eight D-Type Latches

8.3 Feature Description

8.3.1 Balanced CMOS 3-State Outputs
This device includes balanced CMOS 3-State outputs. The three states that these outputs can be in are driving
high, driving low, and high impedance. The term "balanced" indicates that the device can sink and source similar
currents. The drive capability of this device may create fast edges into light loads so routing and load conditions
should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger
currents than the device can sustain without being damaged. It is important for the output power of the device to
be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute
Maximum Ratings must be followed at all times.
When placed into the high-impedance mode, the output will neither source nor sink current, with the exception of
minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output
voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected to
the node, then this is known as a floating node and the voltage is unknown. A pull-up or pull-down resistor can
be connected to the output to provide a known voltage at the output while it is in the high-impedance state. The
value of the resistor will depend on multiple factors, including parasitic capacitance and power consumption
limitations. Typically, a 10 kΩ resistor can be used to meet these requirements.
Unused 3-state CMOS outputs should be left disconnected.

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8.3.2 CMOS Schmitt-Trigger Inputs

This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are
typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table
from the input to ground. The worst case resistance is calculated with the maximum input voltage, given in the
Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics
table, using Ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics
table, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much
slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the
inputs with slow transitioning signals will increase dynamic current consumption of the device. For additional
information regarding Schmitt-trigger inputs, please see Understanding Schmitt Triggers.
8.3.3 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Electrical
Placement of Clamping Diodes for Each Input and Output.

CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.

VCC
Device

+IIK +IOK

Input Logic Output

-IIK -IOK

GND

图 8-1. Electrical Placement of Clamping Diodes for Each Input and Output

8.4 Device Functional Modes

表 8-1. Function Table
INPUTS(1) OUTPUT(2)
OE LE D Q
L H L L
L H H H
L L X Q0 (3)
H X X Z

(1) L = input low, H = input high, ↑ = input transitioning from low to

high, ↓ = input transitioning from high to low, X = don't care
(2) L = output low, H = output high, Q0 = previous state, Z = high
impedance
(3) At startup, Q0 is unknown

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9 Application and Implementation

备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

In this application, the SN74HCS573 is used to control an 8-bit data bus.
Outputs can be held in the high-impedance state, held in the last known state, or change together with the data
inputs, depending on the control inputs at LE and OE coming from the bus controller.
9.2 Typical Application

1D 1Q
2D 2Q
3D 3Q

3-State Output Buffers

4D 4Q
D-Type Latches

5D 5Q
6D 6Q
7D 7Q
8D 8Q
Input Data Bus Output Data Bus
OE
LE

LE
Bus Controller OE

图 9-1. Typical application block diagram

9.2.1 Design Requirements

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9.2.1.1 Power Considerations

Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics section.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the SN74HCS573 plus the maximum static supply current, ICC, listed in the Electrical Characteristics,
and any transient current required for switching. The logic device can only source as much current that is
provided by the positive supply source. Be sure to not exceed the maximum total current through VCC listed in
the Absolute Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74HCS573 plus the maximum supply current, ICC, listed in the Electrical Characteristics, and any transient
current required for switching. The logic device can only sink as much current that can be sunk into its ground
connection. Be sure to not exceed the maximum total current through GND listed in the Absolute Maximum
Ratings.
The SN74HCS573 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all of
the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to exceed
50 pF.
The SN74HCS573 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and
current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the HIGH state, the
output voltage in the equation is defined as the difference between the measured output voltage and the supply
voltage at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.

CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.

9.2.1.2 Input Considerations

Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. The unused inputs can be directly terminated if the
input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The drive current of the controller, leakage current into the SN74HCS573 (as
specified in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10-kΩ
resistor value is often used due to these factors.
The SN74HCS573 has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical
Characteristics. This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than VCC or ground is plotted in the Typical Characteristics.
Refer to the Feature Description section for additional information regarding the inputs for this device.

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9.2.1.3 Output Considerations

The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to the Feature Description section for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit; it will, however, ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the
SN74HCS573 to one or more of the receiving devices.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in MΩ; much larger than the minimum calculated previously.
4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.2.3 Application Curve
LE

D1

Q1

图 9-2. Example timing diagram for one channel

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10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
given example layout image.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example

VCC GND
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation

F Bypass capacitor
OE VCC placed close to the
device
1 20
1D 2 19 1Q
2D 3 18 2Q
Unused input
tied to GND 3D 4 17 3Q
4D 5 16 4Q Unused output
left floating
5D 6 GND 15 5Q
6D 7 14 6Q
7D 8 13 7Q

8D 9 12 8Q
10 11
Avoid 90° GND LE
corners for
signal lines

图 11-1. Example layout for the SN74HCS573 in the RKS Package

14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: SN74HCS573

 SN74HCS573
www.ti.com.cn ZHCSP24A – OCTOBER 2021 – REVISED DECEMBER 2022

12 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, HCMOS Design Considerations application report (SCLA007)
• Texas Instruments, CMOS Power Consumption and Cpd Calculation application report (SDYA009)
• Texas Instruments, Designing With Logic application report
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.6 术语表
TI 术语表 本术语表列出并解释了术语、首字母缩略词和定义。

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15

Product Folder Links: SN74HCS573
SN74HCS573
ZHCSP24A – OCTOBER 2021 – REVISED DECEMBER 2022 www.ti.com.cn

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: SN74HCS573

 重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款 (https:www.ti.com/legal/termsofsale.html) 或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。重要声明

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Copyright © 2021，德州仪器 (TI) 公司
 PACKAGE OPTION ADDENDUM

www.ti.com 15-Apr-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74HCS573DGSR ACTIVE VSSOP DGS 20 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HS573 Samples

SN74HCS573RKSR ACTIVE VQFN RKS 20 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HCS573 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 15-Apr-2023

OTHER QUALIFIED VERSIONS OF SN74HCS573 :

• Automotive : SN74HCS573-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Apr-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HCS573DGSR VSSOP DGS 20 5000 330.0 16.4 5.4 5.4 1.45 8.0 16.0 Q1
SN74HCS573RKSR VQFN RKS 20 3000 180.0 12.4 2.8 4.8 1.2 4.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Apr-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HCS573DGSR VSSOP DGS 20 5000 356.0 356.0 35.0
SN74HCS573RKSR VQFN RKS 20 3000 210.0 185.0 35.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
RKS 20 VQFN - 1 mm max height
2.5 x 4.5, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4226872/A

www.ti.com
 PACKAGE OUTLINE
RKS0020A SCALE 3.300
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

2.6 B
A
2.4

PIN 1 INDEX AREA

4.6
4.4

0.1 C

1.0 C
0.8
SEATING PLANE
0.05
0.00 0.08 C
1 0.1

2X 0.5 (0.2) TYP

10 11
14X 0.5
9 EXPOSED
12 THERMAL PAD

2X
3.5 3 0.1

2
19
0.30
1 20 20X
PIN 1 ID 0.18
(OPTIONAL) 0.5 0.1 C A B
20X
0.3 0.05

4222490/B 02/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RKS0020A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(1)
SYMM

1 20
20X (0.6)

2
19

20X (0.24)

(1.25)

SYMM
(3)
(4.3)

16X (0.5)

(R0.05) TYP

9 12

( 0.2) VIA
TYP
10 11
(2.3)

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL OPENING

SOLDER MASK METAL UNDER

OPENING SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4222490/B 02/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.

www.ti.com
 EXAMPLE STENCIL DESIGN
RKS0020A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

2X (0.95)

1 20

20X (0.6)
2
19

20X (0.24)

2X (1.31)

16X (0.5)

SYMM

(4.3)
(0.76)

METAL
TYP

9 12

(R0.05) TYP

10 11

SYMM

(2.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
83% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X

4222490/B 02/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Copyright © 2023，德州仪器 (TI) 公司