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MIL -STD. 275E

51 Ikrew!wr [?/,4

SUPERSEDING
MIL - STD - 275D
26 APRIL 1978
MIL : STD -1495
3 AUGUST 1973

MILITARY STANDARD
PRINTED WIRING
FOR ELECTRONIC EQUIPMENT
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MI L- ST D-275E
31 December 198L

DEPARTMENT Of OEFENSE
Washington, OC 20301

Printed ‘d Iring for Electronic Equipment

MI L-sTo-275E

1. This Military Standard is approved for use by all Departments and Agencies of
the Department of Defense.

2. Beneficial comments (recommendations, additions, deletions) and any pertinent

data which may be of use in improving this document should be addressed to: Naval
Electronic Systems Command, AlTN: EL EX-8111, Washington, OC 20363, by using the
self-addressed Standardization Oocument Improvement Proposal [00 Form 1426) appearing
at the end of this document, or by letter.

i{
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f41L. sTD-27s E
31 Ikcembcr 198L

CONTENTS

PAGE
Paragraph 1. SCOPE ---------------------------------------------
1.1 Puro Ose ----------------------------------------- 1
1.2 Class ificati on---------------------------------- 1

2. QfFERENCCO DOCUMENT S ------------------------------ 2

3. DE FINITl ON S-------------------------------------:- 4

4. GENERAL REQUIRE ME NT S ------------------------------ 5

4.1 Oesign feature s --------------------------------- 5
4.2 Documenta tion ----------------------------------- 5
4.3 Master drawing ------------------------------- --- 5
4.4 Printed-wiring assembly drawing ----------------- 7
4.s Production master ------------------------------- 7

5. OETAIL 90AR0 REQu IREMENTS -------------------------

5.1 Conductive patter n ------------------------------
5.2 Lands ------------------------------------------- 19
5.3 Hol es ------------------------------------------- 13
5.4 Eyelets and standoff terminal s ------------------ 14
5.5 Plated-through holes --------------------- ------- 14
5.6 Mater ial s ---------------------------------------
5.7 Printed-wiring board dimensi ens -----------------
5.8 Oetail board marking requiremen to ---------------
5.9 Quality conformance testing circui try -----------

6. OETAIL PART MOUNTING REQUIRE MENTS -----------------

6.1 Approved methods of attachment ------------------
6.2 Electrical part mount ing ------------------------
6.3 Con formal coating -------------------------------
Support -----------------------------------------
::: Oetai led assembly marking requiremen to ----------

APPENo Ix

Paragraph 10. SC OPE ------------------------------------------- 23

10. I P“r D05e --------------------------------------- 23

20. OESIGN CON SIOERATIOW S --------------------------- 23

20.1 0esi3n process tolerances and all Owance -------
20.2 Board dimension s ------------------------------ ;;
211.3 Dimensional stabili ty ------------------------- 23
20.4 Dielectric constant and dissipation facto r---- 23
20.5 Surface preparation of large conductive areas -- 23
20.6 High voltage facto rs --------------------------- 23

T49LES

Table 1. Conductor spacing --------------------------------- 9

11. Standard fabrication allowances for
plated-through hole dttachmcnt ------------------ 11
Ill. Standard fabrication allowances for surface
attach meat s ---------- --------------------- ------
IV. Clad ldminlt e;-------------------- . . . . . . . . . . . . . . . .
v. Conformance test circui try ------------------------
V1. CQmposite board design quiddnce -------------------

,.,. ,.
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.. . . . . . . ..-
nlL->l U- Z/>L
31 Lb2cember 198/.

FIGuREs

PAGE
Figure 1. Quality, conformance test circui try ----------------
2. Block diagram depictfng typical printed wiring
drawing relation ships ---------------------------
3. Use of grids in defining pattern requirement s-----
4. Conductor thickness and width ---------------------
Oiscrete leadless component land pattern ----------
2: Chip carrier land patter n ------------------------ - 38
7. Modified fan out pattern s ------------------- ------
8. Heel mounting requirement s --------------- --------- ;;
9. TYP~cal flat pack l and ---------------------------- 40
10. Coined er flattened lead lands --------------------- 40
11. Annular ring requirements (External )-------------- 41
12. Annular ring requirements ( Interna l )--------------
13. Minimum annular ring dimensions (External )--------
14. Ground plane lands (typic a l)----------------------
15. Hole dia”eter for flat lead -----------------------
16. Dielectric layer thickness ❑ easurement ------------
17. Location of test coupon based on number of boards
fabricated per panel --------------------------- . 44
18. Flat lead terminate on ----------------------------- 45
19. Lead bend ---------------------------------------- - 46
20. Perpendicular part mount ing ----------------------- 46

iv
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HIL-STD-275E
31 December 1904

1. SCOPE

1.1 Purpose. This standard establishes desfgn requirements qoverninq rigid,

single --rinted-wiri ng boards, double-sided printed -wirfng boards, multilayered
printed-wiring boards, printed-wiring assemblies constructed from those boards
mentioned above, and design considerations for the ❑ounttng of parts and assemblies
thereon. The design criteria (such as electrical soacings) contained in this
standard are predicated on the requirement that end item assemblies [circuit card
assembl ies, printed-wiring assemblies, hack planes, mother boards) shall be
conformably coated (see 6.3.1). Con formal coating shall be in accordance with
HIL-l -45059.

l.? Classification. Printed-wiring boards shall be of the types shown, as

specified [see 4.2):

Type 1 - Single-sided board

Type 2 - Double-sided board
Type 3 - 14ultilayer board
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MIL. ST! I.275E
31 December 198A

2. REFE!4ENCEII 00CIJ14ENTS

2.1 Government documents.

I 2 .1.1 ~fcations, stand.irds, and handbooks. !Jnless otherwise specfffed, the

following specl Tl cations, standards, and handbooks, of the is Sue listed in that issue
of the Oeo,artment of Defense Index of SDecificatfons and Standards (n ODISS) SDecffied
in the solicitation, form a part of this standard to the extent specified herein.

SPECIFICATIONS

FEo ER4L

L-F-340 Yilm, Sensitized, Wash-Off Process, Oiazotype, Moist and

OrY pr0ce5s, Brown print, Roll and Sheet.
QQ.8-626 9rass, Leaded and NOnleaded Rod, Shapes, Forgings and Flat
Products with Finished Edges i8ar, Flat Mire and Strip).
Qq-B-750 Bronze, Phosphor Bar, Plate, koft, Sheet, Strip, Fl atwire,
and Structural and Special Shaped Sections.
QQ-c-576 Copper Flat Products with Slit, Slit and Edge-Rolled,
Sheared, Sawed, or Nachined Edges. (Plate, 8ar, Sheet, and
Strip).

gQ. N.290 !lickel Plating (Elect rodepositedl.

9Q-S-571 Solder; Tln Alloy; Lead-Tin A11oY: and Lead A11oY.

MILITARY

NIL- O-851O Orawings, ,lndimensio~ed, ReDroducibl es, Photo qraohic and

Contact, Preparation of.
MI L-P-13949 Plastic Sheet, Laminatei, 4etal -Clad (For Printed Wirinql.
General Specification for.
MI L-C-14550 Copper Plating (Electrofleoos itedl.
MI L-P-28909 Printed .Wi ring 4ssembli es.
MI L- G.45204 Gold plating, Elect redeposited.
HiL-i.46Ci53 insulating iompouna, Eiectricai (For Coating Printed
Circuit Assemblies).
MI L- P-5511O Prfnted-li iring 9oarrts.
!IIL-P-E11728 Plating, Tin-Lead, EIectrodeposi ted.

STAN DAROS

MILITARY

OOO-5TD-1OO Engineering Orawing Practices.

MI L- STO-130 Identification Marking of !J. S. Military Property.
000- ST D-1686 Electrostatic Discharge Control Program For Protection of
Electrical and Electronic Parts, Assemblies and fqufpment.

fCopfes of specifications, standards, drawings. and publications required by

manufacturers in connection with specific acquisition functions should be obtaine4
from the contracting activity or as directed by the contracting of ficer. )

2.2 Other publications. The following docunents form a part of this standard to
the extent tndlcatert herein. The issues of the documents which are indicated as 9q0
adopted shall be the issue listed in the current D’on[Ss and the supplement thereto,
if ao~licahle,

AMERICAY NAT ION4L $TANn ARnS INSTITUTE (ANSI)

AN SI. Y14.5 Oimensioninq and Tolerancing for Engineering Orawings.

AN S1-Y14. I Orawing Sheet Size and Format
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MI L. STD-275E
31 Oecember 1984

[Application for copies should be addressed to the hmerican !lational Standards

Institute, Inc. , 1430 Broadway, New york, My 10018. )

A3ER1C4N sOCIET7 FOR TESTING ANO MATERIALS (ASTq)

ASTM - E53 Standard Method for Che~ical Analysis of Copper

(Electrolytic Determination of Copper).

[A DPli Catf On for COl)ie S should be addressed to the America. Society for Testing and
Materials, 1916 Race Street, ‘hiladelohia. pA 19103. )

INsTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS (IEEE)

lEEE-STO-200(ANSI Y3?.16) - Reference designations for CIectrlcal and

Electronic Darts and Equipments.

(Application for coPies should be addressed to Institute of Electrical and

Electronics Engineers Service Center, ATTN: publication $al es, ~~~ Yose La IIe,
Piscataway. NJ 08854. )

INSTITUTE FOR Iv TERCflNNECTING ANO PACKAGING Electronic CIQCUITS (l PC)

IPC-T-50 Terms and Definitions.

IPC-CF-15fT Copper Foil for Printed qi ring fiDPlicati Ofls.
lPC-O.350 End Product Oescri Dtion in Numeric Form.
IPC-S-815 General Requirements for Soldering Electronic
Interconnections.
IPC-SM. B40 qualification and Performance of Permanent Polymer
Coating (Solder Mask) for Printed Boards.

(Application for copies should be addressed to the Institute for Interconnecting

and Packaging Electronic Circuits, 3451 Church Rd. , Evanston. IL 60203. )

2.3 Order of Precedence. In the event of a conflict between the text of this
stand aril and t he references cited herein, the text of this standard shall take
precedence.
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MIL-STD-275E
31 December 1984

3. DEFINITIONS

3.1 Terms and definitions. The terms and definitions used herein shall be in
accordance with this standard and IPC-T-50.

4
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141 L- ST O-275E
11 December 1986

4. GENERAL REOUIRIMENTS

4.1 Oe sign features. The design features of the printed-wiring boards shall be in
accordance with this standard. Quality conformance test circuitry shall also be
I included on the production master. OualitY COnf OrManCe test CfrCUi try shall be
included on each Panel and shall be in accordance with fi9ure I and 5.g. Test
circuitry shall be not more than 0.5 inch (13 mm) and shall be not less than 0.25
inch (6.4 mm) from the edge of the printed board, and represents all the
manufacturing processes such as driiling, plating, etching, fusing, ground lvoltagel
therms\/mechanical planes or cores, separately fabricated layers, permanent coatings
(solder mask) and so forth.

4.2 Documentation. Requirements for drawing content may be satisfied by direct

delineation on the drawing or by reference to other documents which are part of the
engineering drawing set (see figure 2.).

4 .2.1 Qeference designations. Reference designations of components to be mounted

on print eif-wlrlng boards, when specified on the ❑ aster drawing or the printed-wiring
assembly drawing, shall be in accordance with IEEE -S TO-200.

4. 2.2 Oevi ation request and app roval . When a deviation to this standard is
necessary, or has been granted in the initial contract design description, the
contractor (before proceeding furtherl shal I furnish each proposed master drawing, or
a detailed deviation request to the Government Agency concerned for approval with
justification for the deviation. If approved, all deviations granted shall be
documented on the master drawing.

4 .2.3 Governmeflt furnished master drawings. Any deviation from this standard or
drawing shall have been recorded on the Government approved master drawing or a
Government approved deviations list. When new or additional deviations from this
standard or drawing are necessary, the contractor (before processing further) shall
furnish one copy of each proposed master drawing being revised, or a detailed
deviation request to the Government Agency concerned for approval with justification
for the deviation. If approved, all deviations granted shall be documented on the
n~stcr d.a=i~g QV the Government approved deviations list.

4. 2.4 Conflicts. In the event of any conflict between the approved master drawing
supplemented by an approved deviation list, if applicable, and the requirement of
this standard. the apQr Oved master drawing and deviations list shall take precedence.

4.3 Master drawin~. The master drawing shall be prepared in accordance with
OOO-STO-1O O; shall incl tide ail appropriate detail board requirements (see section 5),
and the following:

a. The type, size, and shape of the printed-wiring board.

b. The size, location, and tolerance of all holes therein.
c. Ltchback allowances, when required or permitted.
d. Location of traceability marking.
e. Dielectric separation between layers.
f. Shape and arrangement of both conductors and nonconductor patterns defined
on each layer of the printed-wiring board. Copies of the production
masters or cop{es of the artwork may be used to define these patterns.
Separate views of each conductor layer.
Any and all pattern features not controlled by the hole sizes and locations
shall be dimensioned either specifically. or by reference to the qrid system
(see n).
i. Processing allowances that were used in the design of the printed -w~ring
board (see 5.1.1, 5.1.4, 5.2.1.2, 5.2.2. and 5.2.2.61.
j. All notes either included on the first sheet(s) of the master drawing or by
specifying the location of the notes on the first sheet.
k. Conductor layers numbered consecutively starting with the component side as
layer 1. If there are no conductors or lands on the component side, the
next layer shall be layer i. For assemblies with components on both sides.
the most densely populated side shall be layer 1.

5
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!fl L- STO-275E
31 December 198&

1. Identification marking see 5.8).

m. Size. sha!e. and locati n of reference designation a“d legend markings, if
reoui
–,–. red “[see . . . h)
n. k moduiir grid system to identify all holes, test points, lands, and overall
board dimensions with modular units of length of 0.100, 0.050, 0.025, or
other multiples of 0.005 inch in that order of preference. ,For design where
the majority component locations are metric-based (S1), the basic modular
units of length shall be 2.0, 1.0, 0.5, or other ~ultiples of 0.1 mm in that
order of preference. The grid system shall be applied in the X and ‘f axes
of the Cartesian coordinates. The grid shall not be reproduced on the
master drawing; but may be indicated using grid scales or X, Y control
dimensions (see figure 3).
0. Oimens$ons for critical pattern features which may effect circuit
performance because of distributed inductance or capacitance effects
within the tolerance required for circuit performance.
P. All terms used on the master drawing shall be in conformance with the
definitions of ANSI II PC-T-50 or ANSI V14.5 [see 3.1 and 2.2).
q. Obviations to this standard [see 4.2.21
r. +Iinimum Ii”e width and spacing of the finished printed-wiring board.
s. Maximum rated voltage lmaxim”m voltage between the two nonconnected
adjacent conductors with the greatest Dotential difference) for type 3
boards only.
t. Plating and coatfng material(s) and thicknesses).
u. Identification of test points required by the design (see 5.1.8).
v. Applicable fabrication specification with date(s), reyjsion letter, a“d
amendment number.

when continuation sheets of a drawing are used for conductor pattern definition,
they need not be prepared O“ standard drawing forms provided standard sheet sizes at-e
used with sta”ftard continuation sheet title blocks i“ accordance with ANSI Y14.1
located in the lower right corner of each sheet. Numeric form of end product
descriptions shall be in accordance with I PC-O-350.

4 .3.1 Hole location tolerance. Unless otherwise specified, the location of holes
shall ho a,mens, nneli w)?h ros?oct tn single 9. seen.davy grid systeqs. [arh
distinctive hole pattern {such as, plated-through holes, tooling hol es., mou”ti”g
holes, windows, access holes, and so forth), may require separate consideration-or
specification of tolerance. Producibility considerations are presented in table VI.

4. 3.2 Processing allowances. The processing allowances which were considered in

the design and artwork preparation for the printed-wiring board shall be documented
and defined on the master drawing i“ either note form or by reference to another
drawing which contains artwork requirements or specifications. This information
shall be expressed in terms of the maximum variation between the end-product
conductor widths and spacings and what may appear on the artwork; the minimum land,
in reference to the drilled or plated hole and what may appear on the artwork; or any
other feature conditions considered i“ the design where the variation between
end-product and artwork configuration play a role in the producibility of the
printed-wiring board.

4 .3.3 Oatunls. There shall he a !ni”imu!n of two datum features to establish the
mutually Perpendicular datum reference frame for each board. These datums shall be
established by at least two holes, points. symbols. or other datum features, but not
edges. Critical design features may require the use of more than one set of datum
references. The master drawing shall, establish the relationship and acceptable
tolerance between all datums teatures. All datum features shall be located on grid
or establish grid Criterion, as defined on the master drawing, and should be o“ or
within the outline of the printed-wiring boards.

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MI L.sTD-275E
31 lkcemb(?r 198$

4.4 Printed-wiring assembly drawing. The printed-wiring assembly drawing shall

cover printed-wiring on which separately manufactured parts have been added. The
printed-wiring assembly drawing shall be in accordance with DOD- ST D-1OO and should
include at least the fOl\Ouing:

a. Darts and material list.

b. Component mounting and installation requirements.
Cleanliness requirements per MI L-P-28809.
;; Location and identification of materials or components (or both).
Component orientation and polarity.
:: Applicable ordering data from HIL-P-28809.
9. Structural details when required for support and rigidity.
h. Electrical test requirements.
Marking requirements.
~~ Electrostatic discharge protection requirements.
k. Special solder plug requirements.
1. Eyelets and termina Is.
m. Lead forming requirements.
n. Type of con formal coating and masking.
o. Solder mask.
P. Traceability.

The printed-wiring assembly drawing shall inclu4e the definition of any conditions
considered in the design where the manufacturing variation between the end product
and assembly configuration play a role in the producibility or performance of the
printed-wiring assemblies.

I 4. 4.1
necessary,
Oeviat ion
or has been
request
granted
and ap proval.
In the Initial
When a deviation
contract design
to this standard
description,
is
the
contractor [before proceeding further) shall furnish each proposed assembly drawing,
or a detailed deviation request to the Government Agency concerned For approval with
justification for the deviation. If approved, all deviations granted shall be
documented on the assembly drawing.

4.4.2 Government furnished assemblv drawinrls. Any deviation from this standard or
the drawing shall have been recorded on the Government approved assembly drawing or a
Government approved deviations list. When new or additional deviations from this
standard 0. the drawing are necessary. the contractor (before proceeding further]
shall furnish one COPY of each proposed assembly drawing being revised, or a detailed
deviation request to the Government Agency concerned for approva) with justification
for the deviation. If approved, all deviations granted shall be documented on the
assembly drawing or the Government approved deviations list.

4.4.3 Conflicts. In the ?vent of any conflict between the aDPrOved assembly
drawing supplemented by an approved deviation list, if applicable, and the
requirement of this standard, the approvel assembly drawing an4 deviations list shall
take precedence.

4.5 Pr04u~tion master. Uh@” specified in the contract or purchase order, a produc-
tion master of each layer shall be Provided as part of the drawin9 set. Uhen a pro-
duction !Id Ster i5 not suPPlie4, the manufacturer shall be responsible for the
preparation of the production master with sufficient accuracy to meet the
requirements of the printed wiring detailed on the naster drauinq. The production
master shall be as defined in IPC-T -50 and shall be supplied or prepared on 0.0075
+0.0005 inch thick biaxially nri en ted, dimensionally stable polyester type film or
equal, in accordance with MI L-D-8510. type 11; L-F-IUD film. photographic subc13ss a,
class 2, type I or 1[, style 1A or photographic rj lass elates. The accuracy of the
production master (single image. multiple image, Or any associated quality assurance
I co,JPonsl
located
shall
within
be such
0.004 inch
that the
dianeter
lands,
of the
conductors:
true grid
and other
position
features
established
shall
for
be
the
layer, an4 that for the cnm?osite production master, the features of all layers shall
coincide within 0.006 inch diameter of the true grid position, when reed; ur.pd at 20-C
*l”c, and 50 *5 percent reldtive humidity after the .matr?rial has stabilized. 10 the
event that tighter tolerances are required in order to produce printed wiring, the
production master preci. ion requirements as considered in the design process, shall
be defined an the master drawing.

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)fIL-sTO-275E
31 twc.mnber 1986

5. DETAIL BOARO REQUIREMENTS

5.1 Conductor pattern.

5. 1.1 Conductor thickness and width. The width and thickness of conductors on the
finished printed-wiring board shall be determined on the basis of the current
carrying capacity required. The temperature rise shall be determined in accordance
with figure 4a for type 1, type 2, and external layers of type 3 boards, and figure
4b for internal layers of type 3 boards. For ease of manufacture and durability in
usage conductor width and spacing requirements shall be maximized while maintaining
the !aininun spa Cing requirements of table I. The minimum conductor width shown o“
the master drawing shall be not less than 0.004 inch [0.10 mm). To maintain the
conductor width shown on the master drauing, the line widths on the production master
shall be compensated for process allowances as shown {n 20.1 and table Vl of the
appendix.

5.1.2. Conductors tiith less than 90” included angle. All conductors that change
direction where the included angle is less than 90 sfiall have the external corners
of the conductor rounded.

5. 1.3 Conductors. The length of a conductor between any two lands “should be he!d
to a minimum. However, conductors which are straight lines and run in X, Y, or 45
directions in general are preferred to aid computerized documentation for mechanized
or automated layouts.

5. 1.4 Conductor spacing. Larger spacings shall be used whenever possible and the
minimum spacing between conductors, between conductor patterns, and between conduc-
tive materials (such as conductive markings or mounting hardware) and conductors
shall be in accordance with table 1, and defined on the master drawing. To ma{nt.ain
the conductor spacing shown on the master drawing, space widths on the production
master shall be compensated for process allowances IIS shown in 20.1 and table VI of
the appendix. Plat?d. through holes passing through internal foil planes [ground and
voltage) and thermal planes shall meet the same minimum clearance between the
plated-through hole and foil or ground planes as required for spacing between
internal conductors.

TABLE [. Conductor spacin~.

1 volt age between conductors I M1n Imum spacing i

DC or AC peak (volts) T Surface layers I Internal layers
1 r
o-1oo 10.005 inch (0.13 mm) 10.004 inch (0.10 mm) I
101-300 10.015 Inch (0.38 mm) 10.008 inch (0.20 mm) I
301-500 10.030 inch (0.76 mm) 10. O1O inch (0.253 ❑m) I
Greater than 500 AI 10.00012 inch (.00305 mm) 10.0001 inch [.002S mm)l
Iper volt Iper volt
/ I

~1 For reference only. voltages greater than 500 should be evaluated for the specific
design application.

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f41L-sTo-275[
31 Cecev,bcr 198.

5. 1.5 Edge spacinq. The ‘minimum spacing between conductive patterns and the edge
of the print ed-wirin board or any adjacent conductive surface, such as Supporting
structure or frames f nonmoving), shall be not less than the minimum SpaCfng specified
in table 1 plus .015 -inch (0.38 mm), provided the edges are protected from physical
harm in the installed assembly configuration. Drinted wiring not so protected shall
have a minimum conductor to edge distance of 0.050 inch [1.25 mm). The edge spacing
requirement is not applicable to heat sinks and ground planes. To maintain the edge
spacinq shaun on the master drawing, the ed e spacings shall be compensated for
process allowances as shown in 20.1 and tab 1 e V] of the appendix.

5. 1.6 Large conductive areas. Large conductive areas fncrease ‘the likelihood for
blisterin~ or bowing during the soldering opera tf on. The pattern and locat$on of
large conductive areas should be per 5. 1.6.1 and 5.1.6.2. Design of conductive areas
should provide balanced construction and include the use of nonfunctional copper, if
practical .

5. 1.6.1 Large external conductive areas. External conductive areas that extend
beyond a l-inch diameter circle should contain etched areas that will break up the
large conductive area but wfll retain the continuity and functionality of the
conductor. If etched areas are not provided, other methods should be uSed to mi n{-
mize blistering or bowtng. Large conductive areas should, if possible, be on the
component side of the board. If solder mask is em loyed, over melting Metal S.,

I conductive
mask, see
areas
IPC-SM-840
larger
and
than
20.5
0.050
of the
fnches
append i-.
wide sha ! 1 not be employed under the solder

5. 1.6.2 Large internal conductive areas [type 3). When a conductive area that
extends beyond a l-inch diameter circle IS used on an internal layer, the layer
should be placed as near the center of the board as possible and should contafn
etched areas that will break up the large conductive area but will retain the
continuity and functionality of the conductor. If more than one internal layer has a
large conductive area, the layers should be located in the board to provide balanced
construction. For surface preparation considerations see 20.5 of the appendix.

5. 1.7 Interracial connections. lnterfacial connections on type 2 and 3

>?infed.w,r,n.g boards shall be made by use of plated-through holes only. Uires
standoff terminals, eyelets, rivets, or pins shall not be used to provide interracial
connections.

5. 1.7.1 Solder fillets and plugs. Printed-wiring boards subjected to wave or dip
soldering sliall designed to facilitate flow of solder around component leads in
plated-through ho~es and into plated-through holes without leads, so as to create a
solder plug. Careful consideration shall be given to hole-to-lead diameter clearance
(see 5.3.2 and 5.5) hole to board thickness ratios and heat relief of metal planes to
promote solder plugging. In the event solder plugging due to natural capillary
action is not possible, such as when a heat sink is bonded directly over
plated-through holes, the desfgn shall include provision for prevention of solder,
flux or other chemicals from entering the plated-through hole. Solder may be
prevented from entering the holes by prebilling these holes with an appropriate
polymer plug, covering the holes with a sheet of permanent bonded material, tenting
the holes with a permanent solder mask or blocking these holes with some temporary
technique that will prevent solder access to the hole. All techniques must have
sufficient durability to not break up when e%p~sed to the solder process. The
printed-wiring assembly drawfng shall define the absence of such solder plug
requirements. As a mininmm solder plugs shall be required i“:

a. All electrically function~l and nonfunctional plated-through holes with a

lead; the lead is required to be surrounded 36o by the solder plug no matter
what technique for soldering is used.
b. Any plated-through hole without a lead, that is subject to wave or dlp
soldering with the degree and percentage of hole plugging described by the
appropriate assembl Y or sOlderfng specification [M IL-P -28S09, I PC-S-815).

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MI L.sTD. z75E
31 December 198b

Solder plugs are not necessarily required in:

a. hny unsupported hole without a lead.

b. Nonfunctional plated-through holes [hand soldered or vapor phase reflowed
assembly).
c. hny electrically functional pl~ted-throuqh ?ole (without a lead) not
subjected to wave or dfp soldering.
d. Any plated-through hole covered with permanent solder mask other polyqeric
cover layer (not Con formal coating] or is already filled w;th an appropriate
polymer in order to prevent hole access during wave or dip solder inq.
e. Any plated-through hole, electrically functional or not, wtthout a lead,
where access to the hole is limf ted by components, heat sinks. by design
[blind viasl, or where access of solder to the hole is prevented durinq the
solder process.

5. 1.9 Test oaints. when required by the design, test points for orobiftq shall be
provided as part of the conductor pattern and shall be identified on the master
drawing and the assembly drawing. These “probe points” shall require that a land be
available for probing as opposed to a conductor. Vias or component lead mo’unting
Ia”ds may be considered as probe points provided that sufficient area is available
for probing and maintaining the integrity of the via or component lead mounting
joint. Probe points shall meet the elating requirements of 5.5.4.

5.2 Lands. Lands shall be provided for each point of attachment of a part lea.i or
other e~cal connection to the printed-wiring board.

5. 2.1 Lands for through hole attachment. When through hole attachment is
required, all of the requirements of 5.Z sfiall be considered in the desiqn of the
printed-wiring board except where 5 .2.2 applies for surface attachment.

S. 2.1.1 Lands location. The lan4s shall completely surround and abut on the
mounting holes except where 5 .2.2 and 5 .2.5 applies.

S. 2.1.2 Through hole land area requirements. The mi~imuv diarqets. r of the land
surrounding an unsupported nole snail >e at least 0.1340 inch (1.02 m.ni greater than
the marinum diameter of the hole. When eyelets or standoff terminals are used, the
lands on type 1, type 2, and external layers of type 3 boards shal I be so designed as
to have a minimum diameter of at least 0. ’3?9 inch greater than the maxinun diameter
of the projection of the eyelet or standoff terminal flange. The minimum diameter of
a land surrounding a plated-through hole on type 2 and type 3 boards shall be
determined by considering the following:

a. Maximum diaveter of the drilled hole.

b. Minimum annular ring requirements “[see 5.2.3). Etch back. when required, will
reduce the insulation area that supports the internal land. The minimum
annular ring considered in the design shall be not less than the maximum
etch back allowed.
c. A standard fabrication allowance determined by statistical survey, which
considers pro.iuction master tooling and process variations required to
fabricate boards (see table 11].

10
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MI L- ST D-275E
II Ikccmbcr 198/.

TABLE II. Minimum standard fabrication allowances for plated-through hole attachment.

1 i I I Reduced r
lGreatest board lpanel dimension I Preferred I Standard producibility i
inches i riches I inches
{ I I r
IUP to 12 inches 0.028 0.020 I 0.012 Al
/ : I
1 I
IMore than 12 inches 0.034 I O.O24 I 0.016 ~1 I
/

The above considerations shall be incorporated into the minimum land area provided on
the production master such that: Minimum land diameter . a+2b+c. All lands anti
annular rings shall be maximized wherever feasible, consistent with good design
practice and elect rica! clearance requirements.

II For copDer weights greater than 1 ozlsq. ft., *dd D.002 inch m{ni~um to the
fabrication allowance for each additional ozlsq. ft. of copper used.

5. 2.2 Lands for surface attachment. Uhen surface attachment is required, all Of
the requirements of 5.2 shall be considered in the design of the printed-wiring board
except where 5. 2.1 and 5. 2.6 apply. The selection. design, and position of the land
geometry in relation to the part may significantly impact the solder joint. The
designer must understand the capabilities and limitations of the manufacturing and
assembly operations.

5. 2.2.1 Lands for end-capped discrete components. Discrete components, when

mounted as aeflned In 6.2.12 .3, shall have their land relationships identified as
shown on figure 5.

5. 2.2.2 Land o.sttern for leadless chip carriers. The attachment lands for surface
mounting Ieadless chip carriers should be the same width as the component terminal
(c J;til J:ioc ,7Jxintifi) p!u; 9.095 inch (0.0: mm ) . .hene.~er CO; ;ib le. The land lp~,.jth
should extend between 0.015 inch to 0.04 inch (0.38 to 1.02 mm) beyond the maximum
chip carrier outline o“ all four sides to create a horizontal soll~r fillet length
equal to the vertical fillet rise {see figure 6). The design of fan-out to
interconnect the haste land oattern to other circuit ryldevices is dependent on wiring
dens fty. testability, assembly, repairability, and routability requirements. Figure
7 shows some examples of possible fan-out patterns for leadless chip carriers. Chip
carrier land sites should be located on a fixed grid within the printed board to
optimize testing. This grid should be compatible with assembly and testing equipment
so as to minimize the amount of specialized and complex equipment necessary.

5. 2.2.3 Lands for leaded chip carriers. The land size for ceramic and for leaded
chip carriers should match the lead configurations. J shaped leads should have the
land width he equal to or 0.005 inch larger than the width of the lead. The land
length should extend between 0.015 inch to 0.040 inch (0.38 to 1.02 mm) beyond both
sides of the foot of the J pattern. Other types of leads used for chip carriers
should have the land commensurate with the lead configuration. in order to create a
horizontal solder fillet length at the toe and heel o; the lead configuration, .3s
shown on figure 8.
I 5.2. 2.4 Lands for ribbon Ieade/ surface mounted parts. The land requirements for
mountina ribbon leaded Ddrt S. such as Iat uack s”. ‘“audd vack s”. ur small outline
devices: shall preferably be rectangular. The mi”imurn land width shall be equal to
or exceed the maximum lead width by the amount shown on figure 8 providing room fOr
both solder fillets at both the heel and toe of the ribbon lead. The ~inimum land
width shall be approximately one and one-half times the width of the lead, or 0.005
inch (0.13 mm). whichever is less (see figure 9). Flat pack termination shall he
staggered to Permit greater spacing wherever possible. The center position of ribbon
leaded components should be on a fixed grid, wherever possible. to facilitate te!. ting.
I

II
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MI L- ST D-275E
31 IJcceu,bcr 1984

5. 2.2.5 Lands for flattened round leads. Flattened round leads shall have a land
which will provide the seating so that the heel and the terminal relationship is in
accordance with fi9ure 10. Leads shall be seated with no side overhang. Toe
provided that the flattened lead in contact with the terminal
.-
overhang is acceptable,
area is a minimum of 150 percent of the unflattered lead diameter and the overhang
does not reduce the spacing to adjacent parts to less than that specified on the
assembly drawing.

5.2.2.6 Lands for plated -thro,lgh holes (vfas for hoards with surface attached
m) . The ninimun diameter of a Ia”d surrounding a plated-through hole on type 2
and type 3 boards where surface attachment is used shall be determined by considering
the following:

a. Maximum diameter of the drilled hole.

b. Minimum annular iing (see 5.2.3). Etch back, when required, will reduce the
insulation that supports the internal land. The minimum annular ring
considered in the design shall be not less than the maximum etchback allowed.
c. A stan4ar4 fabrication allowance, determined by statistical survey, which
considers tooling production master and process variations required to
fabricate hoards (see table III).

TABLE 111. Minimum standard fabrication allowances for surface attachment.

I I I I Reduced r
lGreatest board lpanel dimension I Preferred I Standard producibility i
inches inches ! inches
I I I (
IIJP to 12 inches ‘0.026 t ~o. o18 I +0.010 Al
/ /
1 I
Ifiore than 12 inches ‘0.032 +0.022 +0.014 ~1 i
/ I

The above considerations shall 5e incorporated into the minimum land provided on the
master pattern such that: Minimum land diameter = a+2b+c. All lands and annular
rings shall be maximized wherever feasible, consistent with good design practice and
electrical clearance requirements.

1/ For copper #eights greater than 1 ozlsq. ft.. add 0.002 inch minimum tO the
fabrication allowance for each additional ozlsq. ft. of copper used.

5.2.3 Annular ring considerations. The ainimum annular ring on external layers is
the minimum amount of copper [at the narrowest point) between the edge of the hole
and the edge of the land after plating of the hole. The minimum annular ring on
internal layers is the minimum amount of copper (at the narrowest point) between the
edge of the drilled hole and the edge of the land after drilling the hole.

Extcr”al - The minimum annular ring for an unsupported hole shall be D.ol5
inch, The mininum annular ring for a plated-through hole in tyPe ?,
and external layers of type 3 boards shall be 0.002 inch, except
where the conductor joins the land the annular ring shall be 0.005
inch minimum (see figures 11 and 13).

Internal - The minimum annul ar”rinq for internal lands on type 3 boards shall
be 0.002 inch (see figure 12). Etch back, when required, will reduce
the insulation supporting the annular ring of internal lands. The
minimum annular ring considered in the design shall be not less than
the rnaxinum etch back allowed.

12
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MI L- ST O-275E
11 Ikcember 1986

5. 2.4 Nonfunctional lands (type 3, internal layers). Nonfunctional lands may be

included on Internal layers of type boards. hey need not be used where electrical
clearance requirements do ~ot permit, such as, ground planes, voltage planes and
thermal planes. Plated-through holes passing through internal foil planes (ground
and voltage) and thermal planes shall meet the same minimum spacing requirements as
that for conductors on internal layers [see table 1).

5. 2.5 Thermal relief in conductor planes. Thermal relief is only required for
holes that are subject to soldering. Connections associated with large conductor
areas (ground planes, voltage planes, thermal planes, etc. ) shall have a land that is
relieved locally in the area of the plated-through hole connection in a manner
similar to that shown on figure 14. !4hen electrical considerations preclude the use
of this technique, approval to deviate shall be obtained from the acquiring activity.

5. 2.6 Offset lands. Lands, when used in conjunction with clinched leads, may be
located aa jacent to (not surrounding) the lead termination hole. The land shall be a
sufficient distance from the hole to ai low clipping of the part lead prior to
unsoldering the part lead from the land.

5.3 ~.

5.3.1 Quantity. 4 separate component hole shall be provided for each lead or
terminal of a part or end of wire jumper except as specified in 5.2 and 6.2.14.

5. 3.2 Oi ameter of unsupported ho\es. The diameter of an unsupported terminal hole

shall not exceed by more than 0.020 inch (0.51 mm] and shail be not less ttian 0.006
inch (0.15 nm) the nom fnal diameter of the lead to be inserted, unless it is
clinched. The number of different hole sizes shall be kept to a minimum. When flat
ribbon leads are mounted through unsupported holes, the difference between the
nominal diagonal of the lead and the inside diameter of the unsupported hole shall
not exceed 0.020 inch (0.51 Tm) and shall be not less than 0.006 inch (0.15 mm), as
shown on figure 15.

I 5.3.3.
.3Pp*eved
Eyelet
by the
hole
Government
diameter.
acqu; ring
Eyelets shall
act. i.ity.
not be used
Uhen Pyelets
in new des(gn
are .sed, the
unless
diametev
of holes in which eyelets are inserted shall not exceed the outside diameter of the
barrel of the eyelet by more. than 0.006 inch (0.25 mm). The maximum inside diameter
of the eyelets shall be not more than 0.028 inch (0.71 mm) greater or less than 0.006
inch than the nominal diameter of the lead or terminal to be inserted in the eYel et,
unless the lead is clinched (see 6.1.2). Interconnections shall not be made with
eyelets.

5.3.4. Spacing of adjacent holes. The spacing of unsupported or plated-through

holes (or” both) shall be such that the lands surrounding the holes meet the spacing
requirements of 5.1.4. The spacing between adjacent holes of any other type shall be
not less than the printed-wiring board thickness or the hole diameter, whichever is
smaller.

5. 3.5 Location. 411 land and hole locations shall be at the grid intersections of
the modular (see 4.3) controlled by either primary or secondary
grid systemsdi%~s~~t~~f ~%~~m for printed wiring except as specified in 5.3.5.1.

5. 3.5.1 Pattern variations. Parts whose leads emanate in a pattern which vdries
from the grid Inter sections established by the master drawing shall be mounted or
attached to the printed-wiring board with one of the following hole patterns:

a. .4 hole pattern where the hole for at least one part lead is located at a
grid intersection of the modular dimensioning system and the other holes of
the pattern are Aimeosi oned from the grid location or from datum origin.
b. A hole pattern where the center of the pattern is located at a grid
intersection of the modular dimensioning system a“d all holes of the patter”
are dimensioned from that grid location or from datum origin.

11
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MI L. ST I-I. ?75E
31 I)ecemi,cr 198L

5.3.6 Indexing holes. if indexing holes are to a~pear on the printed-wiring

board, they shall be rllnensi oned on the master drawing.

5.4 Eyelets and standoff terminals. Eyelets and standoff terminals are to be
considered components and spec> fled on the assembly drawing.

I 5.4.1 Material. The eyelets shall he made of copper cctnfarming to OQ.C-576.

Standoff terminals shall be made of brass conforming to QQ-B-626 or bronze conforming
to qo-B.750.

5.4.2 Finish. The eyelets shall be ti”.lead plated and fused (se: 5.6.4.5). The
standoff terminal shall be finished in accordance with 5 .,6.4.5 or 5 .6.4.6 after
having bee” underplayed with 0.13001 inch (0.003 mm) minimum copper in accordance with
MI L-C-14550.

5.4.3 Flange design. The flange used to make elect rical. contact to the terminal
area shall be of the funnel flange type. The included angle of the flange shall be
between 35 and 120 degrees. The rolled or flat flange shall be used when there will
be contact with unclad material.

5.5 Plated-through holes. The maaimun diameter of the plated-through hole shall
not be more than 0.028 inch (0.71 MM) larger than the nominal of the inserted lead or
the nominal diagonal of a flat ribbon lead, as shown on figure 15. The minimum
diameter of the plated-through hole shall be not less than O.OO6 inch (0.15 mv)
larger than the nominal diameter of the inserted lead or nominal diagonal of a flat
ribbon lead. Unless otherwise specified, the hole size shall be the finished plated
Size after solder coating fJr solder Platinq. Plated-through boles used for
functional interracial Connections Jhal) not be used for the mounting of devices
which put the plated-through hole in compression. Plated-through holes used for
functional interracial connections shall not be used for the mounting of eyelets,
standoff terminals, or ri vets.. The thickness of electrolytic copper Dlating in the
hole shall be 0.001 inch (0.03 mm), minimum. The wallj of plate d-throu h holes shall
b? solder coated tsee 5.6.4.6) or tin/lead ul ated and fused (see 5.6.4. ! ) as Dart of
surface conductive cover requirements (see 5,6.4). Solder coating or tin-lead
plating dot-s not apply tn plat, d. through holes which are internal to the
printed-wiring board and do not extend to the surface. The end product diameter of
plated-through holes shall be specified on the master drawing.

5.6 Materials.
.— Printed-wiring Board designs shall be such that internal
temperature rise due to current flow i“ the conductor (see 5.1.1) when added to all
other sources of heat at the conduct orllaminate interface, Will not reSUlt in am
OPerating temperature in excess of that specified for the laminate material (see
table IV). $inCe heat dissipated by parts mounted on the boards will contribute
10cal heating effects, the material selection shall take this local factor plUS the
equipments general internal rise in temperature, plus the specified Opera t;ng ambient
temperature for the equipment into account. Hot spot temperatures shall not exceed
the temperatures specified in table IV for the laminate ~aterial selected. Materials
used (copper-clad. prepreg, copoer foil, heat sink, etc. ] shall be specified on the
master drawing.

5.6.1 Metal-Clad laminates. The Printed-wiring board$ shall be fabricated from

the metal-clad laminates specified in table 111 and copper foil types specified In
IPC-CF-150. The type of board(j) that each material may be used in is indicated in
table IV.
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HIL-STO-275E
31 Ikenber 198L

TABLE IV. glad laminates.

1 I I Uperatlng I Board type r

I Specification I Base material I temperature ~1 T 1 I 2 I 3 T

T 1 I I I I +
lf41L-P -13949 I 105” C” 1 X1X1-I
GE~xGF 2/ 125-C lx3/lx3/lxl
I I GE!, GH, GP, GT, GX: GR, GY ~ ) So”c lx-lx-lx!
G1 41 170” C .~xj//x~/lxl
I I I II

~1 Ambient temperature plus the temperature rise caused by CUr?eflt in the con-
ductors [see 5.1.1).
21 GE or GF laminates shall not be conbined in one board with Cl prepregs.
71 See 6.4.
II Uhen GI laminates are combined in one board with G[ or GF prepregs, the
temperature shall be 125-C.

5. 6.1.1 Minimum thickness of laminate. The thickness of the laminate per

MI L-P-13949 used in type 3 printed-wiring boards shall be .002 inch (0.05 mm) or
greater, provided the resulting dielectric layer in the finished board shall meet the
requirements of 5.7.4. The thickness of the Idmindte per MI L-P-13949, used in type J
and type 2 boards shall be as specified in the master drawing and shall meet the
requirements of 6.4 [see figure 16).

5. 6.2 Bonding materials.

5.6.2.1 Dreimpreqna ted bonding layer (prep reg). Orepreg used i“ type 3 printed-
wiring boards shall conform to type GC, GF, or Gf of !41L. ?-13949. Type GE or GF
preoreg shall not be used with type G1 prepreg. If a specific type of bonding
material is required, it shall be so specified on the master drawing.

5. 6.2.2 Other bonding films. Other bonding films such as cast resin films and
double side~ res)n coated polyimide films may be used to bond external heat Sinks.
internal thermal planes, or internal conductive planes provided the cured films meet
the temperature requirements of the base material as specified in table IV. 5.7.4,

I and on the mazter

5. 6.3 COPP er
drawing

circuitry layers. The thickness of finished copper conductors shall

be not less than 1 o.nc$ per square foot (0.0012 inches). Copper foil used shall be
not less than 1/2 Oztft and nust be plated up to the 1 ozifc requirement.
[pre~auti Onary note: A reduction of copper thickness after processing can be
expected. )

All external conductive patterns (plated-through holes, terminal

ar~~;;aet%%%;l be solder coated or tin-lead plated, ““less a permanent so,der
mask coating is used (see 5.6.5) or d heat sink is bonded to the external surface, or
other plating 1s approved by the acquiring activity. !+hen other platings are used on
the same printed -wlr!nq board in conjunction with solder coating or tin-lead Olatinq.
the area of overlap shall be kept to a minimum and no exposed copper shall be
permitted at the interface between the other plating and the solder coating or
tin-lead plating. ?Jo solder or tin plating shall be under other P]atinls. Unless
otherwise spec~fied on the master drawing, surface and pldted- through hole plating
thicknesses shall meet the requirements suecified in 5.6.4. I through 5.6.4.6.

5.6.4. I Elect roless copper plating. .tn elect roless deposition system shall be
used as a prel?ml nary process for providing the conductive layer over nonconductive
materials for subsequent elect redeposition of metal in plated-through holes.
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MI L- ST D-275E
31 Occcmber 1984

5. 6.4.2 Electrolytic copper plating. All electrolytically deposited copper

plating shall be performed In accordance with M IL-C-14550, and shall have a minimum
purity of 99.5 percent as determined by AS Tf4-ES3. The minimum thickness shall be
.001 inch (0.03 ~ml.

All electrolytically deposited gold shall be in accordance

wi~~’~~[?G~il, class 1. The minimum thickness shall be D,000D50 inch
(0.0013 mm); the maxinum thickness shall be 0.0001 inch (0.003 ram) on areas that are
to be soldered. A low stress nickel shall be used between gold overplanting and
covper (see 5.6.4.4).

5.6.4.4 Nickel plating. 411 electrolytically deposited nickel plating shall be

low stress and conform to QQ-N-290, class 2, except the minimum thickness shall be
.0002 inch ( .005 rim).

5.6.4.5 Tin-lead plating. Tin-1ead plating shall be in accordance ~ith

1 NIL-P-81728.
the surface.
The tin-lead
Fusing shall
shall
be required
be .0003
on all
inch [.008
tin-lead
mm) thick
plated
minimum,
surfaces.
as plated on

5 .6.4.6 Solder coatin . Unless otherwise specified, solder coating shall be in

accordance with composlt?on Sn60, Sn62, or Sn63 of 90-S-571. The solder coating
thickness shall be 0.0003 inch (0.008 mm) minimum, as coated (see 6.2.12 for surface
mounted components) .

5. 6.5 Solder mask. Polymer mask coatings shall ~eet the requirements of
IPC-S!4.840, class 3 and. when required, shall be specified on the master drawing.

5. 6.5.1 Solder mask over melting metals. Polymer mask coatings do not typically
adhere to molten metals. When coatings are required over melting metal [such as
solder) with areas of metal larger than 0.050 inch (1.3 mm) in two directions, the
design shall provide relief through the metal to the printed-wiring substrate. The
relief shall be at least 0.010 inch by 0.010 inch (0.25 mm by 0.25 mm) i“ size and
located on a grid no greater than 0.250 inch (6.4 mm].

5 ,6,5.2 Solder mack river nonmeltinn metals. When polymer mask coatinqs are
required over nonmelting metals (such as copper), the design shall provide that
conductor areas nOt covered by the mask shall be tinllead plated and fused (see
5.6.4.51 or solder coated (see 5.6.4.6). Eiondingladhesion promoters may be required
(See 20.51.

5.7 Printed-wiring board dimensions. The board design shall meet the requirements
specified in 5. 7.1 through 5.7.5.

5. 7.1 !3verall board dimensions. Overall printed-wiring board dimensions (length

and widthT. should coincide with lines of the modular dimensioning system.

5. 7.2 Roard thickness. The board thickness shall include metallic deposition,
fusing, and solder mask, shall be measured across the board thickness extremities,
and shall be as sp”ec if fed on the master drawing. In critical areas such as card
guides, the thickness requirements shall be detailed on the ❑aster drawing.

5. 7.3 Board thickness tolerance. The board thickness tolerance for types 1, 2,
and 3 shall be as specified on the master drawing.

5. 7.4 14inimum thickness of dielectric layers. Finished type 3 boards shall have a
minimum 0 . lnc . 8 nm o dlelectr>c material between the consecutive
conductor layers. when cured. Greater thicknesses should be considered for voltages
greater than 100 volts. The dielectric material will be in accordance with
II IL-P-13949 and may be comprised of laminate. prepreg and laminate, or multiple
layers of prepreg. There shall be no less than two sheets of prepreg (B-stage) or
laminate (C-stage), or combination thereof used between adjacent conductive layers.
Other bonding films and thicknesses shall be specified on the master drawing (see
5.6. 2.2 and figure 16).

NoTE: Thickness of dielectric layers shall be measured in accordance with

MI L- P-5511O.

#
-.

16
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MI L-STD-27E
11 December 1984

5.7.5 Bow and twist. Unless otherwise specified on the master drawing, the maximum allowable bow
and twist shall he 1.5 perrent.

5.8 Detail board marking require flents. lnfiivi.iual printed-wiring boards and quality conformance
test circuitry shall be identified in accordance with the master drawing and MIL-STD-130. Provision
shall b? made in the design for locating the traceability and date markings that are additionally
required by the fabrication specification. The methods and materials for marking shall be specified
on the master drawing. If ESD ❑arking is required at the board level, it shall be specified on the
master drawing. Xari.ing shall be of a contrasting color to the background.

5.9 Guality conformance testing circuit~. The quality conformance test cirkuitry, ccmprised of
the coupons shown on figure 1, shall be a part of every panel used to produce pri nted-wi ring boards
that are designed to this standard. The minimum number of coupons per panel and the requirements for
positioning will be in accordarcc with table V. Coupons A, B, and F shall be positioned in
accordance with 4.1 and figure 17. Al 1 other counons may be positioned at optional locations. Al 1
coupons required shal 1 be shcmn on the master drawi w, artwork, and production master.

TA9LE V. Conformance test circuitry.

1 Cou?on Type 1 I Type 2 I Type 3 I

I type board I board board
I I
1 h qot requ 1red IT wlce per panel opposl te iwice per panel opposite
I tiicro- Icorners location fixed bylcorners location fixed byl
I section I Iart’.mrk (see figure 17) iartwork (see figure i7) I

1 B IT wtce per pane7 opposite I Iwlce per panel opposite II wlce per panel opposite I
I 14icro- Icorners lwation fixed bylcorners location fixed bylcorners l~ation fixed byl
I section Iartbmrk (see figure 17) ~artwork (see figure 17) ~artwurk (see figure 17) I

1 c 10nce per panel lccation 10nce per panel location 10nce per panel location f
~ Plating Ioptional pattern defined ioptional pattern defined Ioptional pattern defined I
I by artwork I hy artwork Iby artwork
! I
1 D Not requ~ red ID nce per panel locatlon 10nce per panel l“ok~
I Thermal Ioptional pattern defined Ioptional pattern defined I
1 sheck Iby artwork Iby artwork
I
1 . lf Once per panel location I Once per pan~l locatlon 10nce per panel location
I Insulation Ioptional pattern defined [optional pattern defined Ioptional pattern defined ~
~resi stance Iby artwork I by a rtwnrk I by artwork
I I
~ :{ot requi red I Not required IT w{ce per panel opposfte
lReqisTration I Icomers location
I If i xed by artwork :
I I(see figure 1)
/ I I
~r Ilhen require , once per When required, once per
I S014er Ipanel with solder mask Ipanel with solder mask Ipanel with solder mask ~
I mask Ilocation optional Ilocation optional Ilocation optional
Ipattern fixed hy artwork Ipattern fixed by artwork ~pattern fixed by artwork 1
I

~1 If the panel has solder mask. the f ,coupon shall be covered with the solder mask.
Clearances of 0.010 TO.005 should be provided for all surface lands.
~1 Registration coupons are optional and may De uses In I leu of microsection evaluation for
regi strati on.

17
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f41L-sTcl-275E
31 Ikccmber 19s4

6. DETAIL PART MOUNTING REQUIREMENTS

6.1 Lpproved methods of attachment. Component leads s.ha\l pass throuqh lead
component holes and be attached or the component terminals or leads shall be surface
mounted to the land pattern. Part attachment shall be descrfbed on the assembly
drawing following the methods specified in 6. 1.2 through 6.1.5.4. General mounting
requirements shall be as specified in 6.1.1.

6. 1.1 Unclinched leads. Unless otherwise specified, unclinched leads (either

straigh L or partl all y bent for retention) shall be soldered in component holes or
eyelets in accordance with I PC-S-815. lf no clinching requirements are specified on
the assembly drawing, unclinched lead termination shall apply.

6. 1.1.1 [n unsupp orted holes. Lead tip projection shall be required to extend
from 0.020 ?nch (0.51 mm) mlnlmum to 0.060 inch (;.5 mm] maximum from the surface of
the foil.

6. 1.1.2 In plated-through or eyelet ted holes. The lead shall be required to

extend at least to the surface of the plating or rim of the eyelet and extend no more
than 0.060 inch (1.5 mm) from the plating surface or eyelet.

6 .1.2 Clinched leads. Ilhen maximum mechanical retention of a lead or terminal i!

required hy design, the lead or terminal shall be clinched. The component holes may
be plated-through holes, unsupported holes, or eyelet ted holes. Clinching
requirements shall be defined on the assembly drawing. The lead end shall not extend
beyond the edge of its land or its electrically connected conductor pattern in
violation of the rein{ mum spacing requirement. >art ial clinching of leads for part
retention shall be considered under the requirements of 6.1.1.

6. 1.3 Surface terminated ribbon leads. Flat-wire ribbon leads may be attached to
lands on the Drinted-wirinq board. Connections shall be made by solderinq only. The
contact area between any l~ad and land shall be not less than a-square haiing each
side equal to the nominal width of the lead (see figure 9). Minimum conductor
spacing indicated in 5. 1.4 shall be maintained. Attachne”t details may be conveyed
by an assembly drawing reference to lPC-S-815 (see figure 18). For additional
mounting notes and Cti0sider6Liun> s,e< 6. Z. ii.

6. 1.4 Surface terminated round leads. With prior approval by the government
acquiring actlvlty, designs may stipulate that parts shall be attached with their
round leads soldered to surface terminals (lands) without first passing through a
hole. The lands shall be designed with proper shape a“d spacing to comply with
proper soldering techniques (see I PC-S-815).

6. 1.5 Standoff terminals, eyelets, or fasteners.

6. 1.5.1 Component attachment to standoffs. Component attachment to standoff

terminals shall be defined on the assembly drawing and meet the requirements of
I PC-S-815. Placement of terminals shall be specified to suit each application.

6. 1.5.2 Attachment of standoffs to boards. A terninal of the funnel flanged type

shall be specltled wherever the tl ange must be soldered for electrical connection to
a land. The included angle of such flange shall be between 35 and 120 degrees.

6. 1.5.3 ~elets. Eyelet applications used in design shall be in compliance with

the following:

Attachment requirements - lnterfakial connections shall not be made with

eyelets. Eyelets installed aC dn electrically functional land shall be required
to be of the funnel flange type.

6. 1.5.4 Fastening harduar~. The installed location a“d installation orie”tdtio”

shall be prescribed on the assembly drawing for any fastening devices such .+s rivets,
machine screws, washers. inserts, nuts. Jnd bracketing. Precautions such as the
specification of tightening torque values shall be provided wherever general assembly
practices might be inadequate or detrimental to the board assembly’s structure or
functioning.
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MI L- ST D-275E
31 Ileccmbvr 1984

6.2 Electrical Part mou~. The following are requirements the designer shall
consider and detail on the assembly drdwing in specific notes or illustrations. 411
such electrical parts, hereafter referred to as components, shall also be selected so
as to withstand the vibration, fnechanical s?ock, humidity, and other environmental
condirioms the design must endure when the components are installed in accordance
with 6. 2.1 through 6.2.14.

Parts shall be mounted o? only one side of the

pr!;;~;-bf!%&&%%;Sembly WIIe”e”er FIOS.Sibl~.

6. 2.2 4ccessibilft~. Lands and termin)ls shall be located and spaced so that the
terminations of each component are not obscured by any other component, or by any
other permanently installed part%. [ach component shall be capable of being removed
from the assembly without having to remove any other COmDOnent.

6.2.3 Design envelope. Unless otherwise detailed on the assembly drawing, the
board edge is regarded as the e$.treme perimeter of the assembly, beyond which no
portion of d component is allowed to extend. The designer shall prescribe the design
envelope with due respect for maximum part body dimensions and the mounting
provisions dictated by the board and assembly documentation.

6. 2.4 Over conductive areas. No parts shall be mounted in dfrect contact with
external conductor areas unless required for thermal di5si Datf Qn. If design
limitations require placement of parts over conductive areas, the part shall be
mounted so that subsequent insulating coating will cover the conductive area under
the part or conductive areas under Darts shall be insulated or protected a9.3in St
moisture entrapment by applying conform.+] coating or a cured resin coating by
laminating low-flow prepreg material in accordance with t41L-P-13949, or by solder
masking over the area prior to nounting the part.

6.2.5 Thermal transfer. Components, which for thermal reasons require extensive
surface contact with the board or with d heat sink .nounted on the board. shall be
protected from processing solutions at the conductive interface. TO prevent risk of
entrapment. compatible materials and ~ethods shall be specified to seal the interface

NOTE: Even totally nonmetallic interfaces tha are prone to entrap fluids can
have adverse effects on the fabricator’ ability to pass required
I cleanliness tests.

6. 2.6 Components dissipating cne or more watts. Design for heat dissipation of
components shal I insure that the max)mum all owabl_e temperature of the board materia
is not exceeded under operating conditions specified in 5.6. heat dissipation may be
accomplished by requiring a gap bet. een board and component, using a clamp or thermal
mounting plate, or attaching a compatible, thermally conductive naterial working in
conjunction with a thermal bus plane to the component.

6. 2.7 Stress relief bends. Lands and terminals s$all be located by design so that
components can be mounted or provided with stress relief bends in such a manner that
the leads cannot overstress the part lead interface when subjected to the anticipated
en Vir On U!ent S Of temperature, vibration, and shock of MI L-P-28809. The lead length
for stress relief and ledd bend radius shall be in accordance with figure i9. Where
lead bending can not be in accordance uith figure 19 in order to achieve design
goals, the bends shall be detailed on the assembly drawing.

6. 2.8 ~echanical support. b,ll parts weighing 0.25 Ounce [7,1g) or mor? per lead
shall be supporteti by clamps or other specified means which will insure that the
soldered joints and leads are not relied upon for mechanical strength.

6. 2.9 4xi al-leaded parts. 4xial -leaded parts shail be mounted as specified on the
approved assembly drawing and mounted so that a portion of the body iS as close to
the printed-wiring hoard as possible. The leads shall be shaped in accordance with
6.2.7. This does not apply to parts mounted on standoff terminals (see 6.1.5.11.

19
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MI L-sTD.275[
31 Dcccmbcr 1984

6. 2.9.1 Perpendicular mounting. Axial -1eaded components weighing less than 0.50
ounce [14g) may be mounted on the assembly using perpendicular ❑ounting criteria.
The assembly drawing shall prescribe a minimum of 0.015 inch (0.38 !nm) space between
the end of the component body [or the lead-weld) and the board. Unless otherwise -t
noted on the assembly drawing, components required to be perpendicularly mounted
shall be installed with their major axis within *15 degrees of a right angle with
board surface. The naximum vertical height from the board surface shall be 0.55 inch
(14 mml [see figure 20).

6.2.10 Nonaxial- leaded parts. Nonaxial -leaded parts shall be mounted with the
surface from which the lead projects a minimum of 0.010 inch (0.25 mm) above the
printed-wiring board surface. Oimensioqing of the required spacing under these
components is generally not required unless the component package design could result
in an assembly error. For thermal considerations see 6. 2.5 and 6.2.6.

6.2.11 Multi ple-le aded components. Multiple-leaded components (components with

three or more leads}, except mult]ple leaded components mounted to thermal planes or
heat sinks, shall be mounted in such a manner that components are spaced off the
board to facilitate cleaning, provide electrical isolation, and to prevent moisture
traps. The necessary gap may be prescribed as an exceptional fabrication requirement
by identifying the subject component and prescribing the required underbody clearance
dimension or the gap may be achieved by v~rtue of the component’s own standoff
features. lJn less otherwise specified, a clearance of 0.010 inch (0.25 nm) minimum
.- .1,..
app, ,es.

6. 2.11.1 Spacers. Special spacers (such as feet, ribs, or projections] with

minimal contact may be prescribed to go under the component, provided they will not
ivpair soldering or the assembly’s performance.

6.2. 11.2 Seal in$. The need for a gap between component body and board may be
avoided by requiring the interface under the component to be sealed with adhesive or
a combination of adhesive and insulation material, which is compatible with tne
board. parts, and con formal coating. This option exists only if all lead
terminations are external to the seal. Repairability shall not be precluded by the
mcthnd or n:ter ial $electi~n.
. .
6.2.12 S,jrface mounted components. The req”ireme”ts and considerations of 6. 2.4
apply to this class of components. Space for cleaning shall be provided to reduce
entrapment.

6. 2.12.1 Flat-pack types with ribbon leads. Lead forming is a major design
consideration and shall be detailed on the assembly drawing to provide for lead
stress relief, fit to the land patter”, underbody clearance for cleaning. and any
designed-in provisions for thermal transfer (see figure 18 and 6.1.3).

6. 2.12.2 Chip carrier type. Leadless components may be attached to the surface of
a land. The component shall be attached to the land of the printed-wiring board in a
way that provides sufficient space under the body of the component to facilitate
cleaning. Land pattern design shall facilitate adeauate solder fillets between the
conductor pattern and the component.

6 .2.12.3 End-cap discrete components. End-cap discrete resistor a“d capacitor

components and similar lead less end-cap discrete components shall be mounted to
printed wiring or urintert circuitry. The devices shall not be stacked no. shall they
bridqe spacing between other parts or components, such as terminals or other
properly-mounted conponcnts.

6 .2.12.4 Surface mnunting of flattened r.a””d leaded components. Components with

da ial leads of round cross-sections shall be utilized for surface mounting only if
the leads are coined or flattened for positive receding. For flattened round leads
with original diameter of 0.025 inch (0.635 mm] or greater, the flattened thickness
shdll be 70 percent of the original diameter, minimum. For leads with an original
diameter less than the 0.025 inch [0.635 mm], the flattened thickness shall be 50
Percent of the original diameter, minimum. The body of a planar mounted axial leaded
component should be spaced away from the board to facilitate cleaning.

‘,_;

20
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MI L- STCS-275E
31 V.?CCti,r 1984

6.2.13 Two-part connectors (plug and receptacle). Two-part connectors containing

male and female quick disconnect electrical contacts and integral ali9nin9 hardware
to assure ProPer mating of the contacts s6all be s?ecified as the only means to inte-
grate plug-in printed-wiring assemblies. Their attachment and mounting methods dre
subject to the design concerns of 6.1 6.2.3, and 6.2.4. 9oard connectors may be
uniquely keyed in such a manner only ;nsertion of the proper assembly 1s possible.

6. 2.13.1 ‘Aires. Use of hard wiring directly to plug in connector mounted

printed -wiri~ard assemblies shall not be permitted. Plug in assemblies shall
have all external electrical connections accomplished through the. use of twO-part
connectors.

6.2.14 Jumper wires. Jumper wires may be used on types i, 2, or 3 printed-wiring

board assembles. Jumper wires shall be terminated in holes or standoffs. They may
also be terminated on lands with prior approval of the government acq Ui ring
activity. Jumper wires shall be considered a component. Jumper wires shall be as
short as practicable and shall not be applied over or under other replaceable
components [including jumper wires). Jumper wires must be permanently fixed to the
printed-wiring board at intervals not to exceed 1 inch. Jumper wires less than 0.50
inch in length whose path does not pass over conductive areas and does not violate
the spacing requirements [see 5.1.4) may be uninsulated. Insulation, when requi red,
or jumper wires shall be compatible with the con formal coati I19.

6.3 Con formal coatinq. The design criteria contained in this standard are
predicated on the requirement that end item assemblies shall be COnf Ormally coated.
solder mask shall flOt be used in lieu of con form.sl coating.

Printed-wiring assemblies sha)l be conformably coated with a

CO~i~i~ m%’%%i%”conforms to !41L-I-4605S3. The coating shall be applied to both
sides of the cleaned printed-wiring assembly including the part leads. The type of
con formal C0atin9 shall be listed on the assembly drawing.

6.3. 1.1 Surfaces to be free of coating. Surfaces specified on the approved

assembly drawing to be free of con formal coating shall be suitably masked and
?r@te~ted frOm ~0atin9, ~fi.+tin! residues, and masking residues. The masking material
used shall have no deleterious effects on the printed-wiring boards. Printed-wiring
assemblies having adjustable components shall not have the adjustable portion covered
with coating. Electrical and mechanical mating surfaces, such as probe points, screw
threads, bearing surfaces, and so forth shall not be coated.

6. 3.2 [leaning agents. Cleaning agents and techniques shall have no deleterious
effects on any part of the printed-wiring assembly.

6. 3.3 Compatibility. The con formal coating shall be compatible with all parts of
the printed-wiring assembly.

6. 3.4 Thickness. The thickness of the co” formal coating shall be as follows for
the type specified, when measured on a flat unencumbered surface:

d. Types ER, IJR, and AR: 0.003 .0 .002 inch (0.08 *0.05 ram).
b. TYpe sR: 0.005 *0.003 inch [0.13 ●0.08 mm).
c. Tyve XY: 0.0005 to 0.002 inch (0.010 to 0.05 ~ml.

6. 3.5 electrical performance. Printed-wiring assemblies shall be constructed,

adequately masked, or otherwise protected in such d manner that application of
con formal coating does not degrade the electrical performance of the assembly.

6 .3.6 D“ffer mdteri al. If components) on the printed-wiring assembly are made of
brittle material (~lass or ceramic) they shall be protected against breakage by a
buffer material be ore applying the”conformal coating to the assembly. The buffer
material shall be a thin. pliant material such as polyvinyl idene fluoride,
polyethylene terephtha late, or silicon rubber. and be nonreactive with the con formal
coating material and ali parts of the printed-wiring assembly. The buffer material
shall be fungus resistant and flame retardant, and clear or transparent, so markings
on the components are visible.

21
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MI L- ST D-275E
31 December 1986

6.3. 6.1 When required. When con formal coating types SR, XY, uR, and AR are used,
buffer material is not required. BUffer material will be required for type ER.

NDTE: Board designers are cautioned to consider that buffer material may be needed
when allocating
printed-wiring
space
boards
and location
covered by this
for components
standard.
to be mounted on -)
1
All print ed-w{ri”g assemblies shall be supported within a maximum of
1 ~;~h w;) of the edges on at least two opposite sides.. S.ppctrt shall be
sufficient to prevent fracture or loosening of the foil or breakage of the parts or

I part

6.5
leads resulting

Detailed assembly
from flexing

markinqs.
of the printed-wiring

Completed printed
boards.

wiring assemblies shall be

marked In accordance with the assembly drawing and MI L- STD-130 with their full
identification. Printed-wiring assemblies which Contain electrostatic discharge
sensitive devices shall be narked in accordance with DOO-STO-1686. The marking shall
be etched or applied by the use of a permanent ink which will withstand assembly
processing. tldditional markings if required shall be specified on the assembly
drawing.

“-f

22
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MI L- STD-275E
31 Cecember 1986

APPENDIX

10. SCOPE

10.1 Purpose. This appendix is for guidance to the designer of printed-wiring

boards.

20. DESIGN CO N$1OERATIONS

20.1 Oesign process tolerances and allowances. The data {n table VI shall serve
as a guise concerning the tolerances and .s1 Iowances used in the design process. Due
to tolerance buildup, the tradeoffs involved in arriving at the permissible limits
for each particular tolerance for a particul.zr design should be recognized. This
data is intended to show the increasing difficulty of producin boards with tighter
tolerances. but does not express the limits attainable or perm ? ssible for any single
aspeCt Of board design. This data shall not be interpreted as end item board
requirements.

20.2 Board dimensions. Extreme length-to-width ratios should be avoided.

20.3 Dimensional stability. ‘dhile HIL-P -13949 limits the allowable dimensional
change OT the thin lamlnate, consideration must be given to the fact that during
processing, the thin laminate may either expand or contract wfthin these limits, and
in addition, the change may vary across different portions of the board. The result
may be misregi strati on, and bow and twist beyond that which would be expected from a
simple dimensional change.

20.4 Dielectric constant and dissipation factor. h’hen designing circuits which
depend on stable dielectric properties, consideration should be given to the fact
that MI L-P-13949 sets forth only a maximum for these values and that some materials
which meet the thin laminate specifications will have values 15 percent lower than
the specification requirement.

20.5 Surface preparation of large conductive areas. The adhesion of prepregs and
other polymers, such as sold er mask to large conductive areas, ma { be im~roved
through the use of special materials and surface preparations. T e “se of adhesion
promoters, such as oxide treatments and double treated copper may improve the bonding
of type 3 printed-wiring boards. A protective chemical treatment may be reaui red to
prevent a reaction between the copper surface and the polymer coating.

20.6 High voltage factors (considerations):

a. Encapsulate with void-free potting materials, well bonded to all s“vfaces.

b. Avoid sharp projections.
c. Arrange conductors so that high and low voltage groups are separate from one
another.
d. Provide rounded corners on electrical conductors and ground planes next to
energized circuits.
e. In ac circuits, check adjacent conductors for instantaneous voltage
differences between them.
f. Con formal coating should consist of at least three separate layers, with each
layer applied at right angles to the previous layer.
9. Solder terminations on the printed-wiring board must be smooth and even with
no projections from the component lead or solder spikes.
h. Standoff terminal connections must be solder balled. The radius of the
solder ball should be at least 1/6 of the soacing between the solder ball and
adjacent high voltage circuit or ground plane. When large spacings are
involved, the solder ball should be at least .125 inch [3.1 ❑m) i“ diameter.

23
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MI L-STD-275E
31 December 198&
APPE1/DIX

TAoLE VI, Composite board design guidance.

/—
\
I Reduced
I Preferred Standard I producibility

~ ~
lNumber of conductDr layers
1 (maximum 11)------------- 6 12 I 20
lThickness OT total board
I (ma~inwm) (inch) --------- 0.100(2.54) 0.150 [3.81) i 0.200 [5.08)
lBoard thickness tolerance-- *102 Of above nmninal r 0.007(0.18), ,hichever is greater
lThickness of dielectric
I (miniumml ---------------- 0.008 [0.273) 0.006(0.15) 0.004(0.101
lt4inimn conductor width (or
I figure 4 value, whichever
I i s greater)
Internal --------------- 0.015 [0.38) 0.010(0.25) 0.004 [0.101
/ External --------------- 0.020(0.51) 0.015(0.38) 0.004(0.10)
I Cmductor width to erance
I Unplated 2 ozlft ~ -------- +0.004(0.101 +0.002(0.05) +0.001 [0.025)
-0.006 [0.15) -0.005(0.13) -0.003 [0.08)
I Unplated 1 oz/ft2-------- +0.002 [0.05) +0.001(0.025) +0.001( 0.025)
-0.003(0.08) -0.002(0.05) -0.001(0.025)
1
I Protective plated
(metallic e h resist
~ over 2 ozfft Y copper) --- +0.008 [3.20) ●O.O94(O.1O) +0.002(0.05)
-0.006(0.15) -0.004 [0. 10) -0.002(0.05)
itlinimu mco.fluctor spacing
I (or table 1. whichever.
I is greater) -------------- 0.020 [0.51) 0.010(025) 0.005(0.13)
Ihnular ring plated-through
I hole [mi?imum)
Internal --------------- 0.008(0.201 0.005(0.131 0.002[0.051
/ External --------------- 0.010(0.25) 0.008(9.20) o. CK15(o.13) ~/
lFeature location tolerance
I (master pattern, material
I movement, and registra-
/ tion [rtp)
Longest board dimension
I 12” or less ------------ 0.008(0.20) 0.007(0.181 0. CfJ6(0.15)
Longest board dimension
I o“~l. l~.---.--....---- 0.010 (0.2s) 0.009(0.23) 0.008(0.20)
lM.+ster pattern accuracy
I frtp)
Longest board dimension
i 12” or les. s------------ 0.004(0.10) 0.003(0.08) 0.002(0.05)
Longest board dimension
over lP --------------- 0.005(0.13) 0.004(0.10) 0.0’33( 0.08)
Feature size toleranc e.. :0.003(0.08) ti.002[0.05) +0.001(0.0251
lBoard thickness to plated
I hole diameter (maximum) --- 3:1 4:1 5:1
Itble IWation tolerance
I (rtD)
I Lbnge%t board dimension
12” or less-------------l 0.005 [0.13) 0.003 (G.081 0.002 [0.051 ~1
/ Longest hoard dimension I
D“er 1~-----......---.--i 0.007(0.181 0.005(0.13) 0.003(0.08) ~1
lUnplated hole diameter I
~ tolerance (unilateral)
UD to 0.032 (0.81 )-------1 0.034 [!3.10) 0.003(0.08) 0.0132 (f3.05)
I o:033(o.84 ):o.063(l.611-i 0.006(0.15) 0.004(0.10) 0.002(0.05)
0. C64(1.631-0 .18814.77)-I 0.008(0.20) 0.006(0.15) O. OO4(O.1OI

See footnotes at the end of table.

-.
 Downloaded from http://www.everyspec.com
MIL-STD-275[
31 Oecember 198G
APPENDIX

TA@lE VI. Canposite board design guidance - Continued.

T I I I Reduced
Preferred I Standard ~ Producibility
I I
1 I I I
lPldted hole diameter toler- I I
I ante (unilateral) for i
I minimm hole diameter I I /
I maximum board thickness I
I ratios greater than 1:4 I / !
~ add 0.004 (0.011 ;
0.015(0.38)-0.035(0.76) i 0.008[0.201 I 0.005(0.13) 1 0.004(0.10) I
0.031(0.79)-0.061(1.56) I 0.010 (0.2s) I 0.006(0.15) I 0.004 [0.10)
/ 0.062(1.59)-0.186(4.75) I 0.012(0.31) I 0.00810.20) I 0.006 [0.15) !
lConductor to edge of board I
I (mi nimwm) I I I
I Internal layer---- .-.-.-l 0.100(2.54) I 0.050(1.27) I 0.025(0.64)
i External layer----------i 0.100(2.54) I 0.100(2.54) ~ 0. IM(2.54) i

AI The nunber of conductor layers should be the optinum for the requi red board function
and good producfb(l ity.
21 See 5.2.3.
~1 To be used only in extreme sftuatiom warranted by the application.

I101E: Unless otherwise spec{fted, all dimensions and tolerances are in inches; data in
pa~ntheses ( ) \s expressed in mil 1 imeters.

25
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HIL-STD-275E
31 Oecember 19s4

t--”’OO—

L
MARKING
SEE NOTE 1

COUPON “A”

. +.020 .020-7

50

LOOOJ
7
iYPi CtiL OF Ytii?FACE C*. OF
T’(F’i
LAYERS AND IUTCRNAL See note 10 and 12 INTERNAL
CIRCUIT LAYERS PLANE
LAYERS

COUPON “B”

1. ——

● *O
,000,
L ~

T’f PltAL OF SURFAC[

,
LAYCNS ANO lNTIRNAL
TYPICAL Or
CIRCIJIT Lfif[l!S
INTIRNAL
PLAfl[ LAY[RS
See note 1?
,.-..
rlGuR[ 1. Uuality conformance test circuitry.

i’ b
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HIL-STD-275E
31 December 1984

COUPON “C”

0207 .020
7

‘ii
‘=”
200

r’=-F070
TYPICAL OF
SURFACE
TYPICAL OF
I14TERNAL
TYPICAL OF
LAYERS INTERNAL
CIRCUIT
TYPE 1, 2, 3 PLANi
LAYERS
BOAROS iYPE 3 LAYERS
TYPE 3
BOAAOS
EIoAR03
See Note 12

COUPON “D”

● 0’ ● *
p
-1
LAYER 1 LAYER 2 TVPICAL of
TVP[ 2 ANO 3 TYPE 2 ANO 3 ltlTERNAL
80ARoS BOAROS TYPICAL PLANE LAYERS
OF INTERNAL TYP[ 3 BOAROS
CIRCUIT LAYERS

See notes 8, 9,and 12.

FIGURE 1. Quality conformance test circuitry - Continued.

 Downloaded from http://www.everyspec.com

NIL-STD-275E
31 December 198L

COUPON “E”
.0201

rl 11 , r

●
. 1.000
. TYP
●
●

J L J
LAYE2 1 OF LAViR ? OF
TYPr 1, 2. TYP[ ? AND
A!ID 3 BOARDS 3 BOAROS
TYPICAL OF
INTERNAL TYPE 3
CIRCUIT BOARDS
LAY[RS

See Notes B, 11, and 1?.

-—
COUPON “ J“

+ .500+

LAYims O!lI. V 5CC lIULL-S 12 and 16.

TYPI. 1, 2
flNll ?, UOARIIS

FIGuRC 1. Quality conformance test circuitry - Contin.cd.

.,N
r
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MI L-STU-275E
31 Fmceukr 198L

COUPON “F”

r 1

Ill!i
++
100

T
3.

30
●2
●2
+2
+2

++
c
50 ● 4

1- J L J (c. )
LAYER 3
[a. ) (b. ) TYPICAL OF
SURFACE LAYERS, LAYER ? I1lTERNAL
TYPICAL IATERIIAL PLAIIE LAYER

I
I

r -1 r

++ 1

1- -1” 1-
2
++
+’

-1
I (e. )
(d. )
LAYER 4 LAYER 5
INTCRNAL Ii; TIRNAL

Laye,. -tu-l dyer reyistrdtiun (OpLi onal desiqn).

I

5ee notes 10 tl, ru 24

1 IGINII 1. Imdlity cvnfurma)c~ test circuitry - Cuntinued.

:Y
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MI L-STD-275E
31 Oecember 1984

10
1

Coupon F, layer-to-layer registration (optional design).

18

See notes 18 thru 24.

FIGuR[ 1. @al ity conformance test circuitry - Contiwed.

3U
 Downloaded from http://www.everyspec.com

NOTES: ..
1. Test coupons are to be identified with the followlng:
a. FSCM of board manufacturers.
b. Part number and revision letter of master drawing.
c. Board traceability and lot number.
2. Dimensions are in inches.
3. l@tric equivalents are given for general information only.
4. Unless otherwise specified, all conductors shall be .020 inch (0.51 mn) t.003 (0.08 mm)
wide.
5. Unless otherwise sDecified, the tolerances shall met the requirements of this
specification.
6. Unless otherwise specified, the minimum land dimension shall be .070 inch (1.78 mm)
:.005 inch (0.13 nun) and may represent the land shape used on the associated board.
Holes in the land areas shall be the diam?ter of the smallest component hole in the
associated board (see note 10).
7. Coupons for surface layers or internal layers shall be representative of the type of
circuitry on the associated layer. Any layer with large copper planes shall use the
appropriate plane coupon where applicable on the layer that is being represented by
the coupon.
8. The lengths of coupons O, E. and F are dependent upon the number of layers in the
panel.
9. For coupon O, a pair of holes and a conductor between Sam shal I be provided for
each Idyer. Electrical connection shall be in series, stEf?a’i Se, through each
conductor layer of the board.
10. For coupons A and B, the minic’um land dimension and shape shall be that used on the
associated board. The hole shall be the maximum used in this minimum land dimension.
Il. For coupon [, d pair of holes, and the conductor width and spacing shall be .025
?.005 inch.
12. The quality conformance test circuitry may be segmented; however, coupons A, B, and
F, when required, must be joined together. Coupons [, O, E, and J may be arranged
to optimize board layout. All test coupons illustrated when required must appear on
each panel. The number of layers must be identical to the associated board.
13. Etched letters on coupons are for identification purposes only.
14. The number of layers shown in these test coupons are for illustration purposes only.
Condtictor layer number 1 shall be the first layer on the component side, and all
other conductor layers shal 1 be counted consecutively downward through the laminated
board to the bottcm conductor layer which is the solder side.
15. For coupon F, the design is optional, provided the coupon defines the relationship of
the features on eaCh conductor layer to the board datum. For examples of coupons used
for registration evaluation of type 3 boards.
16. Coupon J is only required on board surfaces to be solder mask coated.
17. SPac ing between coupons may be modified to accommodate tool ing holes used for automatic
andlor multiple mounting microsectioning equipment.
18. The land dimension should represent the smallest land used for a component hole in the
associated board.
19. The holes in the lands should be the diameter of the smallest components in the
associated board.
20. The inside didreter of the circular lands should be design dimension minus 2 x .002
inch, (Additional allowances nay be made for the etch allowance .scd 1. the
dissociated board. )
?1. The clearance hole in the pldnes used for the specific Idyer evaluation should be
design diwns ion minus 2 r. .002 inch. All other clearances should be a minimum of
design dimension plus 2 x .00? inch. (Additional allowances may bc made for the
etch allowances used i. the associated board. ]
22. ihe conductor dimensions should be representative of tile dssoci. ted budrd.
?3. The coupon may be reduced or extended to accommodate the nutier of layers in .3 tYPe
3 board.
N . If continuity exists $etween comnonly number lands, the board dot% not meet the
minimum annular vi.,] rcquircm?nt of 1).002 inch.
2,, . Dark WI!,,, .,,, ,.,,l,.., !,!1, m,,, ,,l

11
 Downloaded from http://www.everyspec.com

.L
ELECTRI ONI C COMPONENTS
REMOVABLE HARDMARE (SCREb!S,’ NUTS , ECT 1
ASSEMBLY PROCESS SPECIFICATION
TEST SPECIFICATION
ASSEMBLY tlARKING REOUIREIIENTS

MASTER DRAWING

tlATERIAL
FABRICATION PROCESS SPECIFICATION
PERMANENTLY ATTACHED HARDWARE
(TERMINALS , RIVETED-ON BRACKETS, ECTI
BOARO MARKING REOUIREt2ENTS
,- —. —-—-7

= ARTWORK MASTER PRODUCTION MASTER ~

L *
I L__[._J
I I
--—-—._
-1

. Includes circuit and silk screen masters.

FIGuR[ 2. Block diagram depicting typical printed-wiring drawing relationships.

32
 Downloaded from http://www.everyspec.com

MI L-STD-Z75C
31 December 1984

..-.
~ouon!$!
8
w 6

111111111111 {Ill 11111111111111111111 1111111111111111

● ● ●

●
●☛
● ●
●

2.000 * — ●

● ●

● ☛✎☛☛☛☛✎☛✎✎☛☛✎ ✎ ☛✎✎☛☛✎☛☛✎☛☛✎
● *0*0* *0***
mm*0**m*9mmm**se*

11111111111111111111 [Ill 11111111111111111111 11111111

g“~g:gg~:$~$fj
.-

NOII : Scales my be located as shown or at the cdgr of the artwork.

Ficuw 3. usc of grids in dcfininq pattern requirements.

77
 Downloaded from http://www.everyspec.com

141L-STD-Z75E
31 Oecember I’?ozs

(For use in determining current carrying capacity and sizes of etched

copper conductors for various temperature rises above ambient)

350

390

250

20.0

In 15.0
:
& 120
~ 100
z 80
: ::
z
5.0
: ,0
‘%
. 30
P, I I I I I I I ,! I
2.0
13 I I I
,
1.0 i I I I I I
I , ! [
, 1 1
I [ I I I I
.25 , I r
.125-
0
I i I I I I I I I

0
.001 I I I ! I I I I I I I I
I
.005
I ,, I !, I I ,, I
.010
.0t5
.020
I I \k –,
>J :
----–~ T T7TEFE
I
.S130 I I \>’

0 , 5 10 .?0 30 so 10 00 1.0 zoo 250 300 400 5cQ m ?00

CROSS SECTION IN SO. MILS

rlGUR1’ 4a. (lmluctor tltickncs~ and width for type 1, tyl~ ?, and external layers of
lY*e ?rlnted-w, rinq boards.

JO
 Downloaded from http://www.everyspec.com

MI L-STD-275[
31 December 198L

f!J3TfS:
1. The design chart has been prepared as an aid in estimating temperature riSeS
(above ambient) .s current for various cross sectional areas of etched copper
conductors. It is assumed that for normal design conditions prevail where
the conductor surface area is relatively small compared to the adjacmt free
panel area. The curves as presented include a nominal 10 percent derating
(on a current basis) to allow for normal variations in etching techniques,
‘copper thickness, conductor width estimates, and cross-sectional area.
2. Additional derating of 15 percent (current-wise) is suggested under the
following conditions:
(a) For panel thickness of 1/32 inch or less.
(b) For conductor thickness of 0.0042 inch (3 oz/ft2) or thicker.
3. For general use the rW~i SSible temperature rise is defined as the difference
between the maximum safe operating temperature of the laminate and the
maximum ambient temperature in the location where the panel will be used.
4. For single conductor applications, the chart may be used directly for
determining conductor widths, conductor thickness, cross-sectional area,
and current-carrying capacity for various temperature rises.
5. $or groups of similar parallel conductors. if closely soaced. the
temperature rise MY be found by using an equivalent cross-section and an
equivalent current. The equivalent cross-section is equal to the sum of the
CiUSS-5e~Liw, S .r Lim IMrdliel conductors, anti the equivalent current is
the sum of the currents in the conductors.
6. The effect of heating due to attachment of power dissipating parts is not
included.
7. I he final conductor thickness in the design chart do not include conductor
overplanting with metals other than copper.

FIGuR[ 4a. Conductor thickness

_.. and —
width for type 1, type 2, and external layers of
tYPe 3 printed-w~rln~ boards - Continued.

35
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MI L-STD-2751
3 I Cec,mbcr ..984

(FW ‘uSE IN DETERMINING CURRCNT CARRYIkG CAPACITY AND SIZES Or ETCHED

cOPPER CONDUCTORS FOR VARIOUS TEMPERt,TURE RISES td3CVE AMBIENT)
17.5

I 5.0

12,5

10.0

m 7.5
:
: 6.0 ...
z 5.0
u
z 4.0
L 3.5
z 3.0
u 2.5
u
2.0
;
1.5
1.0
.75

:x
.i25
.062
0
0
.OGi
.005
.010
.015
.020
,mo

,m
.Om

.100

.150

.200

.230
.300

.330
.400
0131020305070!00 15’3200,?50 Xr34003UJ 003700

CROSS SFCTION IN SO. MlLS

31!
 Downloaded from http://www.everyspec.com

MIL-STD-275E
II December 1‘?8$

NOTES:
1. The design chart has been prepared as an aid in estimating temperature riSeS
(above ambient) .s current for various cross-sectional areas of etched copper
conductors. It is assunu?d that for normal design conditions prevail where
the conductor surface area is relatively smal 1 compared to the adjacent free
panel area. The curves as presented include a ncminal 10 percent derating
(on a current basis) to allow for normal variations in etching techniques,
copper thickness, conductor width estimates, and cross-sectional area.
2. Additional derating of 15 percent (current-wise) is suggested under the
following conditions:
(a) For panel thickness of 1/32 inch or less.
(b) For conductor thickness of 0.0042 inch (3 ozlftz) or thicker.
3. For general use the permissible temperature rise is defined as the difference
between the maximum safe operating temperature of the laminate and the
maximum ambient temperature in the location where the panel will be used.
4, For single conductor applications, the chart may be used directly fOr
determining conductor widths, conductor thickness, cross-sectional area,
and current-carrying capacity for various temperature ri5eS.
5. For groups of similar parallel conductors, if closely spaced, the
temperature rise may be found by using an equivalent cross-section and an
equivalent current. The equivalent cross-section is equal to the sum of the
cross-sections of the parallel conductors, and the equivalent current is
the sum of the currents in the conductors.
b. lhe ettect ot iwatlng due to attacmnent of p.mer dissipating parts is not
included.
7. The final conductor thickness in the design chart do not include conductor
overplanting with metals other than copper.
8. The current may be up-rated 100 percent for external circuitry.

FIGURL 4b. @!d~c~o_r,~i $@e>s.?~d _wjd.t]_fOr internal lay$rS Of type 3 @@S - Continued.

37
 Downloaded from http://www.everyspec.com

141L-STL)-Z7’X
31 December lICL

“ J- 1

-L B

FIGuR[ 5. Discrete leadless conponent land pattern.

.
l-+-l
FIGURL 6. Chip carrier land pattern.

vl
 Downloaded from http://www.everyspec.com

111L-sTLl-275[
31 !kcembcr I’M

Id &l--I-

111[
0.010
I
‘“”’o-i t- “
0.030

T
0.200 0.030 00”
z

h’
0.010

0.070 T
n REF 0.030
0.070
REF
L! ‘
64

, +0.100+

FIGuRE 7. Nodif ied fan-out patternS.

r IGUR1 1!. file.?] nwunt in!l reqUirCmefltS.

—.——

3~
 Downloaded from http://www.everyspec.com

III L-STD-275[
31 December 198L

(MIN)
FLAT PACK LEAD
MINIMUM CONTACT AREA 1
(w BY w)

(N)
FLAT PACK
LAND
% w 7

FIGURE 9. Typical flat pack land.

.015 INCH MIN [0.380 mm) -1

.025 INCH MA X(O.635 mm)

FIGuR[ 10. Coined or flattened lc~d.

—,

4n
—
Downloaded from http://www.everyspec.com

NIL-STD-275E
II Oecembcr 1986

-d ~ MIN
\ ANNULAR
RING LAND ~ 90”

90°
I

.005 MIN –..

I ?
> — PLAT~~ ,005 MIN

TtiRu HOLE
Q “ j& -1 MIN
ANNULAR
_~ ~RING
LANO

FIGuRE 11. Minimum annular rin~

~External)
Type 2 or 3 boards.

INCH?S mm
.025 .13
.015 .38

--.002 MIN

a
-i

.-i

I{OTIS:
SHAVED
n 90”
005 MIN

1. Dimensions are in inches.

2. Hctric equivalents arc yiven for general information only.
3. Ihdii arc permissible at the junction of I?mds and conductors.

rIGURL’ 13. [xamples of minimum annular rinq dimnsions.

([xternal
_— )

41
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II IL-STD-275[
31 Ikccmber 1984

TERMINAL AREA BEFORE TERMINAL AREA AFTER

ORILLING DRILLING

FIGURE 14. Ground plane lands (typical ).

Plated-through hole Unsupported hole

.028 Inch (0.71 mn) MAX .020 Inch (0.51 mn) MAX
A+B=
I .006 Inch (0.15 M] H!I1 .006 Inch (0.15 mm) Mill

rlGuR[ 15. !lule diameter for

— flat lead.
 Downloaded from http://www.everyspec.com

141L-STD-275[
11 rlo,..-h.. * 094

COPPER
LAYER —

PEAKI
DIELECTRIC _
MATER IAL

COPPER
LAYER ~

7HICKNESS MEAS-
uREMENTS OF BASE
MATERIAL )

FIGuRE 16. Dielectric layer thickness mess.renwnt.

 Downloaded from http://www.everyspec.com

MI L-STD-275[
31 ucccmlxsr 198A

----
~STRIP IDENTIFICATION
—

m
.250 (6,35)
.500 112.TDI ‘Yp
L

?--

sEE
NOTE ~ I MDj
,E,Ty L,TR,, TWO BOARD PANEL
IOENTIFICATIW
COUPONS
A, BANDF WHEN
REQUIRED

THREE BOARO PANEL

FOUR BoARD PANEL

;0

❑ ID
@
NINE BMRO PANEL
SIX BOARO PANEL

NDTES:
1. Dimensions are in inches..
2. Metric equivalents are in parentheses.
3. Other coupons as required for use by fabricator to position on panel
Location on artwork is optional and location on panel is optional.

I_l GuRl 17. Locdt ion of Lest circuitry b,>scd on number of boards fabricdtcd per panel.
—— .— . ..— —

44
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HIL.STD-275E
11 Ucc.mbcr 1984

FLAT LEAD=

T -LEAD THICKNESS

LAND ‘-
/

FLAT LEAD

FIGuR[ 18. Flat lead termination.

45
 Downloaded from http://www.everyspec.com

NIL-5 TD-275E
31 Flecemher 1qR6

B“oTm
& STANDAF!D

IIOT[:
BEND

Ileasurerment shall be made from the end of the part.

B. WELDEO BEND

(The end of the part is defined to include any coating

m?niscus, solder seal, solder or weld bead, or any
other extens ion.) (For figure 19s].

Lead diam?ter in inch Minimum radius (R) in~[l

UP to .027 (0.69 non] 1 diarn?ter

From .02LI (0.71 urn) to .047 (1.19 m) 1.5 diameters
.048 [1.22 m) a,,d larger 2 diameters

FIGuRE 19. Lead bend.

ANY DIRECTION

TI
.55 INCH
(1.4 mm)
MAX

L
l_- -m ,,

‘.015 INCH
(0.38 mrn)MlN

rlGURL ?0. Perpmdicul, $r pdrt mount in.1.

 Downloaded from http://www.everyspec.com

~IL-s Tfl-?75E
31 D-xember 1984

Custodians: Oreparing actitvity:

krmy . ER Navy - [C
Navy - EC
Air Force - 17 (Project 5999-0146)

Review activities:
Army . AR, EA. Ml
Navy - OS, SH
Air Force - 11, 16, 85, 99
I)LA - ES
NSA/S512

USer activities:
Navy - AS, [G HC
Air Force - lb

Agent:
LILA - ES

47
 Downloaded from http://www.everyspec.com

NOTE’ W. km my not bc .-d ta -q.=! copies of dommr.rnu. nor to request wmhrn, dwiafioru. or .Iuific.tb. .!
specification mq.iternenu on cum.! cmtrmu. C-mmm.u submitted on thii farm d. not mxwit.tz or amply ..th.riution
lo -ix my portion of the” m !twved docurwnt(s) O* to intend contrutud rcq.ireu.cna.

,rol$ .lUU
,,” u“.,

DEPARTMENT OF THE NAVY

Naval Electronic Systems Comnand
Washington, DC 20363
111111 p

UWITCDSTAIES :

OFFICIAL BuSINE5 Rr -
,fOIA LTV *OR PR8VATC “S[ ,~ [ BUSINESS REPLY MAIL I =
I ,,. s,

POSIAU
Ccass

wILL
●ERM,, MO ,2,0,

BE PAID 9v1ME
W. S”, NGTO.

DEP4R1MENT
0 c

OF THE NAVV
I

.- d

COMMANDER
NAVAL ELECTRONIC SYSTEMS COIWANO ~-
OEFENSE STANOAROIZATION PROGRAM BRANCH
DEPARTMENT OF THE NAVY
UASHINGTON, DC 20363
ATTN : ELEX 8111 4
 .
Downloaded from http://www.everyspec.com

.
STANDARDIZATION OOCUMENl IMPROVEMENT PROPOSAL
(&c I.umcti -R- Side]
rwcwtml ruumfn 2. CUUENT TITLE

*.2A 27A - ,;’7<Z //1/?./!7%f %?/ AZ(:Z%ZZ x%??

, NAMEOF SUBMIt_l, NOOm GA N12-TlON 4.rv?E 0$ onG4N12ATm. iMti-l

-moon
•1

Q -cm
.Ooncc+ (soul. cm. #u*. ZIP cd)

❑ Uw”v.c’lunti”

“o O?ME
m(S”dh
,:
_
PIWL3LEU
AmEA5
.,.,.ymh *.*, M W.rduw:

,. .C..-”adad wore,.,:

. . m...o”!.. !.o..,. ,., “Oc.-””. d”,..,

REMARICS

N.”C 0’ S“n”,,, En L ,, r“,. MI, - O.!ld *. won. TEISP”ONE Mvh18Em IJ.C1.* .4”.

ZIP
Cd,
-OD,,OMI
cd, - 0,,).”.8

UAIL, ”G ADDRESS ,Snw,. C,lI. S,. t..

9 DATE OF SU9U15SION ,VVMMDDI

mm ----- . .-a
Pm Ev10u5 EDITION Is WSOLETC.
W L“::, 14zb