Microelectronic Engineering 132 (2015) 14–20

Contents lists available at ScienceDirect

Microelectronic Engineering
journal homepage: www.elsevier.com/locate/mee

Review Article

Fabrication of gated nano electron source for vacuum nanoelectronics

Masayoshi Nagao ⇑, Tomoya Yoshida
National Institute of Advanced Industrial Science and Technology (AIST), 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan

a r t i c l e i n f o a b s t r a c t

Article history: Many kinds of attractive new applications, such as image sensors, stationary X-ray sources, and the col-
Received 9 May 2014 umn-less SEM, are investigated as post field emission displays that use a gated nano electron source. The
Received in revised form 7 August 2014 fabrication of the gated nano electron source is overviewed from the conventional method to the latest
Accepted 14 September 2014
one, especially in regarding to the gate formation process. Multi-stacked gate electrode formation using
Available online 22 September 2014
an etch-back method was developed recently, which is a very attractive method for generating a focused
electron beam. The traditional Spindt-type emitter fabrication method is also being improved to the one
Keywords:
that is easier and applicable to large area substrates. Using a double-layered photoresist as a lift-off layer
Field emitter array
Double gate
and using HiPIMS sputtering instead of an e-beam evaporator was proposed. Thin film-type FEA fabrica-
Multi gate tion is also improved to make vertically standing thin film by ion irradiation, which is applicable for mak-
Etch-back ing an emitter array on a large sized substrate.
Spindt-type emitter Ó 2014 Elsevier B.V. All rights reserved.

1. Introduction especially of the vertical-type FEA, which includes Si and Spindt-

FEA, will be overviewed with a historical explanation of FEA
The gated nano electron source (field emitter arrays: FEA) has fabrication.
been intensively investigated since the 1990s for application to
the field emission display (FED). The Futaba Corporation started 2. Silicon emitter fabrication
mass production of the 1st generation monochromatic FED [1]
from the 90s and the 2nd generation full color FED [2] from 2006 Crystalline silicon was widely used for making vacuum micro-
by using a Spindt-type FEA. The mass production of larger display and nano-electronics device because of its well-developed fabrica-
panels was also projected; one was a display that uses a nano- tion process used in semiconductor device fabrication. In an early
Spindt emitter made by Field Emission Technologies Inc. [3], and stage, a single crystalline silicon wafer is wet etched to form field
the other was one that uses a surface-conduction electron-emitter emitter arrays [13]. Isotropic etching and orientation-dependent
(SCE) made by SED Inc. [4]. However, companies gave up the com- etching is extensively developed. It was, however, very difficult
mercialization after 2008. Although FED development declined, the to achieve good uniformity in a large area substrate when using
gated nano electron source has been improved continuously and is wet etching. After the dry etching process was applied, silicon
still an attractive device for new applications, such as an FEA X-ray emitter fabrication development accelerated.
image sensor using CdTe that can detect not only the X-ray inten-
sity but also the incident X-ray photon energy [5], a medical image 2.1. Formation of single crystalline silicon emitter using dry etching
sensor using a highly sensitive imaging device that has an FEA and
a high avalanche rushing amorphous photoconductor (HARP) [6], a Betsui [14] developed a method for fabricating gated single
stationary X-ray source array for a medical tomographic system crystalline silicon (c-Si) field emitter arrays. His method became
[7,8], a column-less scanning electron microscope (SEM) using a a kind of standard for fabricating Si FEAs, and a lot of variations
quintuple-gated FEA [9], and a field-emission based THz wave gen- were investigated. Here, the fabrication is explained along with
erator [10]. These applications are possible thanks to a break- Fig. 1. First, a silicon dioxide disc-shaped mask is formed by ther-
through in the fabrication of the gated FEA. The technologies mal oxidation, photolithography, and reactive ion etching (RIE)
developed before 2001 are well described in Refs. [11,12]. In this (a). Then, single crystalline silicon is etched through the SiO2 disc
paper, recent innovative nano-fabrication of the gated FEA, by RIE to form a tip structure (b). The RIE ends before the SiO2 mask
is removed and then sharpened by using thermal oxidation (c). A
⇑ Corresponding author. moderate thermal oxidation temperature about 950° C can shar-
E-mail address: my.nagao@aist.go.jp (M. Nagao). pen the tip. After the sharpening, the insulator SiO2 and gate metal

http://dx.doi.org/10.1016/j.mee.2014.09.004
0167-9317/Ó 2014 Elsevier B.V. All rights reserved.
 M. Nagao, T. Yoshida / Microelectronic Engineering 132 (2015) 14–20 15

are deposited by using an evaporator (d). A self-aligned gate aper- in uniformity, reliability and stability. Using amorphous Si (a-Si)
ture is formed in this step. The overlying structure on the emitter is an alternate for overcoming the substrate limitation problem.
tip is removed by using a buffered hydrofluoric (BHF) acid solution In this case thermal oxidation sharpening cannot be applied
(e). Fig. 1(f) shows a silicon emitter with Nb gate electrode fabri- because of the significant damage done to the a-Si surface mor-
cated by the authors referring to Betsui’s method. The merits of phology. An alternative sharpening process was developed by
this process are that a very sharp tip can be obtained uniformly using ion etching [21]. Two-step ion etching using Ar and CHF3
by using thermal oxidation, which was confirmed by TEM observa- reactive ion etching (RIE) is applied at room temperature. A start-
tion [15], and that the gate aperture is self-aligned. ing emitter tip, which is fabricated out of amorphous silicon (a-Si)
with RIE of an SF6 and O2 gas mixture, has the shape of a circular
2.2. Polycrystalline silicon, amorphous silicon, sharpening truncated cone whose top is flat. Ar ion etching sharpens the apex
of the emitter moderately. However, the tip is still blunt. CHF3 RIE
The polycrystalline silicon (poly-Si) emitter is investigated in after Ar ion etching shapes the emitter tip into a cone with a much
order to lower the fabrication cost and to overcome the limitation sharper apex. An interesting point is that sharpening does not
of the substrate size especially in the field of the field emission dis- occur by CHF3 RIE only. The combination of Ar sputtering and
play [16–19]. The basic fabrication procedure is similar to that of c- CHF3 RIE makes the very sharp tip, even at room temperature. This
Si FEAs from the viewpoint of using isotropic etching by RIE and low temperature process is applicable for display applications that
thermal oxidation sharpening. However, poly-Si FEAs have a rough use a glass substrate.
tip structure and asymmetric gate aperture due to the grain bound-
ary. The rough morphology of the tip and gate structure causes the 2.3. Etch-back method for gate formation
increase of the undesired gate current. The large gate current is apt
to cause tip and gate disruptions due to an arc discharge between In the fabrication with Betsui’s method, the lift-off process for
the tip and gate electrode [20]. Hence, poly-Si FEA has difficulties the metal disc [step (d) in Fig. 1] is a kind of bottleneck to improv-
ing the fabrication yield because the small metal disc becomes a
waste particle and causes a short problem between the tip and
gate. In addition to this, the initial SiO2 mask determines the diam-
eter of the gate aperture; therefore, we cannot miniaturize the gate
aperture with an additional process in order to improve the emis-
sion characteristics. The etch-back method is another solution for
making the gate aperture [22–24]. Fig. 2 is a typical procedure of
the etch-back method. The starting point is just after the emitter
tip formation shown in Fig. 1(c). After this formation, SiO2 is
removed by BHF, and then, the gate insulator SiO2 and gate metal
are deposited by PE-CVD and sputtering, respectively (a). Note that
the material that is not affected by BHF should be selected as a gate

Fig. 1. Procedure for fabricating gated silicon field emitter by thermal oxidation Fig. 2. Etch-back method for making gate aperture on silicon emitter cone and SEM
sharpening [14] and SEM image of the fabricated emitter. image.
16 M. Nagao, T. Yoshida / Microelectronic Engineering 132 (2015) 14–20

electrode because BHF is used in the following emitter tip opening current under the strong focused condition. This is caused by the
process. Then, a photoresist having an appropriate viscosity is spin lowered field enhancement on the emitting tip from the low
coated (b). The thickness of the photoresist on top of the mountain potential of the vicinal focusing electrode. In addition to this, the
structure becomes thin; therefore, the gate electrode on the emit- fabrication of these double-gated FEA is basically based on Betsui’s
ter tip can be selectively etched by the following RIE (c). After that, method. Hence, a similar difficulty in the fabrication yield exists.
the photoresist is removed, and the SiO2 on the emitter tip is also To overcome the difficulty in fabrication and the current degrada-
removed by BHF (d). In this step, the gate electrode works as a tion problem, a volcano-structured double gate FEA is proposed
mask during the BHF etching. In this process, a self-aligned gate that uses the etch-back method [34]. The merit of this method is
aperture can be opened without lithography. The gate hole diame- not only the good controllability of the gate structure (aperture
ter is determined by the thickness of the SiO2 layer not by the size and electrode height) but also it is applicable many times on
lithography resolution; therefore, a small gate aperture is easily the emitter structure. By extending this method, we can stack
obtained [25] by controlling the insulator thickness. For example, many electrodes with a gate aperture on the emitter tip, as shown
less than 500 nm is easily achieved, as shown in Fig. 2(e). In addi- in Fig. 3. The quintuple-gated FEA is fabricated by applying the
tion, this method has good controllability in changing the gate etch-back method five times and using a specialized emitter tip
electrode height, which also influences the emission performance opening process [35]. The tip opening process is key for this fabri-
[26]. cation. When the emitter tip is exposed, BHF etching is usually
used. The etching of the BHF goes isotropically; therefore, the lat-
eral etched length is the same as that of the vertical depth. If the
2.4. Double and multi-gate FEA tip-exposing etching is carried out at one time, the SiO2 layer under
the top electrode is completely removed while the emitter tip is
For practical applications, beam focusing of the emitted elec- opened, especially for arrays with a small tip-to-tip interval. To
trons is very important. An FEA with a focusing electrode is an overcome this, step-by-step tip opening is applied. First, a short
attractive device. Two types of FEAs integrated with focusing elec- BHF etching is carried out. The time of this short etching is deter-
trodes have been proposed so far [27]. One uses an in-plane focus- mined to be the same time as that needed to etch the thickness of
ing method [28], in which two gate electrodes are made coplanar.
The other one is a double-gated FEA, in which two electrodes are
vertically stacked [29]. The latter case is more effective for gener-
ating a focused electron beam. Many researchers reported the fab-
rication and characterization of the double-gated FEA [30–33].
However, it has an problem related to the decrease of emission

Fig. 3. SEM images of multi-gated FEA fabricated by using etch-back method and
specialized tip exposure process. Fig. 4. Fabrication of Spindt-type emitter and SEM example.
 M. Nagao, T. Yoshida / Microelectronic Engineering 132 (2015) 14–20 17

the top SiO2 layer. The first etching makes the undercut in the first micro-cavities [39]. The field emitter cone made with his proce-
top layer. After that, photolithography is carried out without a dure is called the ‘‘Spindt-type emitter’’. The fabrication process
photo mask. The photoresist gets into the undercut region, and is well established, and the Spindt-type emitter shows excellent
the top electrode works as a photo-mask. Thus, the photoresist emission characteristics such as a high current density [40], uni-
under the top electrode is not exposed and consequently is not form emission [41], and good reliability [1]; therefore, many kinds
removed after the developing. The remaining photoresist protects of prototypes have been developed by using Spindt-type emitters.
the top SiO2 layer from the side etching at the following BHF etch- Here, the Spindt-type emitter fabrication flow is described briefly
ing for the second SiO2 layer. Thus, this second layer can be along with Fig. 4. First, an emitter electrode, gate insulator (SiO2),
removed with a moderate undercut. By repeating the procedure and gate electrode are deposited on the insulating substrate. Then,
for several times, the SiO2 layer on top of the emitter tip is success- a gate hole pattern is etched by photolithography and RIE. The SiO2
fully removed without an excess of undercut. layer is also etched by RIE with the gate electrode as an etching
The etch-back method enables us to make a multi-gate FEA and mask. After the RIE of the SiO2, BHF etching is performed to make
is a significant breakthrough in the field of FEA fabrication. The an overhang structure, as shown in Fig. 4(a). Material that is not
multi-gated FEA is a good candidate for e-beam applications, such affected by BHF should be selected as the emitter and gate elec-
as the multi-electron-beam lithography system and tiny electron trode. Usually, Mo or Nb is used. After formation of the cavity
microscope. The beam focusing characteristics are intensively structure, a lift-off layer, which is often called a ‘‘sacrificial layer’’
investigated [36–38] for this purpose. or ‘‘parting layer’’, is deposited from the grazing angle with the
rotation of the substrate (b). The grazing-angle deposition is neces-
3. Spindt-type emitter fabrication sary in order to prevent deposition on the emitter electrode; there-
fore, an e-beam evaporator is commonly used for this process. This
The Spindt-type emitter is one of the most famous emitters in process controls the following hole closure rate and manages stres-
the field of vacuum nanoelectronics. The name ‘‘Spindt-type emit- ses in the emitter layer. Then, emitter material is deposited from a
ter’’ is often used for indicating the vertical-type emitter, but this is perpendicular direction to the substrate. During emitter deposi-
not correct. ‘‘Spindt-type emitter’’ is not the name of the emitter tion, the hole closes with the thickness of the deposition, and the
shape but of an emitter that is made by using Spindt’s method. cone is formed in the bottom of the hole (c). This cone formation
In this section, the original Spindt-emitter fabrication and its mod- process is the key technology of the Spindt-type emitter. Hence,
ification will be overviewed. an emitter made by deposition with a hole closure should be called
a ‘‘Spindt-type emitter’’. Mo is usually used for the emitter mate-
rial. The aspect ratio of the emitter cone depends on the substrate
3.1. Original Spindt-type emitter fabrication
temperature; the higher the temperature, the higher the aspect
ratio [40]. After the formation of the emitter cone, the lift-off layer
Spindt at the Stanford Research Institute developed a process
is dissolved by using wet etchant that attacks only the lift-off
for fabricating arrays of miniaturized metal field emitter cones in

Fig. 5. SEM images of Ni Spindt-type emitter using double-layered photoresist as a lift-off layer. (a) Micro-cavity made of double-layered photoresist, (b) cross sectional
image after Ni deposition on double-layered photoresist, (c) Ni emitter cone after lift-off, and (d) example of double gated emitter fabricated on Ni emitter tip.
18 M. Nagao, T. Yoshida / Microelectronic Engineering 132 (2015) 14–20

material. Fig. 4(e) shows a cross section of a Spindt-type emitter is called the ‘‘lift-off resist’’ (LOR), which is commercially available.
made of Mo. The second (upper) layer is a normal photoresist. After spin coating
of the double-layered photoresist, a gate hole pattern is exposed
and developed by using TMAH solvent. The underlying LOR layer
3.2. Modification in lift-off layer
is isotropically etched after the photoresist developing; therefore,
this simple process makes a cavity with an overhang structure, as
When fabricating a Spindt-type emitter, the grazing-angle
shown in Fig. 5(a). The emitter material can be deposited on this
deposition of aluminum is used for the parting layer. This process,
cavity, and the emitter cone is made in the same way as in the nor-
however, is not adequate for a large area substrate because the lar-
mal Spindt-emitter process if the emitter material is appropriately
ger the substrate, the longer the distance needed between the
selected. Since the cavity is made of photoresist, the substrate can-
source and substrate in order to achieve uniformity of directional-
not be heated during emitter material deposition. Mo emitter is
ity. The deposition equipment consequently tends to become
hard to make in this method because Mo is usually deposited in
bulky, which leads to an increase of fabrication cost. This is a
the heated condition to avoid the peeling off problem caused by
demerit for large area applications such as field emission displays.
film internal stress. Hence, material having low stress should be
To eliminate the deposition of the aluminum lift-off layer, using
selected. Nickel is a good candidate for this method, as shown in
a reflow process for aluminum, instead of grazing angle deposition,
Fig. 5(b). More than 1.5-lm-thick film can be deposited on the dou-
has been proposed [42]. An Al parting layer is deposited before the
ble-layered photoresist without the peeling off problem by using an
gate formation and rapid thermal annealing is carried out to flow
e-beam evaporator in the non-heated condition. One of the merits
aluminum to the sidewall of the gate hole and obtain a similar
of this process is the simplicity in forming the cavity, which is per-
shape for the parting layer of the original Spindt-type emitter for-
formed by using the single photolithography process. The other
mation. In this case, the interface property between the Al and
merit is the easy lift-off process because a photoresist can be easily
underling gate layer is important for the shape of the Al reflow.
removed by using an organic solvent. For example, the lift-off pro-
Appropriate gate material having a good wettability should be
cess finishes in several minutes when using a 4-inches wafer. This is
selected.
much faster than that using an aluminum parting layer with acid
Another method that does not use the grazing angle deposition
solvent. Fig. 5(c) shows an emitter cone made of Ni after lift off pro-
has been proposed that uses a double-layered photoresist lift-off
cess. The Ni emitter shows a higher aspect ratio than that of the Mo
layer [43]. In this method, a double layered photoresist is used to
emitter even with room temperature deposition. In this process, a
form the cavity structure instead of the insulator and gate electrode
gate electrode is not formed. However, this is not a demerit but a
in which the emitter cone is made. The first (bottom) layer is a non-
kind of merit. After formation of the emitter tip, a gate electrode
photosensitive resist that can be etched by the tetramethylammo-
and multi-focusing electrode can be easily formed on the tip by
nium hydroxide (TMAH) developer. The non-photosensitive resist
using the etch-back method, as mentioned before. Fig. 5(d) shows
an example of the double-gated Ni Spindt-type emitter made by
using etch-back method. A Spindt-type emitter with a volcano-
structured double gate is suitable for high-resolution image sensor
applications [44].

3.3. Modification of emitter deposition

As mentioned previously, directional deposition is a key process

for the Spindt-emitter formation, which is realized by using an e-
beam evaporator. However, using this evaporator in emitter mate-
rial deposition is also a bottleneck for scaling up of the substrate
because the equipment also becomes bulky in order to keep direc-
tionality when using a large substrate.
Using a collimated sputter has been proposed for this process
[45]. In the sputtering machine, the distance between the source
and substrate is much shorter than that with the e-beam evapora-
tor, and the collimator makes the direction of the sputtered parti-
cles perpendicular to the substrate. The emitter shape, however,
distributes in accordance with the distance from the collimator;
therefore, the collimator should be designed in accordance with
the emitter array pattern. In addition to this, a large amount of
the emitter material is deposited on the collimator, so the collima-
tor should be exchanged frequently.
An alternative method for using sputtering for emitter cone for-
mation is proposed that uses high power impulse magnetron sput-
tering (HiPIMS) [43]. In HiPIMS, a significant amount of the
sputtered metal species is ionized by applying high power density
to the sputtering target in pulses of a low duty cycle (<10%) and
frequency (<10 kHz) [46]. The ‘‘directionality’’ of ionized sputtered
species can be enhanced by using a negative substrate bias; there-
fore, it has the potential to form a cone structure in a cavity. The
realization of HiPIMS requires only power supplies different from
Fig. 6. (a) Relationship between bias voltage and emitter height when fabricating
those used in the conventional magnetron sputtering process. As
Mo cone in micro-cavity by HiPIMS sputtering. (b) Cross sectional SEM image of the a consequence, the physical parameter of the equipment, such as
emitter made by DC sputtering, and (c) by HiPIMS with an appropriate condition. the distance from the target to the substrate, is the same as that
 M. Nagao, T. Yoshida / Microelectronic Engineering 132 (2015) 14–20 19

of conventional sputtering. Fig. 6 shows the relationship between structure [47], a star shaped emitter [48], a comb shaped emitter
emitter height and off cycle voltage, including the height obtained [49], and so on [50–52]. One of the reasons for the variety of the
from normal DC sputtering. For the HiPIMS experiment, a small lateral FEAs would be the easiness in fabrication. The lateral FEAs,
cavity with a 1-lm-diameter gate hole was made on a wafer by however, emit electrons in a parallel direction to the substrate. The
normal lithography and using an etching method, as previously efficiency of obtaining electrons perpendicular to the substrate is
shown in Fig. 4(a). After the formation of the cavity, Mo was depos- not so good. A thin film bending phenomenon is discovered that
ited by HiPIMS at an Ar gas pressure of 3 Pa, a duty cycle of 5%, and occurs when irradiating ions on the cantilever structured thin film
an input power of 100 W. The off cycle voltage, which is equivalent [53], which enables the thin film to bend upward to be perpendic-
to the substrate bias voltage, was varied from 0 to 100 V. The thick- ular to the substrate, as shown in Fig. 7(a). This ion-induced-bend-
ness of the deposited film was about 1 lm on the flat substrate. ing (IIB) phenomenon occurs on any material of thin-films and any
The emitter height made in the cavity was evaluated by cross sec- species of incident ions [54]. When the penetration depth of ions is
tional SEM. As shown in Fig. 6, almost no emitter was formed in the within the upper half layer of the target thin-film, the irradiated
case of DC sputtering. However, HiPIMS with an appropriate condi- thin film is bent upward. When the penetration depth is deeper
tion formed a cone with a moderate height. The emitter height than the lower half of the thin film, the film is bent downward.
made in the cavity increased with the increase of the bias voltage Hence the bending direction can be controlled by the energy of
from 0 to 50 V. This is due to the increase of the directionality of ions. The curvature of the bended film depends on the dose of ions:
the incident particles. However, the emitter height decreased over a larger dose makes a smaller curvature radius. For example, a dose
50 V of bias voltage. This is probably due to the sputtering by the of 1016 ions/cm2 of 25-keV Ar+ ions makes the 20-nm-thick Mo
high-energy particles. In addition to the bias voltage, Ar gas pres- film stand upright [55]. The material dependence of the IIB phe-
sure would influence the emitter shape and should be optimized. nomenon was investigated to find out that the molybdenum film
As there is much room for optimization of the deposition parame- gives the largest bending angle among the several refractory met-
ter, the HiPIMS shows the possibility of forming an emitter cone by als [56].
sputtering. The IIB method was applied for fabricating an FEA [57]. The IIB
method can form a vertical-thin-film (VTF) structure with micron-
order height and with a high aspect ratio from a very thin film hav-
4. Lateral-type FEA and bending method ing a thickness of about 20 nm. Once the VTF structure is formed,
the gated VTF-FEA is easily fabricated by using the etch-back
A lateral-type FEA has a coplanar configuration for the emitter method previously mentioned. Fig. 7(c) shows a typical example
and the gate. Various kinds of lateral FEAs have been proposed so of the gated VTF-FEA. The advantage of this IIB method is that it
far, for example, a wedge emitter with three-dimensional gate needs only thin film deposition and that the process window of

Fig. 7. (a) Schematic of thin film bending method using ion irradiation, (b) vertical thin film array made with IIB method, (c) example of gated vertical-thin film emitter, (d)
standing ring array made with IIB method.
20 M. Nagao, T. Yoshida / Microelectronic Engineering 132 (2015) 14–20

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