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Midterm PDF

The document is an exam for an FPGA lab course that contains two questions. Question 1 asks the student to (1) design a VHDL model to implement a digital circuit shown in Figure 1, (2) use Quartus II to perform synthesis, and (3) use ModelSim to simulate input and output signals. Question 2 asks the student to draw a black-box diagram described by a given VHDL entity declaration. The exam is for a midterm, has 2 pages and 2 questions, and was given on November 2nd, 2020.

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219 views2 pages

Midterm PDF

The document is an exam for an FPGA lab course that contains two questions. Question 1 asks the student to (1) design a VHDL model to implement a digital circuit shown in Figure 1, (2) use Quartus II to perform synthesis, and (3) use ModelSim to simulate input and output signals. Question 2 asks the student to draw a black-box diagram described by a given VHDL entity declaration. The exam is for a midterm, has 2 pages and 2 questions, and was given on November 2nd, 2020.

Uploaded by

Obada Ar-ruzzi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Instructors:

Course Name: FPGA Lab


Palestine Technical University-Kadoorie Dr.Ing Shatha AbuShanab
Student Name:
Course Number: 12120522

Exam's Time: 50 minutes Student Number:

Page’s Number: 2
Question’s Number: 2 Midterm 1st Semester 2020-2021 Exam Date: 02.11.2020

Question 1: (23) Points

“You should take a screenshot for your code and result that shows

every step during working with Quartus and ModelSim programs”

1. Design a VHDL model to implement the digital circuit shown in Fig.1. (6) Points

Figure 2

Figure 1

2. Using Altera’s Quartus II to perform the synthesis (logic and physical) (6) Points

3. Using Altera’s ModelSim to performed the simulation activity of the input signals
(B1,B0,A1,and A0) and complete the output signals(F0,F1,F2) (6) Points
(3) Points
B1 B0 A1 A0 F0 F1 F2

0 0 0 0

1 0 1 1

1 1 1 0

0 1 1 0

1
4. The digital logic circuit is a ……………………. (2) Points

Question 2: (7) Points

Drew black-box diagram that is described by the following VHDL entity declaration?

entity CCT is port (

a_data : in std_logic_vector(0 to 7);

b_data : in std_logic_vector(0 to 7);

c_data : in std_logic_vector(0 to 7);

d_data : in std_logic_vector(0 to 7);

sel1,sel0 : in std_logic;

data_out : out std_logic_vector(7 downto 0));

end CCT;

Good Luck

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