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Finite State Machine (FSM)

A controller FSM at top level
ensuring a sequence of operations
B operates on outputs of A, C
operates on outputs of B

Shared RAM

A B C

STATE MACHINES Start Done Start Done Start Done

Start Done
Controller

Start Sequence of Steps Sequence of Steps

IDLE
start

1. Wait for Start 1. Wait for Start

A

2. Start A START_A 2. Start A

3. Wait for Done WAIT_A 3. Wait for Done
4. Start B 4. Start B
done_a
5. Wait for Done 5. Wait for Done
6. Start C 6. Start C
Shared RAM
Controller

7. Wait for Done START_B 7. Wait for Done

8. Send Done 8. Send Done
B

WAIT_B
9. Return to State 1 9. Return to State 1
done_b

Inputs Outputs Moore’s Machine

START_C
start start_a
WAIT_C Outputs are dependant
done_a start_b
C

done_c on state only

done_b start_c So we only need to
DONE mention inputs on state
Done done_c done transitions

Sequence of Steps

start|start_a IDLE 1. Wait for Start

2. Start A
3. Wait for Done Mealy’s Machine (Direct Combinational path)
WAIT_A
done_a|start_b 4. Start B
5. Wait for Done
6. Start C
7. Wait for Done
8. Send Done Inputs Outputs
WAIT_B
Logic Logic
done_b|start_c 9. Return to State 1

Mealy’s Machine
WAIT_C State Registered
done_c|done
outputs
Outputs are dependant
on state and input
So we need to mention
inputs and outputs on
state transitions

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always@(*)
begin

Combinational
start|
Feed back (AKA start_a=1
parameter IDLE = 2’d0; Latch)… Never
parameter WAIT_A = 2’d1; case(state) allow it… IDLE
IDLE:
parameter WAIT_B = 2’d2; if(start)
parameter WAIT_C = 2’d3; Inputs Outputs begin
State start_a = 1; done_a|
state_nxt = WAIT_A; WAIT_A start_b=1
reg [1:0] state; end
reg [1:0] state_nxt; State

WAIT_B
start
inputs Outputs done_b|
always@(posedge clk) start_c=1

begin 1
if(reset) IDLE start_a
WAIT_C done_c|
state <= #1 IDLE; WAIT_A
done=1
WAIT_B
else WAIT_C
state <= #1 state_nxt;
end

endcase
end

always@(*) always@(*)
begin begin
!start|
start_a = 0; start_a = 0;
start_a=0
start_b = 0; start_b = 0;
start_c = 0; start| start_c = 0; start|
done = 0; start_a=1 done = 0; start_a=1
state_nxt = state; start_b=0 state_nxt = state;
case(state) start_c=0 case(state)
IDLE IDLE
done=0
IDLE: IDLE:
if(start) if(start)
begin begin
start_a = 1; done_a| start_a = 1; done_a|
state_nxt = WAIT_A; WAIT_A start_b=1 state_nxt = WAIT_A; WAIT_A start_b=1
end end
State !done_a| WAIT_A:
start_b=0 if(done_a)
begin
WAIT_B start_b = 1; WAIT_B
start state_nxt = WAIT_B;
done_b| end done_b|
start_c=1 !done_b| WAIT_B: start_c=1
1 start_c=0 if(done_b)
begin
0 IDLE start_a done_c| start_c = 1; done_c|
0 WAIT_A WAIT_C
done=1 state_nxt = WAIT_C; WAIT_C
done=1
0 WAIT_B end
0 WAIT_C WAIT_C:
if(done_c)
!done_c| begin
done=0 done = 1;
state_nxt = IDLE;
end
endcase endcase
end end

ONE HOT ENCODING ONE HOT ENCODING

parameter IDLE = 4’b0001; state parameter IDLE = 4’b0001; state
parameter WAIT_A = 4’b0010; parameter WAIT_A = 4’b0010;
parameter WAIT_B = 4’b0100; parameter WAIT_B = 4’b0100;
parameter WAIT_C = 4’b1000; start_a parameter WAIT_C = 4’b1000; start_a
start start
reg [3:0] state; reg [3:0] state;
reg [3:0] state_nxt; reg [3:0] state_nxt;

state
One-Hot generally
FAST but consumes start
MORE FLIPFLOPS.
1
0 IDLE start_a
0 WAIT_A
0 WAIT_B
0 WAIT_C

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ONE HOT ENCODING ONE HOT ENCODING

parameter IDLE = 4’b0001; state parameter IDLE = 4’b0001; state
parameter WAIT_A = 4’b0010; parameter WAIT_A = 4’b0010;
parameter WAIT_B = 4’b0100; parameter WAIT_B = 4’b0100;
parameter WAIT_C = 4’b1000; start_a parameter WAIT_C = 4’b1000; start_a
reg [3:0] state; reg [3:0] state;
reg [3:0] state_nxt; reg [3:0] state_nxt;

state state
One-Hot generally One-Hot generally
FAST but consumes start FAST but consumes start
MORE FLIPFLOPS. MORE FLIPFLOPS.
1 1
What if it had been What if it had been
a Moore’s Machine? 0 IDLE start_a a Moore’s Machine? 0 IDLE start_a
0 WAIT_A 0 WAIT_A
But remember it had 0 WAIT_B But remember it had 0 WAIT_B
eight states… 0 WAIT_C eight states… 0 WAIT_C
So generally a ONE-HOT Moore
machine is FASTER at the cost of
more FLIPFLOPS

Typical Receiver Typical Receiver

Configuration Signal Path:
Path: Signal
Configuration Processing path
and Settings in Hardware
Of different
components

FPGA DSP FPGA DSP

ADC ADC
Scatter Scatter
Plot Plot

EYE Plot EYE Plot

Typical Receiver File Read/Write

• Works similar to C.
Component’s Data Sheets • Three steps
provide configuration – File Open
and Timing Specification • Integer Fid;
of component interfaces. • Fid = $fopen(“file_name”,”r”); // For Reading
• Fid = $fopen(“file_name”,”w”); // For Writing
DSP – Reading
ADC FPGA Input signal can be read
Model • $fscanf(Fid, “%h”,variable_name); // Read hex data
Model from a file (Generated
using simulation tools • $fread(); // Binary file
like Matlab etc.) – Writing
• $fprintf(Fid, “%d”,variable_name);
Outputs can be dumped • $fdisplay(“%d”,variable_name);
PCI Model • $fwrite();
into files for
verification (Simulation – File Close
tools can be used to • $fclose(Fid);
Test Bench plot output)