National University of Computer and Emerging Sciences

School of Engineering Islamabad Campus

Serial No:
EE303 Microprocessor
______________________________ _________ ______ Final Exam
_____________________
Interfacing
Student Name & Programming
Roll No Section Total
SignatureTime: 3 Hour
Friday, December 23, 2016 Total Marks: 120
Course Instructor
Dr. Waseem Ikram & Engr. Shehzad Ahmad ________________
Signature of Invigilator
DO NOT OPEN THE QUESTION BOOK OR START UNTIL INSTRUCTED .
Instructions:
1. Verify at the start of the exam that you have a total of seven (7) questions printed
on fourteen (14) pages including this title page.
2. Attempt all questions on the question-book and in the given order.
3. The exam is an Open book, closed notes. Please see that the area in your threshold
is free of any material classified as ‘useful in the paper’ or else there may a charge
of cheating.
4. Read the questions carefully for clarity of context and understanding of meaning
and make assumptions wherever required, for neither the invigilator will address
your queries, nor the teacher/examiner will come to the examination hall for any
assistance.
5. Fit in all your answers in the provided space. You may use extra space on the last
page if required. If you do so, clearly mark question/part number on that page to
avoid confusion.
6. Use only your own stationery and calculator. If you do not have your own
calculator, use manual calculations.
7. Use only permanent ink-pens. Only the questions attempted with permanent ink-
pens will be considered. Any part of paper done in lead pencil cannot be claimed
for checking/rechecking.

Q-1 Q-2 Q-3 Q-4 Q-5 Q-6 Q-7 Total

Total
20 12 16 18 22 17 15 120
Marks
Marks
Obtained

Vetted By: ____________________________ Vetter Signature: _____________________

1. Answer the following short questions.

a. If an external memory (RAM) and an IO device are interfaced with a processor which
essential signals will the control bus have? Can the interrupt input signals and the various
counter triggering input signals in an AVR also be classified as control signals? [3]

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Essential control signals are Read/Write and IO/Memory signals.

Yes, Interrupt and counter triggering signals can be classified as control external signals

b. How wide is the internal data bus of the AVR? What is the advantage of doubling the
width of the data bus of the AVR? Why is data bus of double width not implemented in
AVR? [3]

AVR internal data bus is 8-bits wide.

Double the data can flow per unit time which speeds up processing.
All the registers and other units will also have to be doubled otherwise doubling the data
bus will not have any significant advantage.

c. What is the essential function of an Instruction Decoder and Control Unit? Explain
considering an ADD R20, R21 instruction [3]

Instruction Decoder and Control unit essentially decodes each instruction which is
fetched and issues control signals.
It will decode the ADD instruction and issue control signals to perform an Add operation.
It will issue control signals enabling data to flow from registers R20 and R21 to the ALU
and the result stored back in R20.

d. The 32 General Purpose Registers in AVR are considered to be part of which memory in
the AVR architecture. What is the total size of the memory? [2]

The registers are considered to be part of Static RAM which is Data memory. The size of
the memory is 2 KB

e. What is the purpose of 64 IO Registers in the AVR architecture? There are two ways to
read and write from an IO register. For example OUT PORTA, R20 allows 8-bit contents
of R20 register to be written out to Port A. Write the alternate instruction to access Port
A. [4]
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There are different IO devices such as USART, Counters, ADC, SPI, etc. All these are
considered to be IO devices and the AVR communicates with these devices through their
IO Registers. [2]
Alternate instruction is STS $3B, R20 [2]

f. In AVR conditional branches use relative addressing. What is relative addressing and
what are its advantages? Explain with the help of an example. [5]

Relative addressing calculates target address relative to the current instruction. Consider
the code:
0004: AGAIN: ADD R20, R21
0005: DEC R16
0006: BRNE AGAIN
The label ‘AGAIN’ after the BRNE instruction defines the target address. It could have
been 0004, however 0004 is an absolute address. If the same code had been located at
addresses 0009, 0010, 0011 then the BRNE will branch to incorrect address instead of
branching to 0009. In relative addressing the label ‘Again’ will have a value 4 – 7 = - 3
When BRNE instruction is being executed the PC will be pointing to address 0007 if the
relative offset -3 is added to PC the target address is 4. Thus relative addressing allows
the code to be placed anywhere in the memory.

2. Generating time delays.

a. Write the assembly code for a nested loop (one outer and one inner loop). One NOP
instruction is executed in the inner loop. What is the maximum delay which can be
achieved assuming that the AVR has a 10 Mhz clock. [6]

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With 10 Mhz, 1 clock = 0.1 s

LDI R20, 255 ; 1 clk

Outer: LDI R21, 255 ; 1 clk
Inner: NOP ; 1 clk
DEC R21 ; 1 clk
BNEQ inner ; 1 or 2 clks
DEC R22 ; 1 clk
BNEQ outer ; 1 or 2 clks [3]

Inner loop timing = 255(1 + 1 + 2) – 1 = 1019 [1.5]

Outer loop timing = 1 + 255(1 + 1019 + 1 + 2) – 1 = 260865  0.1 s = 26086.5 s
[1.5]

b. If the hardware timer of AVR is to be programmed to give a delay of 26016 s.

Determine the initial count value which needs to be programmed. The count value must
be an integer number. Write assembly instructions which configure the appropriate
counter registers and the counter for counting the delay. Do not write the entire
program. The AVR uses 10 Mhz clock. [6]

1 clk = 0.1 s, Count = 26016/0.1 = 260160 which is too high

Using clk/8 prescaler, 1 clk = 0.8 s, Count = 26016/0.8 = 32520

65536 – 32520 = 33016 [2]

LDI R20, HIGH(-32520) ; with clk/64 count = 4065

OUT TCNT1H, R20

LDI R20, LOW(-32520)

OUT TCNT1L, R20 [2]

LDI R20, 0

OUT TCCR1A, R20

LDI R20, 2 ; 3 if clk/64

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OUT TCCR1B, R20 ; Normal mode, clk/8 [2]

3. A serial RS232 communication link between two AVRs is not working. The problem
could be with the serial link or the remote AVR. The serial link can be easily tested by
connecting the two ends of the serial link to the TRx and RDx pins of the AVR. The AVR
transmits 5 data bytes through the TRx pin, the same should be received through the RDx
pin. The serial link is declared ‘OK’ if the 5 received data bytes are the same as the 5 data
bytes transmitted.
a. Write the assembly code as an Initialize_UART function to configure the UART for
serial communication at 9600 bauds, 8-bit data, parity disabled and 2 stop bits. AVR uses
10 MHz clock [5]

For 9600 bauds: X = 10/(16  9600) – 1 = 64.1  64 [1]

Initialize_UART:
LDI R16, 0x40
OUT UBRRL, R16 ; 01000000 [1]
LDI R16, 0x00
OUT UBRRH, R16 ; 0xxx0000
LDI R16, (1<<RXEN) | (1<<TXEN)
OUT UCSRB, R16 ; enable Rx and Tx 00011000 [1]
LDI R16, (1<<URSEL) | (1 << USBS) | (1<<UCSZ1) | (1<<UCSZ0)
OUT UCSRC, R16 ; 2 stop bits, 8 bit char 10001110 [1]
RET [1]

b. Write assembly code which defines five test bytes in a look-up table. Write assembly
code as a Test function to transmit and receive the first byte, the transmitted and received
bytes are compared if they match then the test is repeated for the remaining four test
bytes, otherwise error flag (T flag in Status Register) is set and the Test Function ends.

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Use the indirect addressing mode to access and transmit 5 consecutive test data bytes
from the look-up table. [11]

.ORG $300
Test_data:
.DB 0x32, 0x41, 0xAC, 0x F3, 0x8B

Test:
LDI ZH, HIGH(Test_data << 1)
LDI ZL, LOW(Test_data << 1)
LDI R17, 5
Next: LPM R20, Z+
NotTxd: SBIS UCSRA, TXC
RJMP NotTxd
OUT UDR, R20
NotRxd: SBIS UCSRA, RXC
RJMP NotRxd
IN R21, UDR
CP R20, R21
BNEQ tstend
DEC R17
BNEQ next
RJMP ext
Tstend: BSET 6
Ext: RET

[define lut: 2] [read byte: 2] [function: 1]

[initialize lut: 1] [write byte: 2]
[test loop: 1] [check bytes: 2]

4. An AVR is used to control a solar tracker designed to keep the solar panel pointed
towards the sun. Two stepper motors are used to move the solar panel in the horizontal
and vertical directions respectively. The DC output of the Solar panel is digitized by

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using the AVR ADC. The digital output of the ADC is compared to check for maximum
voltage which indicates that the solar panel is directly pointing towards the sun.
a. The Solar panel which is tracking the sun has max. output of 10 W. The peak voltage and
current at max. power output is Vpmax = 17.4 V and Ipmax = 0.54 A. The dimension of a 10
W solar panel is 30 cm  30 cm. Design a circuit that interfaces the Solar Panel output
with the AVR ADC. The max. Input analog voltage to ADC channel is 5 V. [4]

A potential divider circuit is used with 14.3 k and 5.7 k resistors connected across the
solar panel output. The voltage across 5.7 k is connected to the ADC input. At max.
Power output Vpmax across the potential divider is 17.4 V, the current is 17.4/20k = 0.87
mA. Voltage output across 5.7 k resistor = 5.7  0.87 = 4.959 V.

b. Write assembly code which configures the ADC for measuring solar panel output.
Channel 0 is used. End of conversion is indicated by an interrupt instead of checking by
polling. AVR uses 10Mhz clk. Use the highest allowable sampling clk, ext. AREF pin is
used, ADC output is left adjusted. Do not write the entire program code. [4]

LDI R16, 0
OUT DDRA, R16 ; configure ADC pins as input [1]
LDI R16, 0x8E
OUT ADCSRA, R16 ; ADC enable, int. enable, clk/64 [2]
LDI R16, 0x20
OUT ADMUX, R16 ; AREF, left jfied., single ended ch 0 [1]

c. The horizontal movement and vertical movement stepper motors are controlled by the 4-
step pattern, C, 6, 3, 9 for forward or upward direction and 9, 3, 6, C for backward or
downward direction. Both the motors are connected through Port D. The upper four bits

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of Port D control the vertical direction motor and the lower four bits control the
horizontal direction motor. Write assembly code as a Horizontal_Movement function
which when called checks the T status flag, if Flag is clear it moves the horizontal motor
one step forward, otherwise backward. Assume Port D is initialized as output port.
Comment the code to help understand the code. [10]

Horizontal_Movement:
BRTS back
LSR R20 ; shift right
BRCC extf ; check for 1 shifted out
ORI R20, 0x80 ; if yes, rotate 1 into MSB
Extf: RCALL Delay ; delay
RJMP patout
Back: LSL R20 ; shift left
BRCC extb ; check for 1 shifted out
ORI R20, 0x01 ; if yes, rotate into LSB
RCALL Delay ; delay
Patout: ANDI R20, 0x0F ; retain pattern for hor. Motor
OR R21, R20 ; append pattern for ver. motor
OUT PORTD, R21 ; out pattern to hor. & ver. Stepper motor
RET

[Function/comments: 2] [shift pattern left: 2] [pattern out: 3]

[check T flag: 1] [shift pattern right: 2]

5. A stopwatch is implemented using the AVR Timer. A switch S is used as a toggle switch
to start and stop the counting. For example, when S is pressed the stop watch starts
counting when switch S is pressed again the stop watch stops counting. Pressing switch S

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again resumes the counting. Switch R resets the stopwatch. An 8 Mhz AVR is used. The
stopwatch counts hours, minutes and seconds. Determine the count value which precisely
measures 1 sec (discard the time taken to execute instructions).
 Write an interrupt driven assembly code to initialize the stopwatch. [10]
 Write ISRs which are executed when the S and R switches are pressed. S switch is
connected to INT0 and R to INT1. [4][2]
 Write ISR which updates the sec, min and hour count. Assume that R22, R23 and R24
keep record of sec, min and hour respectively. [6]
Comment the code to help understand the code.

8 Mhz/256 = 31250 counts/sec

LDI R20, 0x0

OUT TCNT1H, R20
OUT TCNT1L, R20 ; init TCNT1 = 0
LDI R21, HIGH(31250 - 1)
OUT OCR1AH, R21
LDI R21, LOW(31250 – 1)
OUT OCR1AL, R21 ; init OCR1A = 31250
LDI R21, (1 << OCIEA1)
OUT TIMSK, R21 ; Timer1 o/p compare A match
LDI R21, 0xC0
OUT GICR, R21 ; int 0 and 1 enable
LDI R21, 0X05 ; int 0 and 1
OUT MCUCR, R21 ; triggered on falling and rising edge
SEI ; set global int
OUT TCCR1A, R20
LDI R21, 0x04
OUT TCCR1B, R21 ; set CTC mode, clk/256, timer off
AGAIN: RJMP AGAIN
[initialize TCNT reg 2] [initialize interrupts 4]
[initialize OCRA reg 2] [initialize timer 2]

INT0: SBIC TCCR1B, WGM12 ; clock disabled? [4]

RJMP EXIT0 ; no,
SBI TCCR1B, WGM12 ; yes, enable clock

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RJMP EXIT1
EXIT0: CBI TCCR1B, WGM12 ; disable clock
EXIT1: RETI

INT1: LDI R21, 0X0 [2]

OUT TCNT1H, R21
OUT TCNT1L, R21 ; reset count
RETI

CTCA: INC R22 ; inc sec [6]

CPI R22, 60 ; check sec overflow
BRNE EXITA ; no overflow exit ISR
LDI R22, 0 ; sec overflow reset to 0
INC R23 ; inc min
CPI R23, 60 ; check min overflow
BRNE EXITA ; no overflow exit ISR
LDI R23, 0 ; min overflow reset to 0
INC R24 ; inc hour
CPI R24, 24 ; check hour overflow
BRNE EXITA ; no overflow exit ISR
LDI R24, 0 ; hour overflow reset to 0
EXITA: RETI

6. A two wheeled robot uses two DC motors.

a. Draw discrete BJT based driver circuit to drive a DC motor. Calculate the value and
wattage of RB resistance, assume that the DC motor draws 2 A current, transistor has h fe =
1200. [6]
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Ib = IC/hfe = 2000/1200 = 1.67 mA [1]

RB = (VBB – VBE)/Ib = (4.8 – 1.4)/1.67 = 2 k [1]
Wattage = Ib2Rb = (1.67)2(2) = 5.578 mW[1]

[3]

b. The two DC motors are controlled through Phase Correct PWM mode. Write assembly
code which generates PWM signals for both the DC motors. Both, Phase correct PWM
signals should be programmed in Mode1, non-inverted, default duty cycle should be close
to 50% and frequency should be close to 2 kHz. The AVR frequency is 8 MHz. Comment
the code to help understand the code. [11]

Frequency = Fosc/2N(Top)
N = 8000/22255 = 7.84  8
Duty Cycle = OCR1x/Top  100
OCR1x = (50  255)/100 = 127.5  128

SBI DDRD, 5 ; set OC1A output (left motor)

SBI DDRD, 4 ; set OC1B output (right motor)
LDI R16, 0
LDI R17, 128
OUT OCRlAH, R16
OUT OCR1AL, R17 ; duty cycle of OC1A signal
OUT OCRlBH, R16
OUT OCRlBL, R17 ; duty cycle of OC1B signal
LDI R18, 0xA1
OUT TCCRlA, R18 ; OC1A and OC1B non-inverted, Mode1
LDI R18, 0x02

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OUT TCCRlB, R18 ; clk/8

[Frequency/Duty Cyle 2] [config. Duty cycle 3] [TCCR1B config. 2]

[configure o/p 2] [TCCR1A config 2]

7. An AVR is connected to MAX7221 using the SPI interface. Eight (8) 7-segment common
cathode displays are connected with the MAX7221.
Write assembly code which enables the AVR to configure the MAX7221 for display of
stop watch time in the given format ‘HH-MM-SS’ on the eight (8), 7-segment displays.

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The code should display the default time 00-00-00 on the displays. Write comments to
indicate what the code is doing. [15]

LDI R17, (1 << MOSI) | (1 << SCK) | (1 << SS)

OUT DDRB, R17 ; set MOSI, SCK and SS signals on AVR as o/p
LDI R17, (1 << SPE) | (1 << MSTR) | (1 << SPR0)
OUT SPCR, Rl7 ; enable SPI, set as Master, clk/16 [3]
LDI R17, 0x09
LDI R18, 0b11011011 ; enable decoding for digits 0, 1, 3, 4, 6 and 7
RCALL RUNCMD ; send command and data to MAX7221
LDI R17, 0x0B
LDI R18, 8 ; scan all 8 displays
RCALL RUNCMD ; send command and data to MAX7221
LDI R17, 0x0C
LDI R18, 1 ; turn on displays
RCALL RUNCMD ; send command and data to MAX7221
LDI R17, 0x01
RCALL RUNDO ; display ‘0’ on display 0 and 1
LDI R17, 0x03
LDI R18, 1 ; display ‘-’ on display 2
RCALL RUNCMD
LDI R17, 0x04
RCALL RUNDO ; display ‘0’ on display 3 and 4
LDI R17, 0x06
LDI R18, 1 ; display ‘-’ on display 5 [5]
RCALL RUNCMD
LDI R17, 0x07
RCALL RUNDO ; display ‘0’ on display 6 and 7 [3]

RUNDO: LDI R16, 2

DO: LDI R18, 0 ; display ‘0’
RCALL RUNCMD
INC R17

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DEC R16
BNEQ DO
RET [2]

RunCMD:
CBI PORTB, SS ; select MAX7221
OUT SPDR, R17 ; send command
Wait1: SBIS SPSR, SPIF ; check if command sent
RJMP Wait1
OUT SPDR, R18 ; send data
Wait2: SBIS SPSR, SPIF ; check if data sent
RJMP Wait2
SBI PORTB, SS ; deselect MAX7221
RET [2]

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