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Utilization

The document provides a utilization report for the Vivado design tool version 2018.2, detailing the resource usage of a synthesized design named 'seq_detector_overlapping_1101011'. It includes statistics on slice logic, memory, DSP, I/O, clocking, and specific features, indicating low utilization across most categories with specific counts for used resources. The report serves as a summary of the design's performance and resource allocation.

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Tej Charan
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45 views4 pages

Utilization

The document provides a utilization report for the Vivado design tool version 2018.2, detailing the resource usage of a synthesized design named 'seq_detector_overlapping_1101011'. It includes statistics on slice logic, memory, DSP, I/O, clocking, and specific features, indicating low utilization across most categories with specific counts for used resources. The report serves as a summary of the design's performance and resource allocation.

Uploaded by

Tej Charan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

-----------------------------------------------------------------------------------
------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Sat Feb 20 17:54:26 2021
| Host : LAPTOP-C7UH12JO running 64-bit major release (build 9200)
| Command : report_utilization -file
seq_detector_overlapping_1101011_utilization_synth.rpt -pb
seq_detector_overlapping_1101011_utilization_synth.pb
| Design : seq_detector_overlapping_1101011
| Device : 7z010iclg225-1L
| Design State : Synthesized
-----------------------------------------------------------------------------------
------------------------------------------------------------------------

Utilization Design Information

Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists

1. Slice Logic
--------------

+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs* | 3 | 0 | 17600 | 0.02 |
| LUT as Logic | 3 | 0 | 17600 | 0.02 |
| LUT as Memory | 0 | 0 | 6000 | 0.00 |
| Slice Registers | 4 | 0 | 35200 | 0.01 |
| Register as Flip Flop | 0 | 0 | 35200 | 0.00 |
| Register as Latch | 4 | 0 | 35200 | 0.01 |
| F7 Muxes | 0 | 0 | 8800 | 0.00 |
| F8 Muxes | 0 | 0 | 4400 | 0.00 |
+-------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full
implementation, is typically lower. Run opt_design after synthesis, if not already
completed, for a more realistic count.

1.1 Summary of Registers by Type


--------------------------------

+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 4 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 0 | Yes | Reset | - |
+-------+--------------+-------------+--------------+

2. Memory
---------

+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 60 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 60 | 0.00 |
| RAMB18 | 0 | 0 | 120 | 0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can
accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a
Block RAM Tile, that tile can still accommodate a RAMB18E1

3. DSP
------

+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 80 | 0.00 |
+-----------+------+-------+-----------+-------+

4. IO and GT Specific
---------------------

+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 6 | 0 | 54 | 11.11 |
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
| PHY_CONTROL | 0 | 0 | 2 | 0.00 |
| PHASER_REF | 0 | 0 | 2 | 0.00 |
| OUT_FIFO | 0 | 0 | 8 | 0.00 |
| IN_FIFO | 0 | 0 | 8 | 0.00 |
| IDELAYCTRL | 0 | 0 | 2 | 0.00 |
| IBUFDS | 0 | 0 | 54 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 8 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 8 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 100 | 0.00 |
| ILOGIC | 0 | 0 | 54 | 0.00 |
| OLOGIC | 0 | 0 | 54 | 0.00 |
+-----------------------------+------+-------+-----------+-------+

5. Clocking
-----------

+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
| BUFIO | 0 | 0 | 8 | 0.00 |
| MMCME2_ADV | 0 | 0 | 2 | 0.00 |
| PLLE2_ADV | 0 | 0 | 2 | 0.00 |
| BUFMRCE | 0 | 0 | 4 | 0.00 |
| BUFHCE | 0 | 0 | 48 | 0.00 |
| BUFR | 0 | 0 | 8 | 0.00 |
+------------+------+-------+-----------+-------+

6. Specific Feature
-------------------

+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+

7. Primitives
-------------

+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| OBUF | 5 | IO |
| LDCE | 4 | Flop & Latch |
| LUT4 | 3 | LUT |
| LUT3 | 2 | LUT |
| IBUF | 1 | IO |
+----------+------+---------------------+

8. Black Boxes
--------------

+----------+------+
| Ref Name | Used |
+----------+------+

9. Instantiated Netlists
------------------------

+----------+------+
| Ref Name | Used |
+----------+------+

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