Integrated, Dual RF Transceiver

with Observation Path

Preliminary Technical Data AD9371
FEATURES FUNCTIONAL BLOCK DIAGRAM
Dual differential transmitters (Tx) AD9371
RX1+ RX1
Dual differential receivers (Rx) RX1– LPF
DECIMATION,
RX2 pFIR,

JESD204-B
Observation receiver (ORx) with 2 inputs RX2+ ADC DC OFFSET
QEC,
Sniffer receiver (SnRx) with 3 inputs RX2– LPF
TUNING,
RSSI,
OVERLOAD
Tunable range: 300 MHz to 6000 MHz ADC
MICRO-
Tx synthesis bandwidth (BW) to 250 MHz CONTROLLER
RX_EXTLO+ LO RF
Rx BW: 8 MHz to 100 MHz RX_EXTLO– EXTERNAL
GENERATOR SYNTHESIZER

Supports frequency division duplex (FDD) and time division OPTION

TX1+

SPI
TX1 SPI
duplex (TDD) operation PORT
TX1– TX2 LPF
Fully integrated independent fractional-N radio frequency (RF) TX2+ DAC
pFIR,

JESD204-B
synthesizers for Tx, Rx, ORx, and clock generation TX2– LPF
DC OFFSET
QEC,
JESD204B digital interface DAC TUNING,
INTERPOLATION

APPLICATIONS TX_EXTLO+ LO RF

CTRL I/F
TX_EXTLO– GENERATOR SYNTHESIZER
3G/4G micro and macro base stations (BTS) EXTERNAL
OPTION
GPIO
ADXADC
3G/4G multicarrier picocells AUXDAC
LO
GENERATOR
FDD and TDD active antenna systems

DEV_CLK_IN+/
DEV_CLK_IN–
RF
Microwave nonline-of-sight (NLOS) backhaul systems SYNTHESIZER
CLOCK
GENERATOR
GENERAL DESCRIPTION ORX1+
OBSERVATION
Rx

ORX1–
The AD9371 is a highly integrated, wideband RF transceiver
ORX2+
offering dual channel transmitters and receivers, integrated ORX2–
synthesizers, and digital signal processing functions. The IC
delivers a versatile combination of high performance and low SNRXA+
SNIFFER
Rx LPF DECIMATION,
pFIR,

JESD204-B
power consumption required by 3G/4G micro and macro base SNRXA–
SNRXB+
ADC AGC,
DC OFFSET,
station equipment in both FDD and TDD applications. The SNRXB– LPF QEC,
SNRXC+ TUNING,
AD9371 operates from 300 MHz to 6000 MHz, covering most ADC RSSI,

14651-001
SNRXC– OVERLOAD
of the licensed and unlicensed cellular bands. The IC supports
receiver bandwidths up to 100 MHz. It also supports observation Figure 1.
receiver and transmit synthesis bandwidths up to 250 MHz to The high speed JESD204B interface supports lane rates up to
accommodate digital correction algorithms. 6144 Mbps. Four lanes are dedicated to the transmitters and four
The transceiver consists of wideband direct conversion signal lanes are dedicated to the receiver and observation receiver channels.
paths with state-of-the-art noise figure and linearity. Each complete The fully integrated phase-locked loops (PLLs) provide high
receiver and transmitter subsystem includes dc offset correction, performance, low power fractional-N frequency synthesis for
quadrature error correction, and programmable digital filters, the transmitter, the receiver, the observation receiver, and the
eliminating the need for these functions in the digital baseband. clock sections. Careful design and layout techniques provide the
Several auxiliary functions such as an auxiliary analog-to-digital isolation demanded in high performance base station applications.
converter (ADC), auxiliary digital-to-analog converters (DACs), All voltage controlled oscillator (VCO) and loop filter components
and general-purpose input/outputs (GPIOs) are integrated to are integrated to minimize the external component count.
provide additional monitoring and control capability.
A 1.3 V supply is required to power the core of the AD9371, and
An observation receiver channel with two inputs is included to a standard 4-wire serial port controls it. Other voltage supplies
monitor each transmitter output and implement interference provide proper digital interface levels and optimize transmitter
mitigation and calibration applications. This channel also connects and auxiliary converter performance. The AD9371 is packaged in a
to three sniffer receiver inputs that can monitor radio activity in 12 mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).
different bands.

Rev. PrA Document Feedback

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
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Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
AD9371 Preliminary Technical Data

TABLE OF CONTENTS
Features .............................................................................................. 1 Theory of Operation ...................................................................... 45
Applications ....................................................................................... 1 Transmitter (Tx) ......................................................................... 45
General Description ......................................................................... 1 Receiver (Rx) ............................................................................... 45
Functional Block Diagram .............................................................. 1 Observation Receiver (ORx)..................................................... 45
Specifications..................................................................................... 3 Sniffer Receiver (SnRx) ............................................................. 45
Current and Power Consumption Specifications..................... 9 Clock Input.................................................................................. 45
Timing Specifications ................................................................ 11 Synthesizers ................................................................................. 46
Absolute Maximum Ratings .......................................................... 13 Serial Peripheral Interface (SPI) Interface .............................. 46
Reflow Profile .............................................................................. 13 GPIO_x AND GPIO_3P3_x Pins ............................................ 46
Thermal Resistance .................................................................... 13 Auxiliary Converters.................................................................. 46
ESD Caution ................................................................................ 13 JESD204B Data Interface .......................................................... 46
Pin Configuration and Function Descriptions ........................... 14 Power Supply Sequence ............................................................. 47
Typical Performance Characteristics ........................................... 17 JTAG Boundary Scan ................................................................. 47
2.6 GHz Band .............................................................................. 17 Outline Dimensions ....................................................................... 48
3.5 GHz Band .............................................................................. 27
5.5 GHz Band .............................................................................. 37

Rev. PrA | Page 2 of 48

Preliminary Technical Data AD9371

SPECIFICATIONS
Electrical characteristics at ambient temperature range, VDDA_SER = 1.3 V, VDDA_DES = 1.3 V, JESD_VTT_DES = 1.3 V, VDDA_1P3 1 =
1.3 V, VDIG = 1.3 V, VDDA_1P8 = 1.8 V, VDD_IF = 2.5 V, and VDDA_3P3 = 3.3 V; all RF specifications based on measurements that
include printed circuit board (PCB) and matching circuit losses, unless otherwise noted.

Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
TRANSMITTERS (Tx)
Center Frequency 300 6000 MHz
Tx Large Signal Bandwidth (BW) 100 MHz
Tx Synthesis BW 2 250 MHz Wider bandwidth for use in
digital processing algorithms
BW Flatness ±0.5 dB 250 MHz BW, compensated
by programmable finite
infinite response (FIR) filter
±0.15 dB Any 20 MHz BW span,
compensated by
programmable FIR filter
Deviation from Linear Phase 10 Degrees 250 MHz BW
Power Control Range 0 42 dB Increased calibration time,
reduced QEC 3, LOL 4
performance beyond 20 dB
Power Control Resolution 0.05 dB
ACLR 5 (Four Universal Mobile −11.2 dBFS rms, 0 dB RF
Telecommunications System attenuation
[UMTS] Carriers)
700 MHz Local Oscillator (LO) −64 dB
2600 MHz LO −64 dB
3500 MHz LO −63 dB
5500 MHz LO −61 dB
In Band Noise −155 dBFS 6/Hz
Tx to Tx Isolation
700 MHz LO 70 dB
2600 MHz LO 65 dB
3500 MHz LO 65 dB
5500 MHz LO 65 dB
Image Rejection Up to 20 dB RF attenuation,
within large signal BW,
QEC3 active
700 MHz LO 65 dB
2600 MHz LO 65 dB
3500 MHz LO 65 dB
5500 MHz LO 50 dB
Maximum Output Power 0 dBFS, 1 MHz signal input,
50 Ω load, 0 dB RF attenuation
700 MHz LO 7 dBm
2600 MHz LO 7 dBm
3500 MHz LO 6 dBm
5500 MHz LO 4 dBm
OIP3 −5 dBFS rms, 0 dB RF
Output Third-Order Intercept Point attenuation
700 MHz LO 27 dBm
2600 MHz LO 27 dBm
3500 MHz LO 25 dBm
5500 MHz LO 25 dBm

Rev. PrA | Page 3 of 48

AD9371 Preliminary Technical Data
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Carrier Leakage After calibration, LOL
correction active, CW 7 input
signal, 3 dB RF and 3 dB digital
attenuation, 40 kHz
measurement BW
700 MHz LO −81 dBFS6
2600 MHz LO −81 dBFS6
3500 MHz LO −81 dBFS6
5500 MHz LO −75 dBFS6
Error Vector Magnitude (3GPP EVM LTE 20 MHz downlink,
Test Signals) 5 dB RF attenuation
700 MHz LO −48 dB
2600 MHz LO −39 dB
3500 MHz LO −38.5 dB
5500 MHz LO −37.5 dB
Output Impedance 50 Ω Differential
RECEIVERS (Rx)
Center Frequency 300 6000 MHz
Gain Range 0 30 dB
Analog Gain Step 0.5 dB
BW Ripple ±0.5 dB 100 MHz BW, compensated
by programmable FIR filter
±0.2 dB Any 20 MHz span,
compensated by
programmable FIR filter
Rx Bandwidth 8 100 MHz Analog low-pass filter (LPF)
BW is 20 MHz minimum,
programmable FIR BW
configurable over the entire
range
Rx Alias Band Rejection 75 dB Due to digital filters
Maximum Recommended Input −14 dBm Input is a CW7 signal at a 0 dB
Power 8 attenuation setting; this level
increases dB for dB with
attenuation
Noise Figure NF Maximum Rx gain, at
Rx port, matching losses
de-embedded
700 MHz LO 12 dB
2600 MHz LO 13.5 dB
3500 MHz LO 14 dB
5500 MHz LO 18 dB
Input Third-Order Intercept Point IIP3 Maximum Rx gain, third-
order intermodulation (IM3)
1 MHz offset from LO
700 MHz LO 22 dBm
2600 MHz LO 22 dBm
3500 MHz LO 20 dBm
5500 MHz LO 20 dBm
Input Second-Order Intercept IIP2 Maximum Rx gain, second-
Point order intermodulation (IM2)
1 MHz offset from LO
700 MHz LO 65 dBm
2600 MHz LO 65 dBm
3500 MHz LO 65 dBm
5500 MHz LO 57 dBm

Rev. PrA | Page 4 of 48

Preliminary Technical Data AD9371
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Image Rejection QEC3 active, within Rx BW
700 MHz LO 75 dB
2600 MHz LO 75 dB
3500 MHz LO 75 dB
5500 MHz LO 75 dB
Input Impedance 200 Ω Differential
Tx1 to Rx1 Signal Isolation and
Tx2 to Rx2 Signal Isolation
700 MHz LO 68 dB
2600 MHz LO 68 dB
3500 MHz LO 62 dB
5500 MHz LO 60 dB
Tx1 to Rx2 Signal Isolation and
Tx2 to Rx1 Signal Isolation
700 MHz LO 70 dB
2600 MHz LO 70 dB
3500 MHz LO 62 dB
5500 MHz LO 60 dB
Rx1 to Rx2 Signal Isolation
700 MHz LO 60 dB
2600 MHz LO 60 dB
3500 MHz LO 60 dB
5500 MHz LO 60 dB
Rx Band Spurs Referenced to −95 dBm No more than one spur at
RF Input at Maximum Gain this level per 10 MHz of Rx
BW; excludes harmonics of
the reference clock
Rx LO Leakage at Rx Input at Leakage decreases dB for dB
Maximum Gain with attenuation for first 12 dB
700 MHz LO −65 dBm
2600 MHz LO −65 dBm
3500 MHz LO −62 dBm
5500 MHz LO −62 dBm
OBSERVATION RECEIVER (ORx)
Center Frequency 300 6000 MHz
Gain Range 0 18 dB
Analog Gain Step 1 dB
BW Ripple ±0.5 dB 250 MHz RF BW, compensated
by programmable FIR filter
Deviation from Linear Phase 10 Degrees 250 MHz RF BW
ORx Bandwidth 250 MHz
ORx Alias Band Rejection 60 dB Due to digital filters
Maximum Recommended Input −13 dBm Input is a CW7 signal at 0 dB
Power8 attenuation setting; this level
increases dB for dB with
attenuation
Signal-to-Noise Ratio 9 SNR Maximum gain at ORx port
700 MHz LO 60 dB
2600 MHz LO 60 dB
3500 MHz LO 60 dB
5500 MHz LO 59 dB 200 MHz BW, 245.76 MSPS

Rev. PrA | Page 5 of 48

AD9371 Preliminary Technical Data
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Input Third-Order Intercept Point IIP3 Maximum ORx gain,
IM3 1 MHz offset from LO
700 MHz LO 22 dBm
2600 MHz LO 22 dBm
3500 MHz LO 18 dBm
5500 MHz LO 18 dBm
Input Second-Order Intercept IIP2 Maximum ORx gain, IM2
Point 1 MHz offset from LO
700 MHz LO 65 dBm
2600 MHz LO 65 dBm
3500 MHz LO 65 dBm
5500 MHz LO 60 dBm
Image Rejection After online tone calibration
700 MHz LO 65 dB
2600 MHz LO 65 dB
3500 MHz LO 65 dB
5500 MHz LO 65 dB
Input Impedance 200 Ω Differential
Tx1 to ORx1 Signal and Tx2 to
ORx2 Signal Isolation
700 MHz LO 70 dB
2600 MHz LO 70 dB
3500 MHz LO 70 dB
5500 MHz LO 70 dB
Tx1 to ORx2 Signal and Tx2 to
ORx1 Signal Isolation
700 MHz LO 70 dB
2600 MHz LO 70 dB
3500 MHz LO 70 dB
5500 MHz LO 70 dB
SNIFFER RECEIVER (SnRx)
Center Frequency 300 6000 MHz
Gain Range 0 52 dB
Analog Gain Step 1 dB
BW Ripple ±0.5 dB 20 MHz RF BW, compensated
by programmable FIR filter
Rx Bandwidth 20 MHz
Rx Alias Band Rejection 60 dB Due to digital filters
Maximum Recommended Input −26 dBm Input is a CW7 signal at 0 dB
Power8 attenuation setting; this level
increases dB for dB with
attenuation
Noise Figure NF Maximum gain at
SnRx port, matching losses
de-embedded
700 MHz LO 5 dB
2600 MHz LO 5 dB
3500 MHz LO 7 dB
Input Third-Order Intercept Point IIP3 Maximum gain, IM3 1 MHz
offset from LO
700 MHz LO 1 dBm
2600 MHz LO 1 dBm
3500 MHz LO 1 dBm

Rev. PrA | Page 6 of 48

Preliminary Technical Data AD9371
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Input Second-Order Intercept IIP2 Maximum gain, IM2 1 MHz
Point offset from LO
700 MHz LO 45 dBm
2600 MHz LO 45 dBm
3500 MHz LO 45 dBm
Image Rejection After online tone calibration
700 MHz LO 75 dB
2600 MHz LO 75 dB
3500 MHz LO 75 dB
Input Impedance 400 Ω Differential
Tx1 to SnRx Signal and Tx2 to Applies to each SnRx input
SNRx Signal Isolation
700 MHz LO 60 dB
2600 MHz LO 60 dB
3500 MHz LO 60 dB
LO SYNTHESIZER
LO Frequency Step 2.3 Hz 1.5 GHz to 3 GHz, 76.8 MHz
phase frequency detector
(PFD) frequency
LO Spur −80 dBc Excludes integer boundary
spurs 1 kHz to 100 MHz
Spot Phase Noise
700 MHz LO
10 kHz −104 dBc
100 kHz −107 dBc
1 MHz −133 dBc
2600 MHz LO
10 kHz −93 dBc
100 kHz −97 dBc
1 MHz −123 dBc
3500 MHz LO
10 kHz −91 dBc
100 kHz −97 dBc
1 MHz −123 dBc
5500 MHz LO
10 kHz −98 dBc
100 kHz −100 dBc
1 MHz −110 dBc
Integrated Phase Noise Integrated from 1 kHz to
100 MHz
700 MHz LO 0.20 °rms
2600 MHz LO 0.49 °rms
3500 MHz LO 0.55 °rms
5500 MHz LO 0.75 °rms
REFERENCE CLOCK (DEV_CLK_IN
SIGNAL)
Frequency Range 10 320 MHz
Signal Level 0.3 2.0 V p-p AC-coupled, common-mode
voltage (VCM) = 618 mV; for
best spurious performance,
use a <1 V p-p input clock

Rev. PrA | Page 7 of 48

AD9371 Preliminary Technical Data
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
AUXILIARY CONVERTERS
ADC
ADC Resolution 12 Bits
Input Voltage
Minimum 0.05 V
Maximum VDDA_3P3 − V
0.05
DAC
DAC Resolution 10 Bits Includes four offset levels
Output Voltage
Minimum 0.5 V Reference voltage (VREF) = 1 V
Maximum VDDA_3P3 − V VREF = 2.5 V
0.05
Drive Capability 10 mA
DIGITAL SPECIFICATIONS (CMOS)
Logic Inputs
Input Voltage
High Level VDD_IF × VDD_IF V
0.8
Low Level 0 VDD_IF × V
0.2
Input Current
High Level −10 +10 µA
Low Level −10 +10 µA
Logic Outputs
Output Voltage
High Level VDD_IF × V
0.8
Low Level VDD_IF × V
0.2
Drive Capability 3 mA
DIGITAL SPECIFICATIONS (LVDS),
SYSREF_IN, SYNCINBx SIGNALS
Logic Inputs
Input Voltage Range 825 1675 mV Each differential input in the
pair
Input Differential Voltage −100 +100 mV
Threshold
Receiver Differential Input 100 Ω Internal termination enabled
Impedance
Logic Outputs
Output Voltage
High 1375 mV
Low 1025 mV
Differential 225 mV
Offset 1200 mV

Rev. PrA | Page 8 of 48

Preliminary Technical Data AD9371
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DIGITAL SPECIFICATIONS (CMOS),
GPIO_3P3_x SIGNAL
Logic Inputs
Input Voltage
High Level VDDA_3P3 VDDA_3P3 V
× 0.8
Low Level 0 VDDA_3P3 V
× 0.2
Input Current
High Level −10 +10 µA
Low Level −10 +10 µA
Logic Outputs
Output Voltage
High Level VDDA_3P3 V
× 0.8
Low Level VDDA_3P3 V
× 0.2
Drive Capability 4 mA
1
VDDA_1P3 refers to all analog 1.3 V supplies including the following: VDDA_BB, VDDA_CLKSYNTH, VDDA_TXLO, VDDA_RXRF, VDDA_RXSYNTH, VDDA_RXVCO,
VDDA_RXTX, VDDA_TXSYNTH, VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH, VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO.
2
Synthesis bandwidth (BW) is the extended bandwidth used by digital correction algorithms to measure conditions and generate compensation.
3
Quadrature error correction (QEC) is the system for minimizing quadrature images of a desired signal.
4
Local oscillator leakage (LOL) is a measure of the amount of the LO signal that is passed from a mixer with the desired signal.
5
Adjacent channel level reduction (ACLR) is a measure of the amount of power from the desired signal leaking into an adjacent channel.
6
dBFS represents the ratio of the actual output signal to the maximum possible output level for a continuous wave output signal at the given RF attenuation setting.
7
Continuous wave (CW) is a single frequency signal.
8
Note that the input signal power limit does not correspond to 0 dBFS at the digital output because of the nature of the continuous time Σ-Δ ADCs. Unlike the hard
clipping characteristic of pipeline ADCs, these converters exhibit a soft overload behavior when the input approaches the maximum level.
9
Signal-to-noise ratio is limited by the baseband quantization noise.

CURRENT AND POWER CONSUMPTION SPECIFICATIONS

Table 2.
Parameter Min Typ Max Unit Test Conditions / Comments
SUPPLY CHARACTERISTICS
VDDA_1P3 Analog Supplies 1 1.267 1.3 1.33 V
VDIG Supply 1.267 1.3 1.33 V
VDDA_1P8 Supply 1.71 1.8 1.89 V
VDD_IF Supply 1.71 1.8 2.625 V CMOS and LVDS supply, 1.8 V to 2.5 V nominal range
VDDA_3P3 Supply 3.135 3.3 3.465 V
VDDA_SER, VDDA_DES, 1.14 1.3 1.365 V
JESD_VTT_DES Supplies
POSITIVE SUPPLY CURRENT (Rx MODE) Two Rx channels enabled, Tx upconverter disabled, 60 MHz
Rx BW, 122.88 MSPS data rate
VDDA_1P3 Analog Supplies1 1055 mA
VDIG Supply 625 mA Rx QEC 2 enabled, QEC2 engine active
VDD_IF Supply (CMOS and LVDS) 8 mA
VDDA_3P3 Supply 1 mA No auxiliary DACs or auxiliary ADCs enabled; if enabled, the
auxiliary ADC adds 2.7 mA, and each auxiliary ADC adds 1.5 mA
VDDA_SER, VDDA_DES, 375 mA
JESD_VTT_DES Supplies
Total Power Dissipation 2.70 W

Rev. PrA | Page 9 of 48

AD9371 Preliminary Technical Data
Parameter Min Typ Max Unit Test Conditions / Comments
POSITIVE SUPPLY CURRENT (Tx MODE) 250 MHz Tx BW, 245.76 MSPS data rate
VDDA_1P3 Analog Supplies1 1000 mA
VDIG Supply 410 mA Tx QEC2 active
VDDA_1P8 Supply Full scale CW 3
405 mA Tx RF attenuation = 0 dB,
80 mA Tx RF attenuation = 15 dB
VDD_IF Supply 8 mA
VDDA_3P3 Supply 1 mA No auxiliary DACs or auxiliary ADCs enabled; if enabled, the
auxiliary ADC adds 2.7 mA, and each auxiliary ADC adds 1.5 mA
VDDA_SER, VDDA_DES, 375 mA
JESD_VTT_DES Supplies
Total Power Dissipation Typical supply voltages, Tx QEC2 active
3.70 W Tx RF attenuation = 0 dB
3.11 W Tx RF attenuation = 15 dB
POSITIVE SUPPLY CURRENT (FDD 250 MHz Tx BW, 245.76 MSPS data rate
MODE), 2× Rx, 2× Tx, ORx ACTIVE
VDDA_1P3 Analog Supplies1 1700 mA
VDIG Supply 1080 mA Tx QEC2 active
VDDA_1P8 Supply Full scale CW3
405 mA Tx RF attenuation = 0 dB
80 mA Tx RF attenuation = 15 dB
VDD_IF Supply 8 mA
VDDA_3P3 Supply 2 mA No auxiliary DACs or auxiliary ADCs enabled; if enabled, the
auxiliary ADC adds 2.7 mA, and each auxiliary ADC adds 1.5 mA
VDDA_SER, VDDA_DES, 375 mA
JESD_VTT_DES Supplies
Total Power Dissipation Typical supply voltages, Tx QEC2 active
4.86 W Tx RF attenuation = 0 dB
4.27 W Tx RF attenuation = 15 dB
MAXIMUM OPERATING JUNCTION 110 °C Device designed for 10-year lifetime when operating at
TEMPERATURE maximum junction temperature
1
VDDA_1P3 refers to all analog 1.3 V supplies including the following: VDDA_BB, VDDA_CLKSYNTH, VDDA_TXLO, VDDA_RXRF, VDDA_RXSYNTH, VDDA_RXVCO,
VDDA_RXTX, VDDA_TXSYNTH, VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH, VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO.
2
QEC is the system for minimizing quadrature images of a desired signal.
3
Continuous wave (CW) is a single frequency signal.

Rev. PrA | Page 10 of 48

Preliminary Technical Data AD9371
TIMING SPECIFICATIONS
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SERIAL PERIPHERAL INTERFACE (SPI) TIMING
SCLK Period tCP 20 ns
SCLK Pulse Width tMP 10 ns
CSB Setup to First SCLK Rising Edge tSC 3 ns
Last SCLK Falling Edge to CSB Hold tHC 0 ns
SDIO Data Input Setup to SCLK tS 2 ns
SDIO Data Input Hold to SCLK tH 0 ns
SCLK Falling Edge to Output Data Delay (3- or 4-Wire Mode) tCO 3 8 ns
Bus Turnaround Time After Baseband Processor (BBP) Drives tHZM tH tCO ns
Last Address Bit
Bus Turnaround Time After AD9371 Drives Last Address Bit tHZS 0 tCO ns
DIGITAL TIMING
TXx_ENABLE Pulse Width 10 µs
RXx_ENABLE Pulse Width 10 µs
JESD204B DATA OUTPUT TIMING
Unit Interval UI 162.76 1627.6 ps
Data Rate per Channel (NRZ) 614.4 6144 Mbps
Rise Time tR 24 35 ps 20% to 80% in 100 Ω load
Fall Time tF 24 35 ps 20% to 80% in 100 Ω load
Output Common-Mode Voltage VCM 0 1.8 V AC-coupled
Termination Voltage (VTT) = 1.2 V 735 1135 mV DC-coupled
Differential Output Voltage VDIFF 360 466 770 mV
Short-Circuit Current IDSHORT −100 +100 mA
Differential Termination Impedance ZRDIFF 80 100 120 Ω
Total Jitter 17 48.8 ps Bit error rate (BER) = 10−15
Uncorrelated Bounded High Probability Jitter UBHPJ 1.2 24.4 ps
Duty-Cycle Distortion DCD 3 8.1 ps
SYSREF_IN Signal Setup Time to DEV_CLK_IN Signal ts 2.5 ns See Figure 2 and Figure 3
SYSREF_IN Signal Hold Time to DEV_CLK_IN Signal th −1.5 ns See Figure 2 and Figure 3
JESD204B DATA INPUT TIMING
Unit Interval UI 162.76 1627.6 ps
Data Rate per Channel (NRZ) 614.4 6144 Mbps
Input Common-Mode Voltage VCM 0.05 1.85 V AC-coupled
VTT = 1.2 V 720 1200 mV DC-coupled
Differential Input Voltage VDIFF 125 750 mV
VTT Source Impedance ZTT 1.2 30 Ω
Differential Termination Impedance ZRDIFF 80 106 120 Ω
VTT
AC-Coupled 1.27 1.33 V
DC-Coupled 1.14 1.26 V

Rev. PrA | Page 11 of 48

AD9371 Preliminary Technical Data
Timing Diagrams
DEV_CLK_IN DELAY
AT DEVICE PINS IN REFERENCE TO SYSREF AT DIGITAL CORE
tS tS
t'H t'H
tH tH t'S

DEV_CLK_IN

14651-002
tH = –1.5ns t'H = +0.5ns
tS = +2.5ns CLK DELAY = 2ns t'S = +0.5ns

Figure 2. SYSREF_IN Signal Setup and Hold Timing

tS tS tS tS

tH tH tH tH

DEV_CLK_IN

SYSREF_IN

14651-003
tH = –1.5ns
VALID SYSREF_IN INVALID SYSREF_IN tS = +2.5ns

Figure 3. SYSREF_IN Signal Setup and Hold Timing Examples Relative to DEV_CLK_IN Signal

Rev. PrA | Page 12 of 48

Preliminary Technical Data AD9371

ABSOLUTE MAXIMUM RATINGS

REFLOW PROFILE
Table 4.
Parameter Rating The AD9371 reflow profile is in accordance with the JEDEC
JESD20 criteria for Pb-free devices. The maximum reflow
VDDA_1P31 to VSSA −0.3 V to +1.4 V
temperature is 260°C.
VDDA_SER, VDDA_DES, and −0.3 V to +1.4 V
JESD_VTT_DES to VSSA THERMAL RESISTANCE
VDIG to VSSD −0.3 V to +1.4 V
Thermal performance is directly linked to PCB design and
VDDA_1P8 to VSSA −0.3 V to +2.0 V
operating environment. Careful attention to PCB thermal
VDD_IF to VSSA −0.3 V to +3.0 V
design is required.
VDDA_3P3 to VSSA −0.3 V to +3.9 V
Logic Inputs and Outputs to VSSD −0.3 V to VDD_IF + 0.3 V Table 5. Thermal Resistance
JESD204B Logic Outputs to VSSA −0.3 V to VDDA_SER Airflow
JESD204B Logic Inputs to VSSA -0.3 V to VDDA_DES Package Velocity1 (m/s) θJA2, 3 (°C/W) θJC2, 4 (°C/W)
Input Current to Any Pin Except ±10 mA BC-196-12
Supplies JEDEC5 0.0 20.5 0.05
Maximum Input Power into RF Ports 23 dBm (peak) 1.0 18.5 N/A6
(Excluding Sniffer Receiver Inputs)
2.5 17.2 N/A6
Maximum Input Power into SNRXA±, 2 dBm (peak)
10-Layer PCB 0.0 14.1 0.05
SNRXB±, and SNRXC±
1.0 12.4 N/A6
Maximum Junction Temperature (TJ MAX) 110°C
2.5 11.6 N/A6
Operating Temperature Range −40°C to +85°C
1
Storage Temperature Range −65°C to +150°C Power dissipation is 3.0 W for all test cases.
2
Per JEDEC JESD51-7 for JEDEC JESD51-5 2S2P test board.
3
1
VDDA_1P3 refers to all analog 1.3 V supplies: VDDA_BB, VDDA_CLKSYNTH, Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
4
VDDA_TXLO, VDDA_RXSYNTH, VDDA_RXVCO, VDDA_RXTX, VDDA_RXRF, Per MIL-STD 883, Method 1012.1.
5
VDDA_TXSYNTH, VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH, JEDEC entries refer to the JEDEC JESD51-9 (high-K thermal test board).
6
VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO. N/A means not applicable.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a ESD CAUTION
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. PrA | Page 13 of 48

AD9371 Preliminary Technical Data

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD9371
TOP VIEW
(Not to Scale)

1 2 3 4 5 6 7 8 9 10 11 12 13 14

VSSA ORX2+ ORX2– VSSA RX2+ RX2– VSSA VSSA RX1+ RX1– VSSA ORX1+ ORX1– VSSA
A

B VDDA_RXRF VSSA VSSA VSSA VSSA VSSA RX_EXTLO– RX_EXTLO+ VSSA VSSA VSSA VSSA VSSA VDDA_3P3

VSNRX_ VDDA_ VDDA_ VRX_

GPIO_3P3_0 GPIO_3P3_1 VSSA VDDA_RXLO VSSA VSSA AUXADC_1 AUXADC_2 GPIO_3P3_9 RBIAS
C VCO_LDO SNRXVCO RXVCO VCO_LDO

GPIO_3P3_3 SNRXC– SNRXB– SNRXA– GPIO_3P3_5 VSSA VSSA VSSA VSSA VDDA_1P8 AUXADC_3 GPIO_3P3_7 GPIO_3P3_8 GPIO_3P3_10
D

DEV_ DEV_
GPIO_3P3_4 SNRXC+ SNRXB+ SNRXA+ VDDA_BB VSSA VSSA VSSA TX_EXTLO– TX_EXTLO+ AUXADC_0 GPIO_3P3_6
E CLK_IN+ CLK_IN–

VDDA_ VTX_
GPIO_3P3_2 VDDA_RXTX VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VDDA_TXLO GPIO_3P3_11
F TXVCO VCO_LDO

VDDA_ VDDA_ VDDA_ VDDA_ VDDA_

VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA
G CALPLL CLKSYNTH SNRXSYNTH TXSYNTH RXSYNTH

TX2– VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA GPIO_12 GPIO_11 VSSA TX1+
H

GP_
TX2+ VSSA GPIO_18 RESET TEST GPIO_2 GPIO_1 SDIO SDO GPIO_13 GPIO_10 VSSA TX1–
J INTERRUPT

VSSA VSSA SYSREF_IN+ SYSREF_IN– GPIO_5 GPIO_4 GPIO_3 GPIO_0 SCLK CSB GPIO_14 GPIO_9 VSSA VSSA
K

VSSA VSSA SYNCINB1– SYNCINB1+ GPIO_6 GPIO_7 VSSD VDIG VDIG VSSD GPIO_15 GPIO_8 VSSA VSSA
L

VCLK_ RX1_ TX1_ RX2_ TX2_

VSSA SYNCINB0– SYNCINB0+ VSSA GPIO_17 GPIO_16 VDD_IF SYNCOUTB0+ SYNCOUTB0–
M VCO_LDO ENABLE ENABLE ENABLE ENABLE

N VDDA_CLK VSSA SERDOUT3– SERDOUT3+ SERDOUT2– SERDOUT2+ VSSA VDDA_SER VDDA_DES SERDIN2– SERDIN2+ SERDIN3– SERDIN3+ VSSA

JESD_VTT_
VSSA VSSA VSSA SERDOUT1– SERDOUT1+ SERDOUT0- SERDOUT0+ VDDA_SER VSSA SERDIN0– SERDIN0+ SERDIN1– SERDIN1+
P DES

14651-004
ANALOG DIGITAL DC POWER GROUND
INPUT/OUTPUT INPUT/OUTPUT

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Type1 Mnemonic Description
A1, A4, A7, A8, A11, A14, B2 to B6, I VSSA Analog ground.
B9 to B13, C5, C9, C10, D6 to D9,
E6, E9, E10, F3 to F10, G1 to G3, G5,
G10 to G14, H2 to H10, H13, J2, J13,
K1, K2, K13, K14, L1, L2, L13, L14,
M2, M9, N2, N7, N14, P1, P2, P3, P10
A2, A3 I ORX2+, ORX2− Differential Input for Observation Receiver 2. Do not
connect if these pins are unused.
A5, A6 I RX2+, RX2− Differential Input for Receiver 2. Do not connect if these pins
are unused.
A9, A10 I RX1+, RX1− Differential Input for Receiver 1. Do not connect if these pins
are unused.

Rev. PrA | Page 14 of 48

Preliminary Technical Data AD9371
Pin No. Type 1 Mnemonic Description
A12, A13 I ORX1+, ORX1− Differential Input for Observation Receiver 1. Do not
connect if these pins are unused.
B1 I VDDA_RXRF 1.3 V Supply Input.
B7, B8 I/O RX_EXTLO−, RX_EXTLO+ Differential Rx External LO Input/Output. If used for
external LO, the input frequency must be 2× the desired
carrier frequency. Do not connect if these pins are unused.
B14 I VDDA_3P3 Supply Voltage for GPIO_3P3_x.
C1, C2, C13, D1, D5, D12 to D14, I/O GPIO_3P3_0 to GPIO_3P3_11 General-Purpose Inputs and Outputs Referenced to 3.3 V
E1, E14, F1, F14 Supply. See Figure 4 to match the ball location to the
GPIO_3P3_x signal name. Some GPIO_3P3_x pins can also
function as auxiliary DAC outputs.
C3 O VSNRX_VCO_LDO Sniffer VCO LDO 1.1 V Output. Bypass this pin with a 1 µF
capacitor.
C4 I VDDA_SNRXVCO 1.3 V Supply Input for Sniffer VCO Low Dropout (LDO)
Regulator.
C6 I VDDA_RXLO 1.3 V Supply for the Rx Synthesizer LO Generator. This pin
is sensitive to aggressors.
C7 I VDDA_RXVCO 1.3 V Supply Input for Receiver VCO LDO Regulator.
C8 O VRX_VCO_LDO Receiver VCO LDO 1.1 V Output. Bypass this pin with a 1 µF
capacitor.
C11 I AUXADC_1 Auxiliary ADC 1 Input Pin.
C12 I AUXADC_2 Auxiliary ADC 2 Input Pin.
C14 N/A RBIAS Bias Resistor Connection. This pin generates an internal
current based on an external 1% resistor. Connect a
14.3 kΩ resistor between this pin and ground (VSSA).
D2, E2 I SNRXC−, SNRXC+ Differential Input for Sniffer Receiver Input C. If these pins are
unused, connect to VSSA with a short or with a 1 kΩ resistor.
D3, E3 I SNRXB−, SNRXB+ Differential Input for Sniffer Receiver Input B. If these pins are
unused, connect to VSSA with a short or with a 1 kΩ resistor.
D4, E4 I SNRXA−, SNRXA+ Differential Input for Sniffer Receiver Input A. If these pins are
unused, connect to VSSA with a short or with a 1 kΩ resistor.
D10 I VDDA_1P8 1.8 V Tx Supply.
D11 I AUXADC_3 Auxiliary ADC 3 Input Pin.
E5 I VDDA_BB 1.3 V Supply Input for ADCs, DACs, and Auxiliary ADCs.
E7, E8 I DEV_CLK_IN+, DEV_CLK_IN− Device Clock Differential Input.
E11, E12 I/O TX_EXTLO−, TX_EXTLO+ Differential Tx External LO Input/Output. If these pins are
used for the external LO, the input frequency must be 2×
the desired carrier frequency. Do not connect if these pins
are unused.
E13 I AUXADC_0 AUXADC 0 Input Pin.
F2 I VDDA_RXTX 1.3 V Supply Input for Tx/Rx Baseband Circuits,
Transimpedance Amplifier (TIA), Tx Transconductance (Gm),
Baseband Filters, and Auxiliary DACs.
F11 I VDDA_TXVCO 1.3 V Supply Input for Transmitter VCO LDO Regulator.
F12 I VDDA_TXLO 1.3 V Supply for the Tx Synthesizer LO Generator. This pin is
sensitive to aggressors.
F13 O VTX_VCO_LDO Transmitter VCO LDO 1.1 V Output. Bypass this pin with a
1 µF capacitor.
G4 I VDDA_CALPLL 1.3 V Supply Input for Calibration PLL Circuits. Use a
separate trace on the PCB back to a common supply point.
G6 I VDDA_CLKSYNTH 1.3 V Clock Synthesizer Supply Input. This pin is sensitive
to aggressors.
G7 I VDDA_SNRXSYNTH 1.3 V Sniffer Synthesizer Supply Input. This pin is sensitive
to aggressors.
G8 I VDDA_TXSYNTH 1.3 V Tx Synthesizer Supply Input. This pin is sensitive to
aggressors.
G9 I VDDA_RXSYNTH 1.3 V Rx Synthesizer Supply Input. This pin is sensitive to
aggressors.
Rev. PrA | Page 15 of 48
AD9371 Preliminary Technical Data
Pin No. Type 1 Mnemonic Description
H1, J1 O TX2−, TX2+ Differential Output for Transmitter 2.
H11, H12, J3, J7, J8, J11, J12, K5 to K8, I/O GPIO_0 to GPIO_18 General-Purpose Inputs and Outputs Referenced to
K11, K12, L5, L6, L11, L12, M10, M11 VDD_IF. See Figure 4 to match the ball location to the
GPIO_x signal name.
H14, J14 O TX1+, TX1− Differential Output for Transmitter 1.
J4 I RESET Active Low Chip Reset.
J5 O GP_INTERRUPT General-Purpose Interrupt Signal.
J6 I TEST Test Pin Used for JTAG Boundary Scan. Ground this pin if
unused.
J9 I/O SDIO Serial Data Input in 4-Wire Mode or Input/Output in 3-Wire
Mode.
J10 O SDO Serial Data Output.
K3, K4 I SYSREF_IN+, SYSREF_IN− LVDS SYSREF Clock Inputs for the JESD Interface.
K9 I SCLK Serial Data Bus Clock.
K10 I CSB Serial Data Bus Chip Select. Active low.
L3, L4 I SYNCINB1−, SYNCINB1+ LVDS Sync Signal Associated with ORx/Sniffer Channel
Data on the JESD Interface.
L7, L10 I VSSD Digital Ground.
L8, L9 I VDIG 1.3 V Digital Core Supply. Use a separate trace on the PCB
back to a common supply point.
M1 O VCLK_VCO_LDO Clock VCO LDO 1.1 V Output. Bypass this pin with a 1 µF
capacitor.
M3, M4 I SYNCINB0−, SYNCINB0+ LVDS Sync Signal Associated with Rx Channel Data on the
JESD Interface.
M5 I RX1_ENABLE Enables Rx Channel 1 Signal Path.
M6 I TX1_ENABLE Enables Tx Channel 1 Signal Path.
M7 I RX2_ENABLE Enables Rx Channel 2 Signal Path.
M8 I TX2_ENABLE Enables Tx Channel 2 Signal Path.
M12 I VDD_IF CMOS/LVDS Interface Supply.
M13, M14 O SYNCOUTB0+, SYNCOUTB0− LVDS Sync Signal Associated with Transmitter Channel
Data on the JESD Interface.
N1 I VDDA_CLK 1.3 V Clock Supply Input.
N3, N4 O SERDOUT3−, SERDOUT3+ RF Current Mode Logic (CML) Differential Output 3. This
JESD lane can be used by the receiver data or by the
sniffer/observation receiver data.
N5, N6 O SERDOUT2−, SERDOUT2+ RF CML Differential Output 2. This lane can be used by the
receiver data or by the sniffer/observation receiver data.
N8, P8 I VDDA_SER JESD204B 1.3 V Serializer Supply Input.
N9 I VDDA_DES JESD204B 1.3 V Deserializer Supply Input.
N10, N11 I SERDIN2−, SERDIN2+ RF CML Differential Input 2.
N12, N13 I SERDIN3−, SERDIN3+ RF CML Differential Input 3.
P4, P5 O SERDOUT1−, SERDOUT1+ RF CML Differential Output 1. This lane can be used by
receiver data or by sniffer/observation receiver data.
P6, P7 O SERDOUT0−, SERDOUT0+ RF CML Differential Output 0. This lane can be used by
receiver data or by sniffer/observation receiver data.
P9 I JESD_VTT_DES JESD204B Deserializer Termination Supply Input.
P11, P12 I SERDIN0−, SERDIN0+ RF CML Differential Input 0.
P13, P14 I SERDIN1−, SERDIN1+ RF CML Differential Input 1.
1
I is input, O is output, I/O is input/output, and N/A is not applicable.

Rev. PrA | Page 16 of 48

Preliminary Technical Data AD9371

TYPICAL PERFORMANCE CHARACTERISTICS

2.6 GHz BAND
Temperature settings refer to the die temperature. The die temperature is 40°C for single trace plots.
–30 100

90
–40
80
RECEIVER LO LEAKAGE (dBm)

–50

RECEIVER IIP2 (dBm)

70
–60 60

–70 50

40
–80
+110°C
+40°C 30
–90 –40°C
20
+110°C
–100 10 +40°C
–40°C
–110 0

14651-008
0 5 10 15 20 25 30
1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

2900

14651-005

F1 OFFSET FREQUENCY (MHz)

RECEIVER LO FREQUENCY (MHz)
Figure 5. Receiver LO Leakage vs. Receiver LO Frequency, 0 dB Receiver Figure 8. Receiver IIP2 vs. F1 Offset Frequency, 2600 MHz LO, 0 dB Attenuation,
Attenuation, 40 MHz RF Bandwidth, 122.88 MSPS Sample Rate 40 MHz RF Bandwidth, F2 = F1 + 1 MHz, 122.88 MSPS Sample Rate
45 100

40 90

80
RECEIVER NOISE FIGURE (dB)

35
RECEIVER IIP2 (dBm)

70
30
60
25
50
20
40
15
30
F2 – F1, +110°C
10 20 F2 – F1, +40°C
F2 – F1, –40°C
+110°C F2 + F1, +110°C
5 +40°C 10 F2 + F1, +40°C
–40°C F2 + F1, –40°C
0 0

14651-009
14651-006

0 3 6 9 12 15 5 10 15 20 25 30
RECEIVER ATTENUATION (dB) INTERMODULATION FREQUENCY (MHz)

Figure 6. Receiver Noise Figure vs. Receiver Attenuation, 2600 MHz LO, Figure 9. Receiver IIP2 vs. Intermodulation Frequency, 2600 MHz LO, 0 dB
40 MHz Bandwidth, 122.88 MSPS Sample Rate, 20 MHz Integration Attenuation, 40 MHz RF Bandwidth, 122.88 MSPS Sample Rate
Bandwidth (Includes 1.4 dB Matching Circuit Loss)
30 40

35
25
RECEIVER NOISE FIGURE (dB)

30
RECEIVER IIP3 (dBm)

20
25

15 20

+110°C 15
10 +40°C
–40°C
10
5
5 +110°C
+40°C
–40°C
0 0
14651-010
1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

2900

0 5 10 15 20 25 30
14651-007

F1 OFFSET FREQUENCY (MHz)

RECEIVER LO FREQUENCY (MHz)

Figure 7. Receiver Noise Figure vs. Receiver LO Frequency, 0 dB Receiver Figure 10. Receiver IIP3 vs. F1 Offset Frequency, 2600 MHz LO,
Attenuation, 40 MHz RF Bandwidth, 122.88 MSPS Sample Rate, 20 MHz 0 dB Attenuation, 40 MHz RF Bandwidth, F2 = 2F1 + 2 MHz,
Integration Bandwidth (Includes Matching Circuit Loss) 122.88 MSPS Sample Rate

Rev. PrA | Page 17 of 48

AD9371 Preliminary Technical Data
40 –40
+110°C
+40°C
35 –40°C
–50

RECEIVER DC OFFSET (dBFS)

30
RECEIVER IIP3 (dBm)

–60
25

20 –70

15
–80
10 F2 – 2F1, +110°C
F2 – 2F1, +40°C
F2 – 2F1, –40°C –90
5 F2 + 2F1, +110°C
F2 + 2F1, +40°C
F2 + 2F1, –40°C
0 –100

14651-014
14651-011
5 10 15 20 25 30 0 5 10 15 20 25 30
INTERMODULATION FREQUENCY (MHz) RECEIVER ATTENUATION (dB)

Figure 11. Receiver IIP3 vs. Intermodulation Frequency, 2600 MHz LO, Figure 14. Receiver DC Offset vs. Receiver Attenuation, 2600 MHz LO,
0 dB Attenuation, 40 MHz RF Bandwidth, 122.88 MSPS Sample Rate 40 MHz RF Bandwidth, 122.88 MSPS Sample Rate

–40 –40
+110°C +110°C
+40°C +40°C
–40°C –50 –40°C
–50
RECEIVER IMAGE (dBc)

RECEIVER HD2 (dBc) –60

–60

–70
–70
–80

–80
–90

–90
–100

–100 –110
14651-012

14651-015
0 5 10 15 20 25 30 0 5 10 15 20 25 30
RECEIVER ATTENUATION (dB) RECEIVER ATTENUATION (dB)

Figure 12. Receiver Image vs. Receiver Attenuation, 2600 MHz LO, Figure 15. Receiver HD2 vs. Receiver Attenuation, 2600 MHz LO,
Continuous Wave Signal 5 MHz Offset, 40 MHz RF Bandwidth, Continuous Wave Signal 5 MHz Offset, −20 dBm at 0 dB Attenuation,
Background Tracking Calibration (BTC) Active, 122.88 MSPS Sample Rate Input Power Increasing dB for dB with Attenuation,
40 MHz RF Bandwidth, 122.88 MSPS Sample Rate

25 –40
+110°C +110°C
+40°C +40°C
20 –40°C –50 –40°C

15
–60
RECEIVER GAIN (dB)

RECEIVER HD3 (dBc)

10
–70
5
–80
0

–90
–5

–10 –100

–15 –110
14651-013

14651-016

0 5 10 15 20 25 30 0 5 10 15 20 25 30
RECEIVER ATTENUATION (dB) RECEIVER ATTENUATION (dB)

Figure 13. Receiver Gain vs. Receiver Attenuation, 2600 MHz LO, Figure 16. Receiver HD3 vs. Receiver Attenuation, 2600 MHz LO,
Continuous Wave Signal 5 MHz Offset, 40 MHz RF Bandwidth, Continuous Wave Signal 5 MHz Offset, −20 dBm at 0 dB Attenuation,
122.88 MSPS Sample Rate Input Power Increasing dB for dB with Attenuation, 40 MHz RF Bandwidth,
122.88 MSPS Sample Rate

Rev. PrA | Page 18 of 48

Preliminary Technical Data AD9371
0 30
+110°C +110°C
+40°C +40°C
–5 –40°C –40°C
25

RECEIVER NOISE FIGURE (dB)

–10
RECEIVER EVM (dB)

–15 20

–20
15
–25

–30 10

–35
5
–40

–45 0

14651-017

14651-020
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 –40 –35 –30 –25 –20 –15 –10 –5 0
RECEIVER INPUT POWER (dBm) INTERFERER SIGNAL POWER (dBm)

Figure 17. Receiver EVM vs. Receiver Input Power, 2600 MHz LO, 40 MHz Figure 20. Receiver Noise Figure vs. Out of Band Interferer Signal Power,
RF Bandwidth, LTE 20 MHz Uplink Centered at DC, BTC Active, 2614 MHz LO, 2435 MHz Continuous Wave Interferer, Noise Figure
122.88 MSPS Sample Rate Integrated over 7 MHz to 10 MHz

0 0
+110°C
–10 –10 +40°C
–40°C
–20 –20
Rx2 TO Rx1 CROSSTALK (dB)

TRANSMITTER IMAGE (dBc)

–30 –30

–40 –40

–50 –50

–60 –60

–70 –70

–80 –80

–90 –90

–100 –100

14651-021
0 5 10 15 20
1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

2900

14651-018

RF ATTENUATION (dB)
RECEIVER LO FREQUENCY (MHz)

Figure 18. Rx2 to Rx1 Crosstalk vs. Receiver LO Frequency, 40 MHz Figure 21. Transmitter Image vs. RF Attenuation, 40 MHz RF Bandwidth,
RF Bandwidth, Continuous Wave Tone 3 MHz Offset from LO 2600 MHz LO, Transmitter QEC Tracking Run with Two 20 MHz LTE
Downlink Carriers, Then Image Measured with Continuous Wave 10 MHz
Offset from LO, 3 dB Digital Backoff, 245.76 MSPS Sample Rate
30 0
+110°C
–10 +40°C
–40°C
25
RECEIVER NOISE FIGURE (dB)

–20
TRANSMITTER IMAGE (dBc)

–30
20
–40

15 –50

–60
10
–70

–80
5
+110°C
+40°C –90
–40°C
0 –100
14651-019

14651-022

–50 –45 –40 –35 –30 –25 –20 –20 –15 –10 –5 0 5 10 15 20
INTERFERER SIGNAL POWER (dBm) DESIRED OFFSET FREQUENCY (MHz)
Figure 19. Receiver Noise Figure vs. Close-In Interferer Signal Power, Figure 22. Transmitter Image vs. Desired Offset Frequency, 40 MHz RF
2614 MHz LO, 2625 MHz Continuous Wave Interferer, Noise Figure Bandwidth, 2300 MHz LO, 0 dB RF Attenuation, Transmitter QEC Tracking
Integrated over 7 MHz to 10 MHz, 40 MHz RF Bandwidth Run with Two 20 MHz LTE Downlink Carriers, Then Image Measured with
Continuous Wave Signal, 3 dB Digital Backoff, 245.76 MSPS Sample Rate

Rev. PrA | Page 19 of 48

AD9371 Preliminary Technical Data
10 0

8 –10

6 –20

Tx1 TO Rx1 CROSSTALK (dB)

4 –30
Tx OUTPUT (dBm)

2 –40

0 –50

–2 –60

–4 –70

–6 –80
+110°C
–8 +40°C –90
–40°C
–10 –100
1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

2900

1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

2900
14651-023

14651-026
FREQUENCY (MHz) RECEIVER LO FREQUENCY (MHz)
Figure 23. Tx Output Power, Transmitter QEC, and External LO Leakage Active, Figure 26. Tx1 to Rx1 Crosstalk vs. Receiver LO Frequency,
5 MHz Continuous Wave Offset Signal, 1 MHz Resolution Bandwidth, 40 MHz Receiver RF Bandwidth, 40 MHz Transmitter RF Bandwidth,
245.76 MSPS Sample Rate Continuous Wave Signal 3 MHz Offset from LO

–60 0
+110°C
+40°C –10
–65 –40°C
TRANSMITTER LO LEAKAGE (dBFS)

–20
Tx2 TO Rx2 CROSSTALK (dB)
–70
–30
–75
–40

–80 –50

–85 –60

–70
–90
–80
–95
–90

–100 –100
14651-024

1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

2900
0 5 10 15 20

14651-027
RF ATTENUATION (dB)
RECEIVER LO FREQUENCY (MHz)

Figure 24. Transmitter LO Leakage vs. RF Attenuation, 2300 MHz LO, Figure 27. Tx2 to Rx2 Crosstalk vs. Receiver LO Frequency,
External Transmitter QEC and LO Leakage Tracking Active, Continuous Wave 40 MHz Receiver RF Bandwidth, 40 MHz Transmitter RF Bandwidth,
Signal 10 MHz Offset from LO, 6 dB Digital Backoff, 1 MHz Measurement Continuous Wave Signal 3 MHz Offset from LO
Bandwidth (If Input Power to the ORx Channel Is Not Held Constant,
Device Performance Degrades as Shown in This Figure)

–60 0
1.8GHz, +110°C –10
–65 1.8GHz, +40°C
TRANSMITTER LO LEAKAGE (dBFS)

1.8GHz, –40°C
2.3GHz, +110°C –20
Tx2 TO Tx1 CROSSTALK (dB)

–70 2.3GHz, +40°C

2.3GHz, –40°C –30
2.8GHz, +110°C
–75 2.8GHz, +40°C
2.8GHz, –40°C –40

–80 –50

–60
–85
–70
–90
–80
–95
–90

–100 –100
14651-025

1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

2900

–30 –20 –10 0 10 20 30

14651-028

OFFSET FREQUENCY (MHz)

TRANSMITTER LO FREQUENCY (MHz)

Figure 25. Transmitter LO Leakage vs. Offset Frequency, 2300 MHz LO, Figure 28. Tx2 to Tx1 Crosstalk vs. Transmitter LO Frequency,
External Transmitter QEC and LO Leakage Tracking Active, 6 dB Digital 40 MHz RF Bandwidth, Continuous Wave Signal 3 MHz Offset from LO
Backoff, 1 MHz Measurement Bandwidth

Rev. PrA | Page 20 of 48

Preliminary Technical Data AD9371
–80 –60
+110°C
–90 +40°C
–40°C –70
TRANSMITTER NOISE (dBm/Hz)

–100
–80
–110

PHASE NOISE (dBc)

–90
–120
–100
–130
–110
–140
–120
–150

–160 –130

–170 –140

–180

14651-029
–150

14651-032
0 5 10 15 20 100 1k 10k 100k 1M 10M
RF ATTENUATION (dB) OFFSET FREQUENCY (Hz)
Figure 29. Transmitter Noise vs. RF Attenuation, 2600 MHz LO, Figure 32. LO Phase Noise vs. Offset Frequency, 3 dB Digital Backoff,
10 MHz Offset Frequency 2600 MHz
–40 1.0
Tx ADJACENT CHANNEL LEAKAGE RATIO (dB)

+110°C UPPER
+40°C UPPER

Tx INTEGRATED PHASE NOISE (Degrees)

–45 –40°C UPPER 0.9
+110°C LOWER
+40°C LOWER 0.8
–50 –40°C LOWER
0.7
–55
0.6
–60 0.5

–65 0.4

0.3
–70
0.2
–75 +110°C
0.1 +40°C
–40°C
–80
14651-030

0
0 4 8 12 16 20
1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

2900

14651-033
RF ATTENUATION (dB)
TRANSMITTER LO FREQUENCY (MHz)
Figure 30. Tx Adjacent Channel Leakage Ratio vs. RF Attenuation, Figure 33. Tx Integrated Phase Noise vs. Transmitter LO Frequency,
2600 MHz LO, 40 MHz RF Bandwidth, Four-Carrier W-CDMA Desired 40 MHz RF Bandwidth, Continuous Wave 20 MHz Offset from LO,
Signal, Transmitter QEC and LO Leakage Tracking Active 3 dB Digital Backoff
–40 35
Tx ALTERNATE CHANNEL LEAKAGE RATIO (dB)

+110°C UPPER +110°C

+40°C UPPER +40°C
–45 –40°C UPPER –40°C
+110°C LOWER 30
+40°C LOWER
–50 –40°C LOWER
TRANSMITTER OIP3 (dBm)

25
–55
20
–60
15
–65

10
–70

–75 5

–80 0
14651-031

14651-034

0 4 8 12 16 20 0 2 4 6 8 10 12 14 16 18 20
RF ATTENUATION (dB) RF ATTENUATION (dB)

Figure 31. Tx Alternate Channel Leakage Ratio vs. RF Attenuation, Figure 34. Transmitter OIP3 vs. RF Attenuation, 2600 MHz LO,
2600 MHz LO, 40 MHz RF Bandwidth, Four-Carrier W-CDMA Desired 40 MHz RF Bandwidth, F1 = 20 MHz, F2 = 21 MHz, 3 dB Digital Backoff,
Signal, 2 dB Digital Backoff, Transmitter QEC and LO Leakage Tracking Active 245.76 MSPS Sample Rate

Rev. PrA | Page 21 of 48

AD9371 Preliminary Technical Data
0 0
+110°C
–10 –10 +40°C
–40°C
–20 –20

TRANSMITTER HD2 (dBc)

–30 –30
Tx OUTPUT (dBm)

–40 –40

–50 –50

–60 –60

–70 –70

–80 –80

–90 –90

–100 –100

14651-038
14651-035
2500 2525 2550 2575 2600 2625 2650 2675 2700 0 5 10 15 20
FREQUENCY (MHz) RF ATTENUATION (dB)

Figure 35. Transmitter Spectrum, 2 dB Digital and 3 dB RF Backoff, Figure 38. Transmitter HD2 vs. RF Attenuation, 2600 MHz LO,
40 MHz RF Bandwidth, Transmitter QEC and Internal LO Leakage Active, 2605 MHz Continuous Wave Desired Signal, 40 MHz RF Bandwidth,
LTE 10 MHz Signal, 2600 MHz LO, 1 MHz Resolution Bandwidth, 245.76 MSPS Sample Rate
245.76 MSPS Sample Rate

0 0
+110°C
–10 +40°C
–10 –40°C
–20
–20
TRANSMITTER HD3 (dBc)

–30
Tx OUTPUT (dBm)

–30
–40

–50 –40

–60 –50
–70
–60
–80
–70
–90

–100 –80

14651-039
0 5 10 15 20
2100

2200

2300

2400

2500

2600

2750

2800

2900

3000

3100

14651-036

RF ATTENUATION (dB)
FREQUENCY (MHz)
Figure 36. Transmitter Spectrum, 2 dB Digital and 3 dB RF Backoff, Figure 39. Transmitter HD3 vs. RF Attenuation, 2600 MHz LO,
40 MHz RF Bandwidth, Transmitter QEC and Internal LO Leakage Active, 2605 MHz Continuous Wave Desired Signal, 40 MHz RF Bandwidth,
LTE 10 MHz Signal, 2600 MHz LO, 1 MHz Resolution Bandwidth, 245.76 MSPS Sample Rate
245.76 MSPS Sample Rate

–20 10
+110°C +110°C
+40°C +40°C
TRANSMITTER OUTPUT POWER (dBm)

–40°C –40°C
–25 5
TRANSMITTER EVM (dB)

–30 0

–35 –5

–40 –10

–45 –15

–50 –20
14651-037

14651-040

0 4 8 12 16 20 0 5 10 15 20
RF ATTENUATION (dB) RF ATTENUATION (dB)

Figure 37. Transmitter EVM vs. RF Attenuation, 2550 MHz LO, Transmitter Figure 40. Transmitter Output Power vs. RF Attenuation, 2600 MHz LO,
LO Leakage and Transmitter QEC Tracking Active, 200 MHz RF Bandwidth, 2605 MHz Continuous Wave Desired Signal, 40 MHz RF Bandwidth,
LTE 20 MHz Downlink Signal, 245.76 MSPS Sample Rate 245.76 MSPS Sample Rate

Rev. PrA | Page 22 of 48

Preliminary Technical Data AD9371
0.10 30
+110°C

OBSERVATION RECEIVER NOISE FIGURE (dB)

0.08 +40°C
–40°C
Tx ATTENUATION STEP ERROR (dB)

25
0.06

0.04
20
0.02

0 15

–0.02
10
–0.04

–0.06
5
+110°C
–0.08 +40°C
–40°C
–0.10 0

14651-041
0 2 4 6 8 10 12 14 16 18 20

1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

2900

14651-044
RF ATTENUATION (dB)
OBSERVATION RECEIVER LO FREQUENCY (MHz)

Figure 41. Tx Attenuation Step Error vs. RF Attenuation, 2600 MHz LO, Figure 44. Observation Receiver Noise Figure vs. Observation Receiver
2610 MHz Continuous Wave Desired Signal, 40 MHz RF Bandwidth, LO Frequency, 0 dB Receiver Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate 245.76 MSPS Sample Rate, 100 MHz Integration Bandwidth

0.5 80

0.4 70

OBSERVATION RECEIVER IIP2 (dBm)

DEVIATION FROM FLATNESS (dB)

0.3
60
0.2
50
0.1

0 40

–0.1 30
–0.2
20
–0.3
10 +110°C
–0.4 +40°C
–40°C
–0.5 0

14651-045
14651-042

–100 –80 –60 –40 –20 0 20 40 60 80 100 0 10 20 30 40 50 60 70 80 90 100 110

FREQUENCY OFFSET FROM LO (MHz) F1 OFFSET FREQUENCY (MHz)

Figure 42. Transmitter Frequency Response Deviation from Flatness vs. Figure 45. Observation Receiver IIP2 vs. F1 Offset Frequency, 2600 MHz LO,
Frequency Offset from LO, 2600 MHz LO, 100 MHz RF Bandwidth, 0 dB Attenuation, 200 MHz RF Bandwidth, F2 = F1 + 1 MHz,
6 dB Digital Backoff, 245.76 MSPS Sample Rate 245.76 MSPS Sample Rate

–40 80
OBSERVATION RECEIVER LO LEAKAGE (dBm)

+110°C
+40°C
–45 –40°C 70
OBSERVATION RECEIVER IIP2 (dBm)

–50 60

–55 50

–60 40

–65 30

–70 20

10 +110°C
–75 +40°C
–40°C
0
14651-046

–80
5 15 25 35 45 55 65 75 85 95 105 115
1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

2900

14651-043

INTERMODULATION FREQUENCY (MHz)

OBSERVATION RECEIVER LO FREQUENCY (MHz)

Figure 43. Observation Receiver LO Leakage vs. Observation Receiver Figure 46. Observation Receiver IIP2 vs. Intermodulation Frequency,
LO Frequency, 0 dB Receiver Attenuation, 200 MHz RF Bandwidth, 2600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate 245.76 MSPS Sample Rate

Rev. PrA | Page 23 of 48

AD9371 Preliminary Technical Data
40 25
+110°C +110°C
+40°C +40°C
35 –40°C 20 –40°C
OBSERVATION RECEIVER IIP3 (dBm)

OBSERVATION RECEIVER GAIN (dB)

30 15

25 10

20 5

15 0

10 –5

5 –10

0 –15

14651-050
14651-047
0 10 20 30 40 50 60 70 80 90 100 110 0 3 6 9 12 15 18
F1 OFFSET FREQUENCY (MHz) OBSERVATION RECEIVER ATTENUATION (dB)

Figure 47. Observation Receiver IIP3 vs. F1 Offset Frequency, Figure 50. Observation Receiver Gain vs. Observation Receiver Attenuation,
2600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth, 2600 MHz LO, Continuous Wave Signal 25 MHz Offset,
F2 = 2F1 + 1 MHz, 245.76 MSPS Sample Rate 200 MHz RF Bandwidth, 245.76 MSPS Sample Rate

40 –40
+110°C

OBSERVATION RECEIVER DC OFFSET (dBFS)

+110°C
+40°C +40°C
35 –40°C –40°C
OBSERVATION RECEIVER IIP3 (dBm)

–50

30
–60
25

20 –70

15
–80

10
–90
5

–100

14651-051
0
14651-048

5 15 25 35 45 55 65 75 85 95 105 115 0 3 6 9 12 15 18
INTERMODULATION FREQUENCY (MHz) OBSERVATION RECEIVER ATTENUATION (dB)

Figure 48. Observation Receiver IIP3 vs. Intermodulation Frequency, Figure 51. Observation Receiver DC Offset vs. Observation Receiver
2600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth, Attenuation, 2600 MHz LO, 200 MHz RF Bandwidth, 245.76 MSPS Sample Rate
245.76 MSPS Sample Rate

0 0
+110°C +110°C
+40°C +40°C
–40°C
OBSERVATION RECEIVER IMAGE (dBc)

–40°C
OBSERVATION RECEIVER HD2 (dBc)

–20 –20

–40 –40

–60 –60

–80 –80

–100 –100

–120
14651-052

–120
14651-049

0 3 6 9 12 15 18 0 3 6 9 12 15 18
OBSERVATION RECEIVER ATTENUATION (dB) OBSERVATION RECEIVER ATTENUATION (dB)

Figure 49. Observation Receiver Image vs. Observation Receiver Attenuation, Figure 52. Observation Receiver HD2 vs. Observation Receiver Attenuation,
2600 MHz LO, Continuous Wave Signal 25 MHz Offset, 2600 MHz LO, Continuous Wave Signal 25 MHz Offset, −20 dBm at 0 dB
200 MHz RF Bandwidth, Background Tracking Calibration (BTC) Active, Attenuation, Input Power Increasing dB for dB with Attenuation,
245.76 MSPS Sample Rate 200 MHz RF Bandwidth, 245.76 MSPS Sample Rate

Rev. PrA | Page 24 of 48

Preliminary Technical Data AD9371
0 90
+110°C +110°C
+40°C +40°C
–40°C 80 –40°C
OBSERVATION RECEIVER HD3 (dBc)

–20

SNIFFER RECEIVER IIP2 (dBm)

70

–40 60

50
–60
40

–80 30

20
–100
10

–120 0

14651-053

14651-056
0 3 6 9 12 15 18 3 6 9 12
OBSERVATION RECEIVER ATTENUATION (dB) INTERMODULATION FREQUENCY (MHz)

Figure 53. Observation Receiver HD3 vs. Observation Receiver Attenuation, Figure 56. Sniffer Receiver IIP2 vs. Intermodulation Frequency, 2600 MHz LO,
2600 MHz LO, Continuous Wave Signal 25 MHz Offset, −20 dBm at 0 dB 0 dB Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
Attenuation, Input Power Increasing dB for dB with Attenuation,
200 MHz RF Bandwidth, 245.76 MSPS Sample Rate

–40 20
+110°C +110°C
+40°C +40°C
SNIFFER RECEIVER LO LEAKAGE (dBm)

–50 –40°C –40°C

15

SNIFFER RECEIVER IIP3 (dBm)

–60
10
–70

–80 5

–90
0
–100
–5
–110

–120 –10

14651-057
14651-054

2300 2400 2500 2600 2700 2800 0 2 4 6 8 10 12

SNIFFER RECEIVER LO FREQUENCY (MHz) INTERMODULATION FREQUENCY (MHz)

Figure 54. Sniffer Receiver LO Leakage vs. Sniffer Receiver LO Frequency, Figure 57. Sniffer Receiver IIP3 vs. Intermodulation Frequency, 2600 MHz
0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate LO, 0 dB Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate

30 0
+110°C +110°C
+40°C –10 +40°C
SNIFFER RECEIVER NOISE FIGURE (dB)

–40°C –40°C
25
SNIFFER RECEIVER IMAGE (dBc)

–20

–30
20
–40

15 –50

–60
10
–70

–80
5
–90

0 –100
14651-058
14651-055

2300 2400 2500 2600 2700 2800 0 5 10 15 20

SNIFFER RECEIVER LO FREQUENCY (MHz) SNIFFER RECEIVER ATTENUATION (dB)

Figure 55. Sniffer Receiver Noise Figure vs. Sniffer Receiver LO Frequency, Figure 58. Sniffer Receiver Image vs. Sniffer Receiver Attenuation,
0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate, 2600 MHz LO, Continuous Wave Signal 1 MHz Offset,
20 MHz Integration Bandwidth 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate

Rev. PrA | Page 25 of 48

AD9371 Preliminary Technical Data
–40 0
+110°C +110°C
+40°C +40°C
SNIFFER RECEIVER DC OFFSET (dBFS)

–40°C –5 –40°C
–50

SNIFFER RECEIVER EVM (dB)

–10
–60
–15

–70 –20

–80 –25

–30
–90
–35
–100
–40

–110 –45

14651-059

14651-062
0 5 10 15 20 –70 –65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10
SNIFFER RECEIVER ATTENUATION (dB) SNIFFER RECEIVER INPUT POWER (dBm)

Figure 59. Sniffer Receiver DC Offset vs. Sniffer Receiver Attenuation, Figure 62. Sniffer Receiver EVM vs. Sniffer Receiver Input Power,
2600 MHz LO, CS Signal 1 MHz Offset, −35 dBm at 0 dB Attenuation, 2600 MHz LO, 20 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC,
Input Power Increasing dB for dB with Attenuation, BTC Active, 30.72 MSPS Sample Rate
20 MHz RF Bandwidth, 30.72 MSPS Sample Rate

0 40
+110°C +110°C
–10 +40°C +40°C
–40°C 30 –40°C
–20
SNIFFER RECEIVER GAIN (dB)
SNIFFER RECEIVER HD2 (dBc)

20
–30
10
–40

–50 0

–60
–10
–70
–20
–80
–30
–90

–100 –40
14651-060

14651-063
0 5 10 15 20 0 4 8 12 16 20 24 28 32 36 40 44 48 52
SNIFFER RECEIVER ATTENUATION (dB) SNIFFER RECEIVER ATTENUATION (dB)

Figure 60. Sniffer Receiver HD2 vs. Sniffer Receiver Attenuation, 2600 MHz LO, Figure 63. Sniffer Receiver Gain vs. Sniffer Receiver Attenuation,
Continuous Wave Signal 1 MHz Offset, −35 dBm at 0 dB Attenuation, 2600 MHz LO, Continuous Wave Signal 1 MHz Offset,
Input Power Increasing dB for dB with Attenuation, 20 MHz RF Bandwidth, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
30.72 MSPS Sample Rate

0
+110°C
+40°C
–40°C
–20
SNIFFER RECEIVER HD3 (dBc)

–40

–60

–80

–100

–120
14651-061

0 5 10 15 20
SNIFFER RECEIVER ATTENUATION (dB)

Figure 61. Sniffer Receiver HD3 vs. Sniffer Receiver Attenuation, 2600 MHz LO,
Continuous Wave Signal 1 MHz Offset, −35 dBm at 0 dB Attenuation,
Input Power Increasing dB for dB with Attenuation, 20 MHz RF Bandwidth,
30.72 MSPS Sample Rate

Rev. PrA | Page 26 of 48

Preliminary Technical Data AD9371
3.5 GHz BAND
–30 90
+110°C
–35 +40°C
–40°C 80

–40
RECEIVER LO LEAKAGE (dBm)

70
–45

RECEIVER IIP2 (dBm)

60
–50
50
–55
40
–60
30
–65
20
–70
+110°C
–75 10 +40°C
–40°C
–80 0

14651-064

14651-067
3300 3400 3500 3600 3700 3800 5 10 15 20 25 30 35 40 45 50 55 60
RECEIVER LO FREQUENCY (MHz) F1 OFFSET FREQUENCY (MHz)

Figure 64. Receiver LO Leakage vs. Receiver LO Frequency, 0 dB Receiver Figure 67. Receiver IIP2 vs. F1 Offset Frequency, 3500 MHz LO, 0 dB
Attenuation, 100 MHz RF Bandwidth, 153.6 MSPS Sample Rate Attenuation, 40 MHz RF Bandwidth, F2 = F1 + 1 MHz, 153.6 MSPS Sample Rate

45 100
+110°C F2 – F1, +110°C
+40°C 90 F2 – F1, +40°C
40 –40°C F2 – F1, –40°C
F2 + F1, +110°C
80
RECEIVER NOISE FIGURE (dB)

35 F2 + F1, +40°C
F2 + F1, –40°C
RECEIVER IIP2 (dBm)
70
30
60
25
50
20
40
15
30
10
20

5 10

0 0

14651-068
14651-065

5 10 15 20 25 30 35 40 45 50 55 60
RECEIVER ATTENUATION (dB) INTERMODULATION FREQUENCY (MHz)

Figure 65. Receiver Noise Figure vs. Receiver Attenuation, 3500 MHz LO, Figure 68. Receiver IIP2 vs. Intermodulation Frequency, 3500 MHz LO,
100 MHz Bandwidth, 153.6 MSPS Sample Rate, 50 MHz Integration 0 dB Attenuation, 40 MHz RF Bandwidth, 153.6 MSPS Sample Rate
Bandwidth (Includes 1 dB Matching Circuit Loss)

30 40
+110°C +110°C
+40°C +40°C
–40°C 35 –40°C
25
RECEIVER NOISE FIGURE (dB)

30
RECEIVER IIP3 (dBm)

20
25

15 20

15
10
10

5
5

0 0
14651-069
14651-066

3300 3400 3500 3600 3700 3800 5 10 15 20 25 30 35 40 45 50 55 60

RECEIVER LO FREQUENCY (MHz) F1 OFFSET FREQUENCY (MHz)

Figure 66. Receiver Noise Figure vs. Receiver LO Frequency, Figure 69. Receiver IIP3 vs. F1 Offset Frequency, 3500 MHz LO,
0 dB Receiver Attenuation, 100 MHz RF Bandwidth, 153.6 MSPS Sample Rate, 0 dB Attenuation, 100 MHz RF Bandwidth, F2 = 2F1 + 1 MHz,
50 MHz Integration Bandwidth (Includes Matching Circuit Loss) 153.6 MSPS Sample Rate

Rev. PrA | Page 27 of 48

AD9371 Preliminary Technical Data
40
F2 – F1, +110°C +110°C
F2 – F1, +40°C +40°C
35 F2 – F1, –40°C –40°C
F2 + F1, +110°C

RECEIVER DC OFFSET (dBFS)

F2 + F1, +40°C
30 F2 + F1, –40°C
RECEIVER IIP3 (dBm)

25

20

15

10

14651-070

14651-073
5 10 15 20 25 30 35 40 45 50 55 60
INTERMODULATION FREQUENCY (MHz) RECEIVER ATTENUATION (dB)

Figure 70. Receiver IIP3 vs. Intermodulation Frequency, 3500 MHz LO, Figure 73. Receiver DC Offset vs. Receiver Attenuation, 3500 MHz LO,
0 dB Attenuation, 100 MHz RF Bandwidth, 153.6 MSPS Sample Rate 100 MHz RF Bandwidth, 153.6 MSPS Sample Rate

–40 –40
+110°C +110°C
+40°C +40°C
–50 –40°C –50 –40°C
RECEIVER IMAGE (dBc)

–60 RECEIVER HD2 (dBc) –60

–70 –70

–80 –80

–90 –90

–100 –100

–110 –110
14651-071

14651-074
RECEIVER ATTENUATION (dB) RECEIVER ATTENUATION (dB)

Figure 71. Receiver Image vs. Receiver Attenuation, 3500 MHz LO, Figure 74. Receiver HD2 vs. Receiver Attenuation, 3500 MHz LO,
Continuous Wave Signal 17 MHz Offset, 100 MHz RF Bandwidth, Continuous Wave Signal 17 MHz Offset, −14dBm at 0 dB Attenuation,
Background Tracking Calibration (BTC) Active, 153.6 MSPS Sample Rate Input Power Increasing dB for dB with Attenuation,
100 MHz RF Bandwidth, 153.6 MSPS Sample Rate

25 –40
+110°C +110°C
+40°C +40°C
20 –40°C –50 –40°C

15
–60
RECEIVER GAIN (dB)

RECEIVER HD3 (dBc)

10
–70
5
–80
0

–90
–5

–10 –100

–15 –110
14651-072

14651-075

RECEIVER ATTENUATION (dB) RECEIVER ATTENUATION (dB)

Figure 72. Receiver Gain vs. Receiver Attenuation, 3500 MHz LO, Figure 75. Receiver HD3 vs. Receiver Attenuation, 3500 MHz LO,
Continuous Wave Signal 17 MHz Offset, 100 MHz RF Bandwidth, Continuous Wave Signal 17 MHz Offset, −14 dBm at 0 dB Attenuation,
De-Embedded to Receiver Port, 153.6 MSPS Sample Rate Input Power Increasing dB for dB with Attenuation, 100 MHz RF Bandwidth,
153.6 MSPS Sample Rate

Rev. PrA | Page 28 of 48

Preliminary Technical Data AD9371
0 30
+110°C +110°C
+40°C +40°C
–5 –40°C –40°C
25

RECEIVER NOISE FIGURE (dB)

–10
RECEIVER EVM (dB)

–15 20

–20
15
–25

–30 10

–35
5
–40

–45

14651-076
0

14651-079
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 –30 –25 –20 –15 –10 –5 0
RECEIVER INPUT POWER (dBm) INTERFERER SIGNAL POWER (dBm)
Figure 76. Receiver EVM vs. Receiver Input Power, 3600 MHz LO, 100 MHz Figure 79. Receiver Noise Figure vs. Out of Band Interferer Signal Power,
RF Bandwidth, LTE 20 MHz Uplink Centered at DC, BTC Active, 3614 MHz LO, 3665 MHz Continuous Wave Interferer,
153.6 MSPS Sample Rate Noise Figure Integrated over 7 MHz to 10 MHz
0
+110°C
–10 +40°C
–40°C
–20
Rx2 TO Rx1 CROSSTALK (dB)

TRANSMITTER IMAGE (dBc)

–30

–40

–50

–60

–70

–80

–90

–100
14651-077

14651-080
3300 3400 3500 3600 3700 3800
RECEIVER LO FREQUENCY (MHz) RF ATTENUATION (dB)
Figure 77. Rx2 to Rx1 Crosstalk vs. Receiver LO Frequency, Figure 80. Transmitter Image vs. RF Attenuation, 100 MHz RF Bandwidth,
100 MHz RF Bandwidth, Continuous Wave Tone 3 MHz Offset from LO 3550 MHz LO, Transmitter QEC Tracking Run with Two 20 MHz,
LTE Downlink Carriers, Then Image Measured with Continuous Wave
10 MHz Offset from LO, 6 dB Digital Backoff, 307.2 MSPS Sample Rate
30
+110°C
+40°C +110°C
28 +40°C
–40°C
–40°C
26
RECEIVER NOISE FIGURE (dB)

TRANSMITTER IMAGE (dBc)

24

22

20

18

16

14

12

10
14651-078

14651-081

–50 –45 –40 –35 –30 –25 –20 –50 –40 –30 –20 –10 0 10 20 30 40 50
INTERFERER SIGNAL POWER (dBm) DESIRED OFFSET FREQUENCY (MHz)
Figure 78. Receiver Noise Figure vs. Close-In Interferer Signal Power, Figure 81. Transmitter Image vs. Desired Signal Offset, 100 MHz RF
3614 MHz LO, 3625 MHz Continuous Wave Interferer, Noise Figure Bandwidth, 3550 MHz LO, 0 dB RF Attenuation, Transmitter QEC Tracking
Integrated over 7 MHz to 10 MHz, 100 MHz RF Bandwidth Run with Two 20 MHz LTE Downlink Carriers, Then Image Measured with
Continuous Wave Signal, 6 dB Digital Backoff, 307.2 MSPS Sample Rate

Rev. PrA | Page 29 of 48

AD9371 Preliminary Technical Data
10 0

8 –10

6 –20

Tx1 TO Rx1 CROSSTALK (dB)

4 –30
Tx OUTPUT (dBm)

2 –40

0 –50

–2 –60

–4 –70

–6 –80
+110°C
–8 +40°C –90
–40°C
–10 –100

14651-082

14651-085
3300 3400 3500 3600 3700 3800 3300 3400 3500 3600 3700 3800
FREQUENCY (MHz) RECEIVER LO FREQUENCY (MHz)

Figure 82. Tx Output Power Spectrum, Transmitter QEC and Figure 85. Tx1 to Rx1 Crosstalk vs. Receiver LO Frequency,
External LO Leakage Active, 5 MHz Continuous Wave Offset Signal, 100 MHz Receiver RF Bandwidth, 40 MHz Transmitter RF Bandwidth,
1 MHz Resolution Bandwidth, 307.2 MSPS Sample Rate Continuous Wave Signal 3 MHz Offset from LO

–60 0
+110°C
+40°C –10
–65 –40°C
TRANSMITTER LO LEAKAGE (dBFS)

–20
–70 Tx2 TO Rx2 CROSSTALK (dB)
–30
–75
–40

–80 –50

–60
–85
–70
–90
–80
–95
–90

–100 –100

14651-086
14651-083

0 5 10 15 20 3300 3400 3500 3600 3700 3800

RF ATTENUATION (dB) RECEIVER LO FREQUENCY (MHz)

Figure 83. Transmitter LO Leakage vs. RF Attenuation, 3550 MHz LO, Figure 86. Tx2 to Rx2 Crosstalk vs. Receiver LO Frequency,
External Transmitter QEC and LO Leakage Tracking Active, 100 MHz Receiver RF Bandwidth, 40 MHz Transmitter RF Bandwidth,
Continuous Wave Signal 10 MHz Offset from LO, 6 dB Digital Backoff, Continuous Wave Signal 3 MHz Offset from LO
1 MHz Measurement Bandwidth (Note that if Input power to ORx channel
is not held constant, performance will degrade as shown in this plot)

0
3.3GHz, +110°C
3.3GHz, +40°C –10
3.3GHz, –40°C
TRANSMITTER LO LEAKAGE (dBFS)

3.55GHz, +110°C
–20
Tx2 TO Tx1 CROSSTALK (dB)

3.55GHz, +40°C
3.55GHz, –40°C
3.8GHz, +110°C –30
3.8GHz, +40°C
3.8GHz, –40°C –40

–50

–60

–70

–80

–90

–100
14651-084

14651-087

–30 –20 –10 0 10 20 30 3300 3400 3500 3600 3700 3800

OFFSET FREQUENCY (MHz) TRANSMITTER LO FREQUENCY (MHz)

Figure 84. Transmitter LO Leakage vs. Offset Frequency, Figure 87. Tx2 to Tx1 Crosstalk vs. Transmitter LO Frequency,
External Transmitter QEC, and LO Leakage Tracking Active, 100 MHz RF Bandwidth, Continuous Wave Signal 3 MHz Offset from LO
6 dB Digital Backoff, 1 MHz Measurement Bandwidth

Rev. PrA | Page 30 of 48

Preliminary Technical Data AD9371
–80 –60
+110°C
+40°C
–90 –40°C –70
TRANSMITTER NOISE (dBm/Hz)

–100
–80

LO PHASE NOISE (dBc)

–110
–90
–120
–100
–130
–110
–140
–120
–150

–160 –130

–170 –140

–180 –150

14651-088

14651-091
0 5 10 15 20 100 1k 10k 100k 1M 10M
RF ATTENUATION (dB) OFFSET FREQUENCY (Hz)

Figure 88. Transmitter Noise vs. RF Attenuation, 3500 MHz LO, Figure 91. LO Phase Noise vs. Offset Frequency, 3 dB Digital Backoff,
100 MHz Offset Frequency, Zeros Input Data 3500 MHz LO

–40 1.0
Tx ADJACENT CHANNEL LEAKAGE RATIO (dB)

+110°C UPPER +110°C

+40°C UPPER +40°C

Tx INTEGRATED PHASE NOISE (Degrees)

0.9
–45 –40°C UPPER –40°C
+110°C LOWER
+40°C LOWER 0.8
–50 –40°C LOWER
0.7
–55 0.6

–60 0.5

0.4
–65
0.3
–70
0.2

–75 0.1

–80 0

14651-092
14651-089

0 5 10 15 20 3300 3400 3500 3600 3700 3800

RF ATTENUATION (dB) TRANSMITTER LO FREQUENCY (MHz)

Figure 89. Tx Adjacent Channel Leakage Ratio vs. RF Attenuation, Figure 92. Tx Integrated Phase Noise vs. Transmitter LO Frequency,
3500 MHz LO, 100 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal, 100 MHz RF Bandwidth, Continuous Wave 20 MHz Offset from LO,
2 dB Digital Backoff, Transmitter QEC and LO Leakage Tracking Active 3 dB Digital Backoff

–40 35
Tx ALTERNATE CHANNEL LEAKAGE RATIO (dB)

+110°C UPPER +110°C

+40°C UPPER +40°C
–45 –40°C UPPER 30 –40°C
+110°C LOWER
+40°C LOWER
TRANSMITTER OIP3 (dBm)

–50 –40°C LOWER

25

–55
20
–60
15
–65
10
–70

5
–75

0
14651-093

–80
14651-090

0 5 10 15 20 0 2 4 6 8 10 12 14 16 18 20
RF ATTENUATION (dB) RF ATTENUATION (dB)

Figure 90. Tx Alternate Channel Leakage Ratio vs. RF Attenuation, Figure 93. Transmitter OIP3 vs. RF Attenuation, 3500 MHz LO,
3500 MHz LO, 100 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal, 100 MHz RF Bandwidth, F1 = 20 MHz, F2 = 21 MHz, 3 dB Digital Backoff,
2 dB Digital Backoff, Transmitter QEC and LO Leakage Tracking Active 307.2 MSPS Sample Rate

Rev. PrA | Page 31 of 48

AD9371 Preliminary Technical Data
0 0
+110°C
–10 –10 +40°C
–40°C
–20 –20

TRANSMITTER HD2 (dBc)

–30 –30
Tx OUTPUT (dBm)

–40 –40

–50 –50

–60 –60

–70 –70

–80 –80

–90 –90

–100 –100

14651-094

14651-097
3400 3425 3450 3475 3500 3525 3550 3575 3600 0 5 10 15 20
FREQUENCY (MHz) RF ATTENUATION (dB)

Figure 94. Tx Spectrum, 2 dB Digital and 3 dB RF Backoff, 100 MHz RF Figure 97. Transmitter HD2 vs. RF Attenuation, 3500 MHz LO,
Bandwidth, Transmitter QEC and Internal LO Leakage Active, LTE 10 MHz 3505 MHz Continuous Wave Desired Signal, 100 MHz RF Bandwidth,
Signal, 3500 MHz LO, 1 MHz Resolution Bandwidth, 307.2 MSPS Sample Rate 307.2 MSPS Sample Rate

0 0
+110°C
–10 +40°C
–10 –40°C
–20
TRANSMITTER HD3 (dBc) –20
–30
Tx OUTPUT (dBm)

–30
–40

–50 –40

–60
–50
–70
–60
–80
–70
–90

–100 –80
14651-095

14651-098
3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000 0 5 10 15 20
FREQUENCY (MHz) RF ATTENUATION (dB)

Figure 95. Transmitter Spectrum, 2 dB Digital and 3 dB RF Backoff, Figure 98. Transmitter HD3 vs. RF Attenuation, 3500 MHz LO,
100 MHz RF Bandwidth, Transmitter QEC and Internal LO Leakage Active, 3505 MHz Continuous Wave Desired Signal, 100 MHz RF Bandwidth,
LTE 10 MHz Signal, 3500 MHz LO, 1 MHz Resolution Bandwidth, 307.2 MSPS Sample Rate
307.2 MSPS Sample Rate (Noise Floor Includes Test Equipment Response)

–20 10
+110°C +110°C
+40°C +40°C
TRANSMITTER OUTPUT POWER (dBm)

–40°C 5 –40°C
–25
TRANSMITTER EVM (dB)

0
–30

–5
–35
–10

–40
–15

–45
–20

–50 –25
14651-096

14651-099

0 5 10 15 20 0 5 10 15 20
RF ATTENUATION (dB) RF ATTENUATION (dB)

Figure 96. Transmitter EVM vs. RF Attenuation, 3500 MHz LO, Figure 99. Transmitter Output Power vs. RF Attenuation, 3500 MHz LO,
Transmitter LO Leakage, and Transmitter QEC Tracking Active, 200 MHz 3505 MHz Continuous Wave Desired Signal, 100 MHz RF Bandwidth,
RF Bandwidth, LTE 20 MHz Downlink Signal, 307.2 MSPS Sample Rate 2 dB Digital Backoff, 307.2 MSPS Sample Rate

Rev. PrA | Page 32 of 48

Preliminary Technical Data AD9371
0.10
+110°C
+40°C 30
0.08

OBSERVATION RECEIVER NOISE FIGURE (dB)

–40°C
Tx ATTENUATION STEP ERROR (dB)

0.06
25
0.04

0.02 20
0

–0.02 15

–0.04
10
–0.06

–0.08
5
+110°C
–0.10 +40°C

14651-100
0 2 4 6 8 10 12 14 16 18 20 –40°C
RF ATTENUATION (dB) 0

14651-103
3300 3400 3500 3600 3700 3800
OBSERVATION RECEIVER LO FREQUENCY (MHz)
Figure 100. Tx Attenuation Step Error vs. RF Attenuation, 3500 MHz LO, Figure 103. Observation Receiver Noise Figure vs. Observation Receiver
3510 MHz Continuous Wave Desired Signal, 100 MHz RF Bandwidth, LO Frequency, 0 dB Receiver Attenuation, 240 MHz RF Bandwidth,
De-Embedded to Transmitter Port, 307.2 MSPS Sample Rate 307.2 MSPS Sample Rate, 120 MHz Integration Bandwidth
1.0 80
0.8
70

OBSERVATION RECEIVER IIP2 (dBm)

DEVIATION FROM FLATNESS (dB)

0.6
60
0.4

0.2 50

0 40

–0.2
30
–0.4
20
–0.6

10 +110°C
–0.8 +40°C
–40°C
–1.0 0
14651-101

14651-104
–100 –80 –60 –40 –20 0 20 40 60 80 100 0 10 20 30 40 50 60 70 80 90 100 110
FREQUENCY OFFSET FROM LO (MHz) F1 OFFSET FREQUENCY (MHz)
Figure 101. Transmitter Frequency Response Deviation from Flatness vs. Figure 104. Observation Receiver IIP2 vs. F1 Offset Frequency, 3600 MHz LO,
Frequency Offset from LO, 3500 MHz LO, 100 MHz RF Bandwidth, 0 dB Attenuation, 240 MHz RF Bandwidth, F2 = F1 + 1 MHz,
6 dB Digital Backoff, 307.2 MSPS Sample Rate 307.2 MSPS Sample Rate
–40 80
OBSERVATION RECEIVER LO LEAKAGE (dBm)

+110°C +110°C
+40°C +40°C
–45 –40°C 70 –40°C
OBSERVATION RECEIVER IIP2 (dBm)

–50 60

–55 50

–60 40

–65 30

–70 20

–75 10

–80 0
14651-102

14651-105

3300 3400 3500 3600 3700 3800 5 15 25 35 45 55 65 75 85 95 105 115

OBSERVATION RECEIVER LO FREQUENCY (MHz) INTERMODULATION FREQUENCY (MHz)
Figure 102. Observation Receiver LO Leakage vs. Observation Receiver Figure 105. Observation Receiver IIP2 vs. Intermodulation Frequency,
LO Frequency, 0 dB Receiver Attenuation, 240 MHz RF Bandwidth, 3500 MHz LO, 0 dB Attenuation, 240 MHz RF Bandwidth,
307.2 MSPS Sample Rate 307.2 MSPS Sample Rate

Rev. PrA | Page 33 of 48

AD9371 Preliminary Technical Data
40 25
+110°C +110°C
+40°C +40°C
35 –40°C 20 –40°C
OBSERVATION RECEIVER IIP3 (dBm)

OBSERVATION RECEIVER GAIN (dB)

30 15

25 10

20 5

15 0

10 –5

5 –10

0 –15

14651-106

14651-109
0 10 20 30 40 50 60 70 80 90 100 110 0 3 6 9 12 15 18
F1 OFFSET FREQUENCY (MHz) OBSERVATION RECEIVER ATTENUATION (dB)

Figure 106. Observation Receiver IIP3 vs. F1 Offset Frequency, 3600 MHz LO, Figure 109. Observation Receiver Gain vs. Observation Receiver
0 dB Attenuation, 240 MHz RF Bandwidth, F2 = 2F1 + 1 MHz, Attenuation, 3500 MHz LO, Continuous Wave Signal 25 MHz Offset,
307.2 MSPS Sample Rate 240 MHz RF Bandwidth, De-Embedded to Receiver Port,
307.2 MSPS Sample Rate

40 –40
+110°C +110°C

OBSERVATION RECEIVER DC OFFSET (dBFS)

+40°C +40°C
35 –40°C –50 –40°C
OBSERVATION RECEIVER IIP3 (dBm)

30 –60

25 –70

20 –80

15 –90

10 –100

5 –110

0 –120
14651-107

14651-110
5 15 25 35 45 55 65 75 85 95 105 115 0 3 6 9 12 15 18
INTERMODULATION FREQUENCY (MHz) OBSERVATION RECEIVER ATTENUATION (dB)

Figure 107. Observation Receiver IIP3 vs. Intermodulation Frequency, Figure 110. Observation Receiver DC Offset vs. Observation Receiver
3500 MHz LO, 0 dB Attenuation, 240 MHz RF Bandwidth, Attenuation, 3500 MHz LO, 240 MHz RF Bandwidth, 307.2 MSPS Sample Rate
307.2 MSPS Sample Rate

0 0
+110°C +110°C
–10 +40°C +40°C
OBSERVATION RECEIVER IMAGE (dBc)

–40°C –40°C
OBSERVATION RECEIVER HD2 (dBc)

–20
–20

–30
–40
–40

–50 –60

–60
–80
–70

–80
–100
–90

–100 –120
14651-108

14651-111

0 3 6 9 12 15 18 0 3 6 9 12 15 18
OBSERVATION RECEIVER ATTENUATION (dB) OBSERVATION RECEIVER ATTENUATION (dB)

Figure 108. Observation Receiver Image vs. Observation Receiver Attenuation, Figure 111. Observation Receiver HD2 vs. Observation Receiver
3500 MHz LO, Continuous Wave Signal 25 MHz Offset, Attenuation, 3500 MHz LO, Continuous Wave Signal 25 MHz Offset,
240 MHz RF Bandwidth, Background Tracking Calibration (BTC) Active, −20 dBm at 0 dB Attenuation, Input Power Increasing dB for dB with
307.2 MSPS Sample Rate Attenuation, 240 MHz RF Bandwidth, 307.2 MSPS Sample Rate

Rev. PrA | Page 34 of 48

Preliminary Technical Data AD9371
0 90
+110°C +110°C
–10 +40°C +40°C
–40°C 80 –40°C
OBSERVATION RECEIVER HD3 (dBc)

–20

SNIFFER RECEIVER IIP2 (dBm)

70
–30
60
–40
50
–50
40
–60
30
–70
20
–80

–90 10

–100 0

14651-112

14651-115
0 3 6 9 12 15 18 2 6 10 14 18
OBSERVATION RECEIVER ATTENUATION (dB) INTERMODULATION FREQUENCY (MHz)

Figure 112. Observation Receiver HD3 vs. Observation Receiver Figure 115. Sniffer Receiver IIP2 vs. Intermodulation Frequency, 3500 MHz LO,
Attenuation, 3500 MHz LO, Continuous Wave Signal 25 MHz Offset, 0 dB Attenuation, 20 MHz RF Bandwidth, 38.4 MSPS Sample Rate
−20 dBm at 0 dB Attenuation, Input Power Increasing dB for dB with
Attenuation, 240 MHz RF Bandwidth, 307.2 MSPS Sample Rate

–40 20
+110°C +110°C
+40°C +40°C
SNIFFER RECEIVER LO LEAKAGE (dBm)

–50 –40°C –40°C

15

SNIFFER RECEIVER IIP3 (dBm)

–60
10
–70

–80 5

–90
0
–100
–5
–110

–120 –10
14651-113

14651-116
3300 3400 3500 3600 3700 3800 0 2 4 6 8 10 12
SNIFFER RECEIVER LO FREQUENCY (MHz) INTERMODULATION FREQUENCY (MHz)

Figure 113. Sniffer Receiver LO Leakage vs. Sniffer Receiver LO Frequency, Figure 116. Sniffer Receiver IIP3 vs. Intermodulation Frequency, 3500 MHz LO,
0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 38.4 MSPS Sample Rate 0 dB Attenuation, 20 MHz RF Bandwidth, 38.4 MSPS Sample Rate

20 0
+110°C +110°C
18 +40°C –10 +40°C
SNIFFER RECEIVER NOISE FIGURE (dB)

–40°C –40°C
SNIFFER RECEIVER IMAGE (dBc)

16 –20

14 –30

12 –40

10 –50

8 –60

6 –70

4 –80

2 –90

0 –100
14651-114

14651-117

3300 3400 3500 3600 3700 3800 0 5 10 15 20 25 30 35 40 45 50

SNIFFER RECEIVER LO FREQUENCY (MHz) SNIFFER RECEIVER ATTENUATION (dB)

Figure 114. Sniffer Receiver Noise Figure vs. Sniffer Receiver LO Frequency, Figure 117. Sniffer Receiver Image vs. Sniffer Receiver Attenuation,
0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 38.4 MSPS Sample Rate, 3500 MHz LO, Continuous Wave Signal 5 MHz Offset, 20 MHz RF Bandwidth,
10 MHz Integration Bandwidth 38.4 MSPS Sample Rate

Rev. PrA | Page 35 of 48

AD9371 Preliminary Technical Data
–40 0
+110°C +110°C
+40°C +40°C
SNIFFER RECEIVER DC OFFSET (dBFS)

–40°C –5 –40°C
–50

SNIFFER RECEIVER EVM (dB)

–10
–60
–15

–70 –20

–80 –25

–30
–90
–35
–100
–40

–110 –45

14651-121
14651-118
0 5 10 15 20 –70 –65 –60 –55 –50 –45 –40 –35 –30
SNIFFER RECEIVER ATTENUATION (dB) SNIFFER RECEIVER INPUT POWER (dBm)

Figure 118. Sniffer Receiver DC Offset vs. Sniffer Receiver Attenuation, Figure 121. Sniffer Receiver EVM vs. Sniffer Receiver Input Power,
3500 MHz LO, Continuous Wave Signal 1 MHz Offset, −35 dBm at 0 dB 3600 MHz LO, 20 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC,
Attenuation, Input Power Increasing dB for dB with Attenuation, BTC Active, 38.4 MSPS Sample Rate
20 MHz RF Bandwidth, 38.4 MSPS Sample Rate

0 35
+110°C +110°C
–10 +40°C +40°C
–40°C 25 –40°C
–20
SNIFFER RECEIVER GAIN (dB)
SNIFFER RECEIVER HD2 (dBc)

–30 15

–40
5
–50
–5
–60

–70 –15

–80
–25
–90

–100 –35

14651-122
14651-119

0 5 10 15 20 0 5 10 15 20 25 30 35 40 45 50 55
SNIFFER RECEIVER ATTENUATION (dB) SNIFFER RECEIVER ATTENUATION (dB)

Figure 119. Sniffer Receiver HD2 vs. Sniffer Receiver Attenuation, Figure 122. Sniffer Receiver Gain vs. Sniffer Receiver Attenuation,
3500 MHz LO, Continuous Wave Signal 1 MHz Offset, −35 dBm at 3600 MHz LO, Continuous Wave Signal 5 MHz Offset, 20 MHz RF
0 dB Attenuation, Input Power Increasing dB for dB with Attenuation, Bandwidth, De-Embedded to Receiver Port, 38.4 MSPS Sample Rate
20 MHz RF Bandwidth, 38.4 MSPS Sample Rate

0
+110°C
+40°C
–10 –40°C
–20
SNIFFER RECEIVER HD3 (dBc)

–30

–40

–50

–60

–70

–80

–90

–100
14651-120

0 5 10 15 20
SNIFFER RECEIVER ATTENUATION (dB)

Figure 120. Sniffer Receiver HD3 vs. Sniffer Receiver Attenuation, 3500 MHz LO,
Continuous Wave Signal 1 MHz Offset, −35 dBm at 0 dB Attenuation,
Input Power Increasing dB for dB with Attenuation,
20 MHz RF Bandwidth, 38.4 MSPS Sample Rate

Rev. PrA | Page 36 of 48

Preliminary Technical Data AD9371
5.5 GHz BAND
–30 100

+110°C 90
–40 +40°C
–40°C
RECEIVER LO LEAKAGE (dBm)

80

–50

RECEIVER IIP2 (dBm)

70

60
–60
50
–70
40 F2 + F1, +110°C
F2 + F1, +40°C
–80 30 F2 + F1, –40°C
F2 – F1, +110°C
20 F2 – F1, +40°C
–90 F2 – F1, –40°C
10

–100 0

14651-226
14651-223
5300 5400 5500 5600 5700 5800 5900 15 20 25 30 35 40 45
RECEIVER LO FREQUENCY (MHz) INTERMODULATION FREQUENCY (MHz)

Figure 123. Receiver LO Leakage vs. Receiver LO Frequency, 0 dB Receiver Figure 126. Receiver IIP2 vs. Intermodulation Frequency, 5600 MHz LO,
Attenuation, 100 MHz RF Bandwidth, 122.88 MSPS Sample Rate 0 dB Attenuation, 100 MHz RF Bandwidth, 122.88 MSPS Sample Rate

45 40

40 +110°C 35
+40°C
RECEIVER NOISE FIGURE (dB)

35 –40°C
30

RECEIVER IIP3 (dBm)

30
25
25
20
20
15
15
+110°C
10 +40°C
10 –40°C

5 5

0 0
14651-224

14651-227
0 3 6 9 12 15 15 20 25 30 35
RECEIVER ATTENUATION (dB) INTERMODULATION FREQUENCY (MHz)

Figure 124. Receiver Noise Figure vs. Receiver Attenuation, 5600 MHz LO, Figure 127. Receiver IIP3 vs. Intermodulation Frequency, 5600 MHz LO,
100 MHz Bandwidth, 122.88 MSPS Sample Rate, 50 MHz Integration 0 dB Attenuation, 100 MHz RF Bandwidth, 122.88 MSPS Sample Rate
Bandwidth (Includes 1.2 dB Matching Circuit Loss)

30 –40

25 –50 +110°C
+40°C
RECEIVER NOISE FIGURE (dB)

–40°C
RECEIVER IMAGE (dBc)

20 –60

15 –70

10 +110°C –80
+40°C
–40°C
5 –90

0 –100
14651-225

14651-228

5300 5400 5500 5600 5700 5800 5900 0 5 10 15 20 25 30

RECEIVER LO FREQUENCY (MHz) RECEIVER ATTENUATION (dB)

Figure 125. Receiver Noise Figure vs. Receiver LO Frequency, 0 dB Receiver Figure 128. Receiver Image vs. Receiver Attenuation, 5600 MHz LO,
Attenuation, 100 MHz RF Bandwidth, 122.88 MSPS Sample Rate, 50 MHz Continuous Wave Signal 10 MHz Offset, 100 MHz RF Bandwidth,
Integration Bandwidth (Includes Matching Circuit Loss) Background Tracking Calibration (BTC) Active, 122.88 MSPS Sample Rate

Rev. PrA | Page 37 of 48

AD9371 Preliminary Technical Data
20 –40

15 –50

10
–60
RECEIVER GAIN (dB)

RECEIVER HD3 (dBc)

5
–70
0
–80
–5
+110°C
–90 +40°C
–10 +110°C –40°C
+40°C
–40°C
–15 –100

–20 –110

14651-229

14651-232
0 5 10 15 20 25 30 0 5 10 15 20 25 30
RECEIVER ATTENUATION (dB) RECEIVER ATTENUATION (dB)

Figure 129. Receiver Gain vs. Receiver Attenuation, 5600 MHz LO, Continuous Figure 132. Receiver HD3 vs. Receiver Attenuation, 5600 MHz LO,
Wave Signal 10 MHz Offset, 100 MHz RF Bandwidth, 122.88 MSPS Sample Rate Continuous Wave Signal 10 MHz Offset, −20 dBm at 0 dB Attenuation,
Input Power Increasing dB for dB with Attenuation,100 MHz RF Bandwidth,
122.88 MSPS Sample Rate

–40 0

–5 +110°C
–50
+40°C
RECEIVER DC OFFSET (dBFS)

+110°C –10 –40°C

+40°C
–60 –40°C
RECEIVER EVM (dB)

–15

–70 –20

–80 –25

–30
–90
–35
–100
–40

–110 –45

14651-233
14651-230

0 5 10 15 20 25 30 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0
RECEIVER ATTENUATION (dB) RECEIVER INPUT POWER (dBm)

Figure 130. Receiver DC Offset vs. Receiver Attenuation, 5600 MHz LO, Figure 133. Receiver EVM vs. Receiver Input Power, 5600 MHz LO, 100 MHz RF
100 MHz RF Bandwidth, 122.88 MSPS Sample Rate Bandwidth LTE, 20 MHz Uplink Centered at DC, BTC Active, 122.88 MSPS
Sample Rate

–40 0

–10
–50
–20
Rx2 TO Rx1 CROSSTALK (dB)

+110°C
+40°C
–60 –40°C –30
RECEIVER HD2 (dBc)

–40
–70
–50
–80
–60

–90 –70

–80
–100
–90

–110 –100
14651-234
14651-231

0 5 10 15 20 25 30 5300 5400 5500 5600 5700 5800 5900

RECEIVER ATTENUATION (dB) RECEIVER LO FREQUENCY (MHz)

Figure 131. Receiver HD2 vs. Receiver Attenuation, 5600 MHz LO, Figure 134. Rx2 to Rx1 Crosstalk vs. Receiver LO Frequency,
Continuous Wave Signal 10 MHz Offset, −20 dBm at 0 dB Attenuation, 100 MHz RF Bandwidth, Continuous Wave Tone 3 MHz Offset from LO
Input Power Increasing dB for dB with Attenuation, 100 MHz RF Bandwidth,
122.88 MSPS Sample Rate

Rev. PrA | Page 38 of 48

Preliminary Technical Data AD9371
30 10

8
25
6
RECEIVER NOISE FIGURE (dB)

Tx OUTPUT (dBm)
20
2

15 0

–2
10 +110°C
+40°C –4 +110°C
–40°C +40°C
–40°C
–6
5
–8

0 –10

14651-238
14651-235
–40 –35 –30 –25 –20 –15 –10 –5 0 5300 5400 5500 5600 5700 5800 5900
INTERFERER SIGNAL POWER (dBm) RECEIVER LO FREQUENCY (MHz)

Figure 135. Receiver Noise Figure vs. Out-of-Band Interferer Signal Power, Figure 138. Tx Output Power, Transmitter QEC, and External LO Leakage
5400 MHz LO, 5600 MHz Continuous Wave Interferer, NF Integrated over Active, 5 MHz Continuous Wave Offset Signal, 1 MHz Resolution Bandwidth,
7 MHz to 10 MHz 245.76 MSPS Sample Rate

0 –40

–10 +110°C

TRANSMITTER LO LEAKAGE (dBFS)

+40°C –50
–20 –40°C
TRANSMITTER IMAGE (dBc)

–30
–60
–40

–50 –70

–60
+110°C
–80 +40°C
–70 –40°C
–80
–90
–90

–100 –100
14651-236

14651-239
0 5 10 15 20 0 5 10 15 20
RF ATTENUATION (dB) RF ATTENUATION (dB)

Figure 136. Transmitter Image vs. RF Attenuation, 75 MHz RF Bandwidth, Figure 139. Transmitter LO Leakage vs. RF Attenuation, 5600 MHz LO,
5600 MHz LO, 0 dB RF Attenuation, Transmitter QEC Tracking Run with External Transmitter QEC, and LO Leakage Tracking Active, Continuous
Two 20 MHz LTE Downlink Carriers, Then Image Measured with Wave Signal 10 MHz Offset from LO, 6 dB Digital Backoff, 1MHz
Continuous Wave 10 MHz Offset from LO, 3 dB Digital Backoff, Measurement Bandwidth
245.76 MSPS Sample Rate

0 –60

–10 +110°C –65

TRANSMITTER LO LEAKAGE (dBFS)

+40°C
–20 –40°C
TRANSMITTER IMAGE (dBc)

–70
–30
–75
–40

–50 –80

–60
–85 5.9GHz, +110°C 5.3GHz, +110°C
–70 5.9GHz, +40°C 5.3GHz, +40°C
–90 5.9GHz, –40°C 5.3GHz, –40°C
–80 5.6GHz, +110°C
5.6GHz, +40°C
–95 5.6GHz, –40°C
–90

–100 –100
14651-240
14651-237

–40 –30 –20 –10 0 10 20 30 40 –40 –30 –20 –10 0 10 20 30 40

DESIRED OFFSET FREQUENCY (MHz) OFFSET FREQUENCY (MHz)

Figure 137. Transmitter Image vs. Desired Offset Frequency, 75 MHz RF Figure 140. Transmitter LO Leakage vs. Offset Frequency,
Bandwidth, 5600 MHz LO, 0 dB RF Attenuation, Transmitter QEC Tracking External Transmitter QEC and LO Leakage Tracking Active,
Run with Two 20 MHz LTE Downlink Carriers, Then Image Measured with 6 dB Digital Backoff, 1 MHz Measurement Bandwidth
Continuous Wave Signal, 3 dB Digital Backoff, 245.76 MSPS Sample Rate

Rev. PrA | Page 39 of 48

AD9371 Preliminary Technical Data
0 –80

–10 –90 +110°C

+40°C
–40°C

TRANSMITTER NOISE (dBm/Hz)

–20 –100
Tx1 TO Rx1 CROSSTALK (dB)

–30 –110

–40 –120

–50 –130

–60 –140

–70 –150

–80 –160

–90 –170

–100 –180

14651-241

14651-244
5300 5400 5500 5600 5700 5800 5900 0 5 10 15 20
RECEIVER LO FREQUENCY (MHz) RF ATTENUATION (dB)

Figure 141. Tx1 to Rx1 Crosstalk vs. Receiver LO Frequency, 100 MHz Receiver Figure 144. Transmitter Noise vs. RF Attenuation, 5600 MHz LO,
RF Bandwidth, 75 MHz Transmitter RF Bandwidth, 1 MHz Offset Frequency
Continuous Wave Signal 3 MHz Offset from LO

0 –40

–10

Tx ADJACENT CH LEAKAGE RATIO (dB)

–45
–20
Tx2 TO Rx2 CROSSTALK (dB)

–50
–30
–55
–40

–50 –60

–60
–65 +110°C LOWER
+40°C LOWER
–70
–40°C LOWER
–70
+110°C UPPER
–80
+40°C UPPER
–75 –40°C UPPER
–90

–100 –80
14651-242

14651-245
5300 5400 5500 5600 5700 5800 5900 0 5 10 15 20
RECEIVER LO FREQUENCY (MHz) RF ATTENUATION (dB)

Figure 142. Tx2 to Rx2 Crosstalk vs. Receiver LO Frequency, 100 MHz Receiver Figure 145. Tx Adjacent Channel Leakage Ratio vs. RF Attenuation,
RF Bandwidth, 75 MHz Transmitter RF Bandwidth, 5600 MHz LO, 75 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal,
Continuous Wave Signal 3 MHz Offset from LO Transmitter QEC and LO Leakage Tracking Active

–10 –40
Tx ALTERNATE CH LEAKAGE RATIO (dB)

–20
–45
–30
Tx2 TO Tx1 CROSSTALK (dB)

–50
–40
–55
–50

–60 –60

–70
–65 +110°C LOWER
+40°C LOWER
–80
–40°C LOWER
–70
+110°C UPPER
–90
+40°C UPPER
–75 –40°C UPPER
–100

–110 –80
14651-243

14651-246

5300 5400 5500 5600 5700 5800 5900 0 5 10 15 20

TRANSMITTER LO FREQUENCY (MHz) RF ATTENUATION (dB)

Figure 143. Tx2 to Tx1 Crosstalk vs. Transmitter LO Frequency, Figure 146. Tx Alternate Channel Leakage Ratio vs. RF Attenuation,
75 MHz RF Bandwidth, Continuous Wave Signal 3 MHz Offset from LO 5600 MHz LO, 75 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal,
2 dB Digital Backoff, Transmitter QEC and LO Leakage Tracking Active

Rev. PrA | Page 40 of 48

Preliminary Technical Data AD9371
–60 0

–70 –10

–20
–80
LO PHASE NOISE (dBc)

–30

Tx OUTPUT (dBm)
–90
–40
–100
–50
–110
–60
–120
–70
–130
–80

–140 –90

–150 –100

14651-247

14651-250
100 1k 10k 100k 1M 10M 5750 5775 5800 5825 5850 5875 5900 5925 5950
OFFSET FREQUENCY (Hz) FREQUENCY (MHz)

Figure 147. LO Phase Noise vs. Offset Frequency, 3 dB Digital Backoff, Figure 150. Transmitter Spectrum, 3 dB Digital and 1 dB RF Backoff,
5850 MHz LO 40 MHz RF Bandwidth, Transmitter QEC, and Internal LO Leakage Active,
LTE 10 MHz Signal, 5850 MHz LO, 1 MHz Resolution Bandwidth, 122.88 MSPS
Sample Rate, Test Equipment Noise Floor De-Embedded

1.0 0
Tx INTEGRATED PHASE NOISE (Degrees)

0.9 –10

0.8 –20

0.7 Tx OUTPUT (dBm) –30

0.6 –40

0.5 –50

0.4 –60

0.3 +110°C –70

+40°C
–40°C
0.2 –80

0.1 –90

0 –100
14651-248

14651-251
5300 5400 5500 5600 5700 5800 5900 5350 5450 5550 5650 5750 5850 5950 6050 6150 6250 6350
TRANSMITTER LO FREQUENCY (MHz) FREQUENCY (MHz)

Figure 148. Tx Integrated Phase Noise vs. Transmitter LO Frequency, Figure 151. Transmitter Spectrum, 3 dB Digital and 1 dB RF Backoff,
75 MHz RF Bandwidth, Continuous Wave 10 MHz Offset from LO, 40 MHz RF Bandwidth, Transmitter QEC, and Internal LO Leakage Active,
3 dB Digital Backoff LTE 10 MHz Signal, 5850 MHz LO, 1 MHz Resolution Bandwidth,
122.88 MSPS Sample Rate, Test Equipment Noise Floor De-Embedded

30 –20

25 +110°C –25
+40°C
TRANSMITTER OIP3 (dBm)

–40°C
TRANSMITTER EVM (dB)

+110°C
+40°C
20 –30 –40°C

15 –35

10 –40

5 –45

0 –50
14651-249

14651-252

0 5 10 15 20 0 5 10 15 20
RF ATTENUATION (dB) RF ATTENUATION (dB)

Figure 149. Transmitter OIP3 vs. RF Attenuation, 5600 MHz LO, Figure 152. Transmitter EVM vs. RF Attenuation, 5600 MHz LO, Transmitter
75 MHz RF Bandwidth, F1 = 20 MHz, F2 = 21 MHz, 3 dB Digital Backoff, LO Leakage, and Transmitter QEC Tracking Active, 75 MHz RF Bandwidth,
245.76 MSPS Sample Rate LTE 20 MHz Downlink Signal, 245.76 MSPS Sample Rate

Rev. PrA | Page 41 of 48

AD9371 Preliminary Technical Data
0 0.10

–10 +110°C 0.08 +110°C

Tx ATTENUATION STEP ERROR (dB)

+40°C +40°C
–20 –40°C 0.06 –40°C
TRANSMITTER HD2 (dBc)

–30 0.04

–40 0.02

–50 0

–60 –0.02

–70 –0.04

–80 –0.06

–90 –0.08

–100 –0.10

14651-256
14651-253
0 5 10 15 20 0 5 10 15 20
RF ATTENUATION (dB) RF ATTENUATION (dB)

Figure 153. Transmitter HD2 vs. RF Attenuation, 5850 MHz LO, Figure 156. Tx Attenuation Step Error vs. RF Attenuation, 5850 MHz LO,
5855 MHz Continuous Wave Desired Signal, 75 MHz RF Bandwidth, 5855 MHz Continuous Wave Desired Signal, 75 MHz RF Bandwidth,
245.76 MSPS Sample Rate 245.76 MSPS Sample Rate

0 0.5

0.4
–10 +110°C

DEVIATION FROM FLATNESS (dB)

+40°C 0.3
–40°C
–20
TRANSMITTER HD3 (dBc)

0.2
–30
0.1

–40 0

–0.1
–50
–0.2
–60
–0.3
–70
–0.4

–80 –0.5

14651-257
14651-254

0 5 10 15 20 –100 –80 –60 –40 –20 0 20 40 60 80 100

RF ATTENUATION (dB) FREQUENCY OFFSET FROM LO (MHz)

Figure 154. Transmitter HD3 vs. RF Attenuation, 5850 MHz LO, Figure 157. Transmitter Frequency Response Deviation from Flatness vs.
5855 MHz Continuous Wave Desired Signal, 75 MHz RF Bandwidth, Frequency Offset from LO, 5850 MHz LO, 200 MHz Synthesis Bandwidth,
245.76 MSPS Sample Rate 6 dB Digital Backoff, 245.76 MSPS Sample Rate

10 –40
OBSERVATION RECEIVER LO LEAKAGE (dBm)
TRANSMITTER OUTPUT POWER (dBm)

+110°C –45
5 +40°C
–40°C +110°C
–50 +40°C
–40°C
0
–55

–5 –60

–65
–10
–70
–15
–75

–20 –80
14651-258
14651-255

0 5 10 15 20 25 5300 5400 5500 5600 5700 5800 5900

RF ATTENUATION (dB) OBSERVATION RECEIVER LO FREQUENCY (MHz)

Figure 155. Transmitter Output Power vs. RF Attenuation, 5850 MHz LO, Figure 158. Observation Receiver LO Leakage vs. Observation Receiver
5855 MHz Continuous Wave Desired Signal, 75 MHz RF Bandwidth, LO Frequency, 0 dB Receiver Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate 245.76 MSPS Sample Rate

Rev. PrA | Page 42 of 48

Preliminary Technical Data AD9371
30 0
OBSERVATION RECEIVER NOISE FIGURE (dB)

–10 +110°C

OBSERVATION RECEIVER IMAGE (dBc)

25 +40°C
–20 –40°C

–30
20
–40

15 –50

–60
+110°C
10 +40°C
–40°C –70

–80
5
–90

0 –100

14651-259

14651-262
5300 5400 5500 5600 5700 5800 5900 0 3 6 9 12 15 18
OBSERVATION RECEIVER LO FREQUENCY (MHz) OBSERVATION RECEIVER ATTENUATION (dB)

Figure 159. Observation Receiver Noise Figure vs. Observation Receiver Figure 162. Observation Receiver Image vs. Observation Receiver
LO Frequency, 0 dB Receiver Attenuation, 200 MHz RF Bandwidth, Attenuation, 5600 MHz LO, Continuous Wave Signal 30 MHz Offset,
245.76 MSPS Sample Rate, 100 MHz Integration Bandwidth 200 MHz RF Bandwidth, Background Tracking Calibration (BTC) Active,
245.76 MSPS Sample Rate

80 25

70 20

OBSERVATION RECEIVER GAIN (dBc)

+110°C
OBSERVATION RECEIVER IIP2 (dBm)

+40°C
–40°C
60 15

50 10

40 5

30 0

+110°C
20 +40°C –5
–40°C
10 –10

0 –15
14651-260

14651-263
10 20 30 40 50 60 70 80 90 100 110 0 3 6 9 12 15 18
INTERMODULATION FREQUENCY (MHz) OBSERVATION RECEIVER ATTENUATION (dB)

Figure 160. Observation Receiver IIP2 vs. Intermodulation Frequency, Figure 163. Observation Receiver Gain vs. Observation Receiver Attenuation,
5600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth, 5600 MHz LO, Continuous Wave Signal 30 MHz Offset,
245.76 MSPS Sample Rate 200 MHz RF Bandwidth, 245.76 MSPS Sample Rate

40 –40
OBSERVATION RECEIVER DC OFFSET (dBFS)

35
OBSERVATION RECEIVER IIP3 (dBm)

–50 +110°C
+40°C
–40°C
30
–60

25
–70
20
–80
15
+110°C –90
10 +40°C
–40°C

5 –100

0 –110
14651-261

14651-264

5 15 25 35 45 55 65 75 85 95 105 115 0 3 6 9 12 15 18
INTERMODULATION FREQUENCY (MHz) OBSERVATION RECEIVER ATTENUATION (dB)

Figure 161. Observation Receiver IIP3 vs. Intermodulation Frequency, Figure 164. Observation Receiver DC Offset vs. Observation Receiver
5600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth, 245.76 MSPS Attenuation, 5600 MHz LO, Continuous Wave Signal 30 MHz Offset,
Sample Rate −15 dBm Input, 200 MHz RF Bandwidth, 245.76 MSPS Sample Rate

Rev. PrA | Page 43 of 48

AD9371 Preliminary Technical Data
0 0

–10
OBSERVATION RECEIVER HD2 (dBc)

OBSERVATION RECEIVER HD3 (dBc)

+110°C –20 +110°C
–20 +40°C +40°C
–40°C –40°C
–30
–40
–40

–50 –60

–60
–80
–70

–80
–100
–90

–100 –120

14651-265

14651-266
0 3 6 9 12 15 18 0 3 6 9 12 15 18
OBSERVATION RECEIVER ATTENUATION (dB) OBSERVATION RECEIVER ATTENUATION (dB)

Figure 165. Observation Receiver HD2 vs. Observation Receiver Attenuation, Figure 166. Observation Receiver HD3 vs. Observation Receiver Attenuation,
5600 MHz LO, Continuous Wave Signal 30 MHz Offset, −15 dBm Input, 5600 MHz LO, Continuous Wave Signal 30 MHz Offset, −15 dBm Input,
Input Power Increasing dB for dB with Attenuation, 200 MHz RF Bandwidth, Input Power Increasing dB for dB with Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate 245.76 MSPS Sample Rate

Rev. PrA | Page 44 of 48

Preliminary Technical Data AD9371

THEORY OF OPERATION
The AD9371 is a highly integrated RF transceiver capable of RECEIVER (Rx)
being configured for a wide range of applications. The device The AD9371 contains dual receiver channels. Each Rx channel
integrates all the RF, mixed signal, and digital blocks necessary is a direct conversion system that contains a programmable
to provide transmit and receive functions in a single device. attenuator stage, followed by matched I and Q mixers that down
Programmability allows the two receiver channels and two convert received signals to baseband for digitization.
transmitter channels to be used in TDD and FDD systems for
3G and 4G cellular standards. To achieve gain control, a programmed gain index map is
implemented. This gain map distributes attenuation among the
The observation receiver channel has two inputs for use in various Rx blocks for optimal performance at each power level.
monitoring the transmitter outputs. This channel has a wide In addition, support is available for both automatic and manual
channel bandwidth that receives the entire transmit band and gain control modes.
feeds it back to the digital section for error correction purposes.
In addition, three sniffer receiver inputs can monitor different The receiver includes Σ-Δ ADCs and adjustable sample rates
radio frequency bands (one at a time). These channels share the that produce data streams from the received signals. The signals
baseband ADC and digital processing with the two ORx inputs. can be conditioned further by a series of decimation filters and
a fully programmable 72-tap FIR filter with additional decimation
The AD9371 contains four high speed serial interface links for settings. The sample rate of each digital filter block is adjustable
the transmit chain and four high speed serial interface links by changing the decimation factors to produce the desired
shared by the Rx, ORx, and SnRx channels (JESD204B, output data rate.
Subclass 1 compliant), providing a low pin count and reliable
data interface to a field-programmable gate array (FPGA) or OBSERVATION RECEIVER (ORx)
other custom integrated baseband solutions. The ORx operates in a similar manner to the main receivers.
The AD9371 also provides self calibration for dc offset and Each input is differential and uses a dedicated mixer. The ORx
quadrature error correction to maintain a high performance inputs share a baseband ADC and baseband section; therefore,
level under varying temperatures and input signal conditions. only one can be active at any time. The mixed signal and digital
The device includes test modes that allow system designers to section is identical in design and operation to the main receiver
debug designs during prototyping and optimize radio channels. This channel can monitor the Tx channels and
configurations. implement error correction functions. It can also be used as a
general-purpose receiver.
TRANSMITTER (Tx)
SNIFFER RECEIVER (SnRx)
The AD9371 employs a direct conversion transmitter
architecture consisting of two identical and independently The sniffer receiver provides three differential inputs that can
controlled channels that provide all the digital processing, monitor different frequency bands. Each input has a low noise
mixed signal, and RF blocks necessary to implement a direct amplifier (LNA) that is multiplexed to feed a single mixer. The
conversion system. Both channels share a common frequency output of this mixer stage is multiplexed with the ORx receiver
synthesizer. mixers to feed the same baseband section. The SnRx bandwidth
is limited to 20 MHz. This receiver can also be used as a general-
The digital data from the JESD204B lanes pass through a fully
purpose receiver if the bandwidth and RF performance are
programmable 96-tap FIR filter with optional interpolation.
acceptable for a given application.
The FIR output is sent to a series of conversion filters that
provide additional filtering and data rate interpolation prior to CLOCK INPUT
reaching the DAC. Each DAC has an adjustable sample rate and The AD9371 requires a differential clock connected to the
is linear up to full scale. DEV_CLK_IN+/DEV_CLK_IN− pins. The frequency of the
Once converted to baseband analog signals, the in-phase (I) and clock input must be between 10 MHz and 320 MHz, and it must
quadrature (Q) signals are filtered to remove sampling artifacts, have very low phase noise because this signal generates the RF
and then the signals are fed to the upconversion mixers. At the local oscillator and internal sampling clocks.
mixer stage, the I and Q signals are recombined and modulated
onto the carrier frequency for transmission to the output stage.
Each transmit chain provides a wide attenuation adjustment
range with fine granularity to help designers optimize SNR.

Rev. PrA | Page 45 of 48

AD9371 Preliminary Technical Data
SYNTHESIZERS AUXILIARY CONVERTERS
RF PLL Auxiliary ADCs (AUXADC_x)
The AD9371 contains three fractional-N PLLs to generate the The AD9371 contains an auxiliary ADC that is multiplexed to four
RF LOs used by the transmitter, receiver, and observation input pins (AUXADC_0 through AUXADC_3). This block can
receiver. The PLL incorporates an internal VCO and loop filter monitor system voltages without adding additional components.
that require no external components. The internal VCO LDO The auxiliary ADC is 12 bits with an input voltage range of 0.05 V
regulators eliminate the need for additional external power to VDDA_3P3 − 0.05 V. When enabled, the auxiliary ADC is
supplies for the PLLs. These regulators only require an external free running. Software reads of the output value provide the last
bypass capacitor for each supply. value latched at the ADC output.
Clock PLL Auxiliary DACs (AUXDAC_x)
The AD9371 contains a PLL synthesizer that generates all of the The AD9371 contains ten identical auxiliary DACs (AUXDAC_0
baseband related clock signals and SERDES clocks. This PLL is to AUXDAC_9) that can supply bias voltages, analog control
programmed based on the data rate and sample rate requirements voltages, or other system functionality. The inputs of these
of the system. AUXDAC_xs are multiplexed with GPIO_3P3_x pins according
to Table 7. The auxiliary DACs are 10 bits and have an output
SERIAL PERIPHERAL INTERFACE (SPI) INTERFACE
voltage range of approximately 0.5 V to VDDA_3P3 − 0.05 V
The AD9371 uses a SPI to communicate with the baseband and have a current drive of 10 mA.
processor (BBP). This interface can be configured as a 4-wire
interface with dedicated receive and transmit ports, or it can be Table 7. AUXDAC Input Pin Assignments
configured as a 3-wire interface with a bidirectional data GPIO_3P3 Pin AUXDAC Output
communications port. This bus allows the BBP to set all device GPIO_3P3_9 AUXDAC_0
control parameters using a simple address data serial bus protocol. GPIO_3P3_7 AUXDAC_1
Write commands follow a 24-bit format. The first bit sets the GPIO_3P3_6 AUXDAC_2
bus direction of the bus transfer. The next 15 bits set the address GPIO_3P3_10 AUXDAC_3
where data is written. The final eight bits are the data being GPIO_3P3_0 AUXDAC_4
transferred to the specific register address. GPIO_3P3_1 AUXDAC_5
GPIO_3P3_3 AUXDAC_6
Read commands follow a similar format with the exception that
GPIO_3P3_4 AUXDAC_7
the first 16 bits are transferred on the SDIO, and the final 8 bits
GPIO_3P3_5 AUXDAC_8
are read from the AD9371, either on the SDO pin in 4-wire
GPIO_3P3_8 AUXDAC_9
mode or on the SDIO pin in 3-wire mode.
GPIO_x AND GPIO_3P3_x PINS JESD204B DATA INTERFACE
The AD9371 general-purpose input/output signals referenced The digital data interface for the AD9371 uses JEDEC Standard
to the VDD_IF supply can be configured for numerous functions. JESD204B Subclass 1. The serial interface operates at speeds up
Some of these pins, when configured as outputs, are used by the to 6144 Mbps. The benefits of the JESD204B interface include a
BBP as real-time signals to provide a number of internal settings reduction in required board area for data interface routing and
and measurements. This configuration allows the BBP to smaller package options due to the need for fewer pins. Digital
monitor receiver performance in different situations. A pointer filtering is included in all receiver and transmitter paths to
register selects what information is output to these pins. Signals provide proper signal conditioning and sampling rates to meet
used for manual gain mode, calibration flags, state machine the JESD data requirements. Examples of the digital filtering
states, and various receiver parameters are among the outputs configurations for the Tx and Rx paths are shown in Figure 167
that can be monitored on these pins. In addition, certain pins and Figure 168, respectively.
can be configured as inputs and used in various functions such
as setting the receiver gain in real time.
The GPIO_3P3_x pins referenced to the VDDA_3P3 supply are
also included in the device and can provide control signals to
the external components such as VGAs or attenuators in the RF
section that typically use a higher reference voltage.

Rev. PrA | Page 46 of 48

Preliminary Technical Data AD9371
Table 8. Example Rx/Tx Interface Rates (2 Rx/2 Tx Channels, Maximum JESD Lane Rates)
Tx/Tx Synthesis/ Tx Input Rx Output JESD Lane Rate JESD204B (No.
Rx Bandwidth (MHz) Rate (MSPS) Rate (MSPS) (Mbps), 2 Tx/2 Rx of Lanes) Tx/Rx Reference Clock Options (MHz)
100/250/100 307.2 153.6 6144 4/2 122.88, 153.6, 245.76, 307.2
75/200/100 245.76 122.88 4915.2 4/2 122.88, 245.76
20/100/40 122.88 61.44 2457.6 4/2 122.88, 245.76
20/100/20 122.88 30.72 2457.6 4/1 122.88, 245.76

TRANSMITTER TRANSMITTER QUADRATURE DIGITAL

HALF-BAND TRANSMITTER FIR ERROR
HALF-BAND GAIN

14651-125
FILTER 2 (INTERPOLATION CORRECTION
FILTER 1 1, 2, 4)

Figure 167. Example Tx Data Path Filter Implementation

DEC5

RECEIVER RECEIVER RECEIVER RFIR QEC DIGITAL DC REAL

ADC HALF-BAND HALF-BAND HALF-BAND (DECIMATION CORRECTION GAIN CORRECTION IF JESD204B
FILTER 3 FILTER 2 FILTER 1

14651-126
1, 2, 4) FILTER

Figure 168. Data Rx Data Path Filter Implementation

POWER SUPPLY SEQUENCE Table 9. Dual Function Boundary Scan Test Pins
The AD9371 requires a specific power-up sequence to avoid Mnemonic JTAG Mnemonic Description
undesired power-up currents. The optimal power-on sequence GPIO_4 TRST Test access port reset
starts the process by powering up the VDIG and the GPIO_5 TDO Test data output
VDDA_1P3 (analog) supplies simultaneously. If they cannot GPIO_6 TDI Test data input
power up simultaneously, the VDIG supply must power up first. GPIO_7 TMS Test access port mode select
The VDDA_3P3, VDDA_1P8, and JESD_VTT_DES supplies GPIO_18 TCK Test clock
must then power up after the VDIG and VDDA_1P3 supplies.
Note that the VDD_IF supply can power up at any time. It is Table 10. JTAG Modes
also recommended to toggle the RESET signal after power has Test Pin Level GPIO_0 to GPIO_3 Description
stabilized prior to configuration. Follow the reverse order of 0 XXXX1 Normal operation
the power-up sequence to power-down. 1 1001 JTAG mode with LVDS
JESD SYNC signals
JTAG BOUNDARY SCAN 1 1011 JTAG mode with CMOS
The AD9371 provides support for a JTAG boundary scan. JESD SYNC signals
There are five dual function pins associated with the JTAG 1
X stands for don’t care.
interface. These pins, listed in Table 9, are used to access the on-
chip test access port. To enable the JTAG functionality, set the
GPIO_0 through GPIO_3 pins according to Table 10 depending
on how the desired JESD sync pin (that is, SYNCINB0+,
SYNCINB0−, SYNCINB1+, SYNCINB1−, SYNCBOUTB0+,
or SYNCBOUTB0−) is configured in the software (LVDS or
CMOS mode). Pull the TEST pin high to enable the JTAG mode.

Rev. PrA | Page 47 of 48

AD9371 Preliminary Technical Data

OUTLINE DIMENSIONS

12.10
12.00 SQ A1 BALL
A1 BALL 11.90 PAD CORNER
CORNER 14 13 12 11 10 9 8 7 6 5 4 3 2 1

A
B
C
D
E
PIN A1
INDICATOR 10.40 SQ F
7.755 REF G
H
J
0.80 K
L
M
N
P
TOP VIEW BOTTOM VIEW
0.80 REF
8.165 REF

DETAIL A
1.27 0.91
1.18 0.84
1.09 DETAIL A 0.77
0.39
0.34
0.29
0.44 REF

SEATING 0.50 COPLANARITY

PLANE 0.45 0.12
0.40
BALL DIAMETER

03-02-2015-A
PKG-004569

COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1.

Figure 169. 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-196-12)
Dimensions shown in millimeters

©2016 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D14651-0-5/16(PrA)

Rev. PrA | Page 48 of 48