SYN500R Datasheet

(300‐450MHz ASK Receiver)

Version 1.1
 Contents

1. General Description ................................................................................................................1

2. Features....................................................................................................................................1
3. Applications .............................................................................................................................1
4. Typical Application .................................................................................................................2
5. Pin Configuration....................................................................................................................2
6. Pin Description ........................................................................................................................3
7. Absolute Maximum Ratings (Note 1) ....................................................................................4
8. Operating Ratings (Note 2) ....................................................................................................4
9. Electrical Characteristics (Note 4).........................................................................................4
10. Typical Characteristics ...........................................................................................................7
10.1. Sensitivity Graphs ..................................................................................................... 7
11. Functional Diagram ................................................................................................................8
12. Functional Description............................................................................................................8
13. Receiver Operation .................................................................................................................8
13.1. LNA .......................................................................................................................... 8
13.2. Mixers and Synthesizer ............................................................................................. 8
13.3. Image Reject Filter and Band-Pass Filter .................................................................. 9
13.4. OOK Demodulator .................................................................................................... 9
13.5. Detector and Programmable Low-Pass Filter ........................................................... 9
13.6. Slicer, Slicing Level ................................................................................................ 10
13.7. AGC Comparator .................................................................................................... 10
13.8. Reference Control ................................................................................................... 10
13.9. Reference Oscillator ................................................................................................ 10
14. Applications Information ..................................................................................................... 11
15. Package Information.............................................................................................................18
 SYN500R

1. General Description
The SYN500R is a general purpose, 3V-5.5V ASK Receiver that operates at 300-450MHz with
typical sensitivity of -109dBm.

The SYN500R functions as a super-heterodyne receiver for OOK and ASK modulation up to
10kbps. The down-conversion mixer also provides image rejection. All post-detection data
filtering is provided on the SYN500R. Any one-of-four filter bandwidths may be selected
externally by the user in binary steps, from 1.25KHz to 10KHz. The user need only configure
the device with a set of easily determined values, based upon data rate, code modulation format,
and desired duty-cycle operation.

2. Features
l –109 dBm sensitivity, 1kbps and BER 10E-02
l Frequency from 300MHz to 450MHz
l Supply Voltage from 3V to 5.5V
l Image Rejection Mixer Data-rate up to 10kbps (fixed-mode)
l Low power, 6.0mA, 3.3V @ 433.92MHz, 3.9mA, 3.3V @315MHz, continuous on data rates
to 10kbps (Manchester Encoded)
l Analog RSSI Output
l No IF filter required
l Excellent selectivity and noise rejection

3. Applications
l Automotive Remote Keyless Entry (RKE)
l Remote controls
l Remote fan and light control
l Garage door and gate openers

*This specification is subject to change without notification. -1-

 SYN500R

4. Typical Application

433.92MHz 1K Baud Rate Example

C3 L2 C8 L1

1.5P 39NH 6.2P 22NH 433.92MHz

2P 47NH 6.2P 39NH 315MHz

5.
Pin Configuration

SYN500R SSOP16

*This specification is subject to change without notification. -2-

 SYN500R

6. Pin Description

SSOP16 Pin Name Pin Function

Reference resonator input connection to Colpitts oscillator stage. May

1 RO1 also be driven by external reference signal of 1.5V p-p amplitude
maximum.
2 GNDRF Negative supply connection associated with ANT RF input.
RF signal input from antenna. Internally AC coupled. It is
3 ANT recommended that a matching network with an inductor -to-RF ground
is used to improve ESD protection.
4 GNDRF Negative supply connection associated with ANT RF input.
5 VDD Positive supply connection for all chip functions.
Not Connected (Floating)
6 NC

Logic control input with active internal pull-up. Used in conjunction

7 SEL0 with SEL1 to control the demodulator low pass filter bandwidth. (See
filter table for SEL0 and SEL1 in application section)
8 SHDN Shutdown logic control input. Active internal pull-up.
9 GND Negative supply connection for all chip functions except RF input.

10 DO Demodulated data output.

Logic control input with active internal pull-up. Used in conjunction

11 SEL1 with SEL0 to control the demodulator low pass filter bandwidth. (See
filter table for SEL0 and SEL1 in application section)
Demodulation threshold voltage integration capacitor connection. Tie
an external capacitor across CTH pin and GND to set the settling time
12 CTH
for the demodulation data slicing level. Values above 1nF are
recommended and should be optimized for data rate and data profile.
AGC filter capacitor connection. CAGC capacitor, normally greater
13 CAGC
than 0.47µF, is connected from this pin to GND

Received signal strength indication output. Output is from a buffer

14 RSSI
with 200Ω typical output impedance.
15 NC Not Connected (Connect to Ground)
Reference resonator input connection to Colpitts oscillator stage, 7pF,
in parallel with low resistance MOS switch-to-GND, during normal
16 RO2
operation. Driven by startup excitation circuit during the internal
startup control sequence.

*This specification is subject to change without notification. -3-

 SYN500R

7. Absolute Maximum Ratings (Note 1)

Supply Voltage (VDD) +7V

Input Voltage +7V
Junction Temperature (TJ) +150°C
Storage Temperature Range (TS) –65°C to +150°C
Lead Temperature (soldering, 10 sec.) +260°C
Maximum Receiver Input Power +10dBm
ESD Rating Note 3

8. Operating Ratings (Note 2)

RF Frequency Range 300MHz to 450MHz

Supply Voltage (VDD) +3.0V to +5.5V
Input Voltage (VIN). 5.5V (Max)
Maximum Input RF Power –20dBm
Ambient Temperature (TA) –30°C to +85°C

9. Electrical Characteristics (Note 4)

Specifications apply for 3.0V < VDD < 5.5V, VSS = 0V, CAGC = 4.7µF, CTH = 0.1µF, fRX = 433.92
MHz, unless otherwise noted. Bold values indicate –40°C – TA – 105°C. 1kbps data rate
(Manchester encoded), reference oscillator frequency = 13.52127MHz.

Symbol Parameter Condition Min Typ Max Units

VDD=3.3V, fRX = 433.92MHz 6.0 mA

VDD=5V, fRX = 433.92MHz 7.0 mA

ISS Operating Supply Current
VDD=3.3V, fRX =315MHz 3.9 mA

VDD=5V, fRX = 315MHz 4.7 mA

ISHUT Shut down Current 0.5 µA

RF Section, IF Section
Image Rejection 20 dB

fRX = 433.92MHz 1.2 MHz

1st IF Center Frequency
fRX = 315MHz 0.86 MHz

*This specification is subject to change without notification. -4-

 SYN500R

fRX = 433.92MHz , VDD=5V

-109 dBm
(matched to 50 Ω) BER=10-2
Receiver Sensitivity @ 1kbps
fRX = 315MHz , VDD=5V
-109 dBm
(matched to 50 Ω) BER=10-2

fRX = 433.92MHz 330 kHz

IF Bandwidth
fRX = 315MHz 235 kHz

19 –
fRX = 433.92MHz Ω
j174
Antenna Input Impedance
32.5 –
fRX = 315MHz Ω
j235

Receive Modulation Duty Cycle Note 5 20 80 %

AGC Attack / Decay Ratio tATTACK / tDECAY 0.1

TA = 25ºC ±2 nA
AGC pin leakage current
TA = +105ºC ± 800 nA

RFIN @ -40dBm 1.15 V

AGC Dynamic Range
RFIN @ -100dBm 1.70 V

Reference Oscillator
fRX = 433.92 MHz
13.52127 MHz
Crystal Load Cap = 10pF
Reference Oscillator Frequency
fRX = 315 MHz
9.81563 MHz
Crystal Load Cap = 10pF

Reference Oscillator Input Impedance 300 kΩ

Reference Oscillator Input Range 0.2 1.5 Vp-p

Reference Oscillator Source Current V(REFOSC) = 0V 3.5 µA

Demodulator
CTH Source Impedance FREFOSC = 13.52127MHz 120 kΩ

FREFOSC = 9.81563MHz 165 kΩ

TA = 25ºC ±2 nA
CTH Leakage Current
TA = +105ºC ± 800 nA

Programmable, see 1625 13000 Hz

Demodulator Filter Bandwidth @ 434MHz
application section

*This specification is subject to change without notification. -5-

 SYN500R

Digital/Control Section
DO pin output current As output source @ 0.8 Vdd 260 µA

sink @ 0.2 Vdd 600

Output rise and fall times CI = 15pF, pin DO, 10-90% 2 µsec

RSSI
RSSI DC Output Voltage Range 0.4 to 2 V

RSSI response slope -109dBm to -40dBm 25 mV/dB

RSSI Output Current 400 µA

RSSI Output Impedance 200 Ω

RSSI Response Time 50% data duty cycle, input 0.3 sec
power to Antenna = -20dBm

Note 1: Exceeding the absolute maximum rating may damage the device.
Note 2: The device is not guaranteed to function outside of its operating rating.
Note 3: Device is ESD sensitive. Use appropriate ESD precautions. Exceeding the absolute
maximum rating may damage the device.
Note 4: Sensitivity is defined as the average signal level measured at the input necessary to
achieve 10-2 BER (bit error rate). The input signal is defined as a return-to-zero (RZ)
waveform with 50% average duty cycle (Manchester encoded) at a data rate of 1kbps.
Note 5: When data burst does not contain preamble, duty cycle is defined as total duty cycle,
including any “quiet” time between data bursts. When data bursts contain preamble
sufficient to charge the slice level on capacitor CTH, then duty cycle is the effective duty
cycle of the burst alone. [For example, 100msec burst with 50% duty cycle, and
100msec “quiet” time between bursts. If burst includes preamble, duty cycle is
TON/(TON+tOFF)= 50%; without preamble, duty cycle is TON/(TON+TOFF+TQUIET) =
50msec/(200msec)=25%. TON is the (Average number of 1’s/burst) × bit time, and
TOFF=TBURST–TON.)

*This specification is subject to change without notification. -6-

 SYN500R

10. Typical Characteristics

10.1. Sensitivity Graphs

*This specification is subject to change without notification. -7-

 SYN500R

11. Functional Diagram

Figure 1. Simplified Block Diagram

12. Functional Description

Figure 1. Simplified Block Diagram that illustrates the basic structure of the SYN500R. It is made
of three sub-blocks; Image Rejection UHF Down-converter, the OOK Demodulator, and
Reference and Control Logics. Outside the device, the SYN500R requires only three components
to operate: two capacitors (CTH, and CAGC) and the reference frequency device, usually a quartz
crystal. An additional five components may be used to improve performance. These are: power
supply decoupling capacitor, two components for the matching network, and two components for
the pre-selector band pass filter.

13. Receiver Operation

13.1. LNA
The RF input signal is AC-coupled into the gate circuit of the grounded source LNA input stage.
The LNA is a Cascoded NMOS.

13.2. Mixers and Synthesizer

The LO ports of the Mixers are driven by quadrature local oscillator outputs from the synthesizer
block. The local oscillator signal from the synthesizer is placed on the low side of the desired RF
signal to allow suppression of the image frequency at twice the IF frequency below the wanted
signal. The local oscillator is set to 32 times the crystal reference frequency via a phase-locked

*This specification is subject to change without notification. -8-

 SYN500R

loop synthesizer with a fully integrated loop filter.

13.3. Image Reject Filter and Band-Pass Filter

The IF ports of the mixer produce quadrature down converted IF signals. These IF signals are
low-pass filtered to remove higher frequency products prior to the image reject filter where they
are combined to reject the image frequencies. The IF signal then passes through a third order band
pass filter. The IF center frequency is 1.2MHz. The IF BW is 330kHz @ 433.92MHz, and this
varies with RF operating frequency. The IF BW can be calculated via direct scaling:
Operating Freq(MHz)
BWIF = BWIF@433.92 MHz ×
433.92
These filters are fully integrated inside the SYN500R.
After filtering, four active gain controlled amplifier stages enhance the IF signal to proper level for
demodulation.

13.4. OOK Demodulator

The demodulator section is comprised of detector, programmable low pass filter, slicer, and AGC
comparator.

13.5. Detector and Programmable Low-Pass Filter

The demodulation starts with the detector removing the carrier from the IF signal. Post detection,
the signal becomes base band information. The programmable low-pass filter further enhances
the base band information. There are four programmable low-pass filter BW settings: 1625Hz,
3250Hz, 6500Hz, 13000Hz for 433.92MHz operation. Low pass filter BW will vary with RF
Operating Frequency. Filter BW values can be easily calculated by direct scaling. See equation
below for filter BW calculation:
Operating Freq(MHz)
BWOperating Freq = BW@433.92MHz ×
433.92
It is very important to choose the filter setting that best fits the intended data rate to minimize data
distortion.
Demod BW is set at 13000Hz @ 433.92MHz as default (assuming both SEL0 and SEL1 pins are
floating). The low pass filter can be hardware set by external pins SEL0 and SEL1.

SEL0 SEL1 Demod BW (@ 434MHz)

0 0 1625Hz
1 0 3250Hz
0 1 6500Hz
1 1 13000Hz-default
Table 1: Demodulation BW Selection

*This specification is subject to change without notification. -9-

 SYN500R

13.6. Slicer, Slicing Level

The signal prior to slicer is still linear demodulated AM. Data slicer converts this signal into
digital “1”s and “0”s by comparing with the threshold voltage built up on the CTH capacitor.
This threshold is determined by detecting the positive and negative peaks of the data signal and
storing the mean value. Slicing threshold default is 50%. After the slicer the signal is now digital
OOK data .
During long periods of “0”s or no data period, threshold voltage on the CTH capacitor may be
very low. Large random noise spikes during this time may cause erroneous “1”s at DO pin.

13.7. AGC Comparator

The AGC comparator monitors the signal amplitude from the output of the programmable
low-pass filter. When the output signal is less than 750mV thresh-hold, 1.5µA current is sourced
into the external CAGC capacitor. When the output signal is greater than 750mV, a 15µA current
sink discharges the CAGC capacitor. The voltage developed on the CAGC capacitor acts to
adjust the gain of the mixer and the IF amplifier to compensate for RF input signal level variation.

13.8. Reference Control

There are 2 components in Reference and Control sub-block:
1) Reference Oscillator
2) Control Logic through parallel Inputs: SEL0, SEL1, SHDN

13.9. Reference Oscillator

Figure 2: Reference Oscillator Circuit

The reference oscillator in the SYN500R (Figure 2) uses a basic Colpitts crystal oscillator
configuration with MOS transconductor to provide negative resistance. All capacitors shown in
Figure 2 are integrated inside SYN500R. R01 and R02 are external pins of SYN500R. User only
needs to connect reference oscillation crystal.

*This specification is subject to change without notification. - 10 -

 SYN500R

Reference oscillator crystal frequency can be calculated:

FREF OSC = FRF/(32 + 1.1/12)
For 433.92 MHz, FREF OSC = 13.52127 MHz.
To operate the MICRF211 with minimum offset, crystal frequencies should be specified with
10pF loading capacitance.

14. Applications Information

Figure 3. SYN500R Application Example, 433.92 MHz

The SYN500R can be fully tested by using one of many evaluation boards designed at Synoxo for
this device. As an entry level, the SYN500R evaluation board(Figure 3) offers a good start for
most applications. It has a helical PCB antenna with its matching network, a band-pass-filter
front-end as a pre-selector filter, matching network and the minimum components required to
make the device work, which are a crystal, Cagc, and Cth capacitors. By removing the matching
network of the helical PCB antenna (C9 and L3), a whip antenna (ANT2) or a RF connector (J2)
can be used instead. Figure 3 shows the entire schematic of it for 433.92MHz. Other frequencies
can be used and the values needed are in the tables below.
Capacitor C9 and inductor L3 are the passive elements for the helical PCB matching network. A
tight tolerance is recommended for these devices, like 2% for the inductor and 0.1pF for the
capacitor. PCB variations may require different values and optimization. Table 2 shows the
matching elements for the device frequency range. For additional information look for Small PCB
Antennas for Synoxo RF Products application note.

Freq(MHz) C9(pF) L3(nH)

390.0 1.2 43
418.0 1.2 36
433.92 1.5 30
Table 2. Matching Values for the Helical PCB Antenna

To use another antenna, like the whip kind, remove C9 and place the whip antenna in the hole
provided in the PCB. Also, a RF signal can be injected there.

*This specification is subject to change without notification. - 11 -

 SYN500R

L1 and C8 form the pass-band-filter front-end. Its purpose is to attenuate undesired outside band
noise which reduces the receiver performance. It is calculated by the parallel resonance equation
f = 1/(2×PI×(SQRT L1×C8)). Table 3 shows the most used frequency values.

Freq(MHz) C8(pF) L1(nH)

390.0 6.8 24
418.0 6.0 24
433.92 5.6 24
Table 3. Band-Pass-Filter Front-End Values

There is no need for the band-pass-filter front-end for applications where it is proven that the
outside band noise does not cause a problem. The SYN500R has image reject mixers which
improve significantly the selectivity and rejection of outside band noise.
Capacitor C3 and inductor L2 form the L-shape matching network. The capacitor provides
additional attenuation for low frequency outside band noise and the inductor provides additional
ESD protection for the antenna pin. Two methods can be used to find these values, which are
matched close to 50Ω. One method is done by calculating the values using the equations below
and another by using a Smith chart. The latter is made easier by using software that plots the
values of the components C8 and L1, like WinSmith by Noble Publishing.
To calculate the matching values, one needs to know the input impedance of the device. Table 4
shows the input impedance of the SYN500R and suggested matching values for the most used
frequencies. These suggested values may be different if the layout is not exactly the same as the
one made here.

Freq (MHz) C3 (pF) L2(nH) Z device (Ω)

390.0 1.5 47 22.5 – j198.5
418.0 1.5 43 21.4 – j186.1
433.92 1.5 39 18.6 – j174.2
Table 4: matching values for the most used frequencies

For the frequency of 433.92MHz, the input impedance is Z = 18.6 – j174.2Ω, then the matching
components are calculated by,
Equivalent parallel = B = 1/Z = 0.606 + j5.68 msiemens
Rp = 1 / Re (B); Xp =1/ Im (B)
Rp = 1.65kΩ; Xp = 176.2Ω
Q = SQRT (Rp/50 + 1)
Q = 5.831
Xm = Rp / Q
Xm = 282.98Ω
Resonance Method for L-shape Matching Network

*This specification is subject to change without notification. - 12 -

 SYN500R

Lc = Xp / (2×Pi×f); Lp = Xm / (2×Pi×f)
L2 = (Lc×Lp) / (Lc + Lp); C3 = 1 / (2×Pi×f×Xm)
L2 = 39.8nH
C3 = 1.3pF
Doing the same calculation example with the Smith Chart, it would appear as follows,
First, we plot the input impedance of the device, (Z = 18.6 – j174.2)Ω @ 433.92MHz.(Figure 4).

Figure 4: device’s input impedance, Z = 18.6 – j174.2Ω

Second, we plot the shunt inductor (39nH) and the series capacitor (1.5pF) for the desired input
impedance (Figure 5). We can see the matching leading to the center of the Smith Chart or close to
50Ω.

*This specification is subject to change without notification. - 13 -

 SYN500R

Figure 5. Plotting the Shunt Inductor and Series Capacitor.

Crystal Y1 or Y1A (SMT or leaded respectively) is the reference clock for all the device internal
circuits. Crystal characteristics of 10pF load capacitance, 30ppm, ESR < 50Ω, -40ºC to +105ºC
temperature range are desired. Table 5 shows the crystal frequencies and one of Synoxo’s
approved crystal manufacturers (www.hib.com.br).
The oscillator of the SYN500R is a Colpitts type. It is very sensitive to stray capacitance loads.
Thus, very good care must be taken when laying out the printed circuit board. Avoid long traces
and ground plane on the top layer close to the REFOSC pins RO1 and RO2. When care is not
taken in the layout, and crystals from other vendors are used, the oscillator may take longer times
to start as well as the time to good data in the DO pin to show up. In some cases, if the stray
capacitance is too high (> 20pF), the oscillator may not start at all.

*This specification is subject to change without notification. - 14 -

 SYN500R

The crystal frequency is calculated by REFOSC = RF Carrier/(32+(1.1/12)). The local oscillator is

low side injection (32 × 13.52127MHz = 432.68MHz), that is, its frequency is below the RF
carrier frequency and the image frequency is below the LO frequency. See Figure 6. The product
of the incoming RF signal and local oscillator signal will yield the IF frequency, which will be
demodulated by the detector of the device.

Figure 6. Low Side Injection Local Oscillator.

REFOSC (MHz) Carrier (MHz) HIB Part Number

12.15269 390.0 SA-12.152690-F-10-H-30-30-X
13.02519 418.0 SA-13.025190-F-10-H-30-30-X
13.52127 433.92 SA-13.521270-F-10-H-30-30-X

Table 5. Crystal Frequency and Vendor Part Number.

JP1 and JP2 are the bandwidth selection for the demodulator bandwidth. To set it correctly, it is
necessary to know the shortest pulse width of the encoded data sent in the transmitter. Like in the
example of the data profile in the figure 7 below, PW2 is shorter than PW1, so PW2 should be
used for the demodulator bandwidth calculation which is found by 0.65/shortest pulse width. After
this value is found, the setting should be done according to Table 6. For example, if the pulse
period is 100µsec, 50% duty cycle, the pulse width will be 50µsec (PW = (100µsec × 50%) / 100).
So, a bandwidth of 13kHz would be necessary (0.65 / 50µsec). However, if this data stream had a
pulse period with 20% duty cycle, the bandwidth required would be 32.5kHz (0.65 / 20µsec),
which exceeds the maximum bandwidth of the demodulator circuit. If one tries to exceed the
maximum bandwidth, the pulse would appear stretched or wider.

SEL0 SEL1 Demod. BW Shortest Pulse Maximum baud rate for 50%
JP1 JP2 (hertz) (µsec) Duty Cycle (hertz)

Short Short 1625 400 1250

Open Short 3250 200 2500
Short Open 6500 100 5000
Open Open 13000 50 10000

Table 6. JP1 and JP2 setting, 433.92 MHz.

*This specification is subject to change without notification. - 15 -

 SYN500R

Other frequencies will have different demodulator bandwidth limits, which are derived from the
reference oscillator frequency. Table 7 and Table 8 below shows the limits for the other two most
used frequencies.

SEL0 SEL1 Demod. Shortest Pulse Maximum baud rate for 50%
JP1 JP2 BW (hertz) (µsec) Duty Cycle (hertz)

Short Short 1565 416 1204

Open Short 3130 208 2408
Short Open 6261 104 4816
Open Open 12523 52 9633

Table 7. JP1 and JP2 setting, 418.0 MHz.

SEL0 SEL1 Demod. Shortest Pulse Maximum baud rate for 50%
JP1 JP2 BW (hertz) (µsec) Duty Cycle (Hertz)

Short Short 1460 445 1123

Open Short 2921 223 2246
Short Open 5842 111 4493
Open Open 11684 56 8987

Table 8. JP1 and JP2 setting, 390.0 MHz.

Capacitors C6 and C4, CTH and CAGC respectively provide time base reference for the data pattern
received. These capacitors are selected according to data profile, pulse duty cycle, dead time
between two received data packets, and if the data pattern has or does not have a preamble. See
Figure 7, example of a data profile.

Figure 7. Example of a Data Profile.

For best results the capacitors should always be optimized for the data pattern used. As the baud
rate increases, the capacitor values decrease. Table 9 shows suggested values for Manchester
Encoded data, 50% duty cycle.

SEL0 JP1 SEL1 JP2 Demod. BW CTH CAGC

(hertz)

*This specification is subject to change without notification. - 16 -

 SYN500R

Short Short 1625 100nF 4.7µF

Open Short 3250 47nF 2.2µF
Short Open 6500 22nF 1µF
Open Open 13000 10nF 0.47µF

Table 9. Suggested CTH and CAGC Values.

Other components used are C5, which is a decoupling capacitor for the VDD line, R4 reserved for
future use and not needed for the evaluation board, R3 for the shutdown pin (SHDN = 0, device is
operation), which can be removed if that pin is connected to a microcontroller or an external
switch, R1 and R2 which form a voltage divider for the AGC pin. One can force a voltage in this
AGC pin to purposely decrease the device sensitivity. Special care is needed when doing this
operation, as an external control of the AGC voltage may vary from lot to lot and may not work
the same for several devices.
Three other pins are worthy of comment. They are the DO, RSSI, and shut down pins. The DO pin
has a driving capability of 0.4mA. This is good enough for most of the logic family ICs in the
market today. The RSSI pin provides a transfer function of the RF signal intensity vs voltage. It is
very useful to determine the signal to noise ratio of the RF link, crude range estimate from the
transmitter source and AM demodulation, which requires a low CAGC capacitor value.
The shut down pin (SHDN) is useful to save energy. When its level close to VDD (SHDN = 1), the
device is not in operation. Its DC current consumption is less than 1µA (do not forget to remove
R3). When toggling from high to low, there will be a time required for the device to come to
steady state mode, and a time for data to show up in the DO pin. This time will be dependent upon
many things such as temperature, crystal used, and if the there is an external oscillator with faster
startup time. Normally, with the crystal vendors suggested, the data will show up in the DO pin
around 1msec time, and 2msec over the temperature range of the device. When using an external
oscillator or reference oscillator signal, the time is reduced considerably and can be around
140µsec. See Figures Figure 10 and 11.

Figure 10: Time-to-Good Data After Shut Down Cycle, Room Temperature.

*This specification is subject to change without notification. - 17 -

 SYN500R

Figure 11. Time to Good Data, External Oscillator, Room Temperature.

15. Package Information

SSOP16 Package Type

*This specification is subject to change without notification. - 18 -