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Design and implementation of numerical controlled oscillator on FPGA

Conference Paper · July 2013

DOI: 10.1109/WOCN.2013.6616221

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 Design and Implementation of Numerical Controlled
Oscillator on FPGA
Nehal.A.Ranabhatt1, Sudhir Agarwal2, Raghunadh.K.Bhattar3 , Priyesh.P.Gandhi4
1
PG Student,
Student L. C. Institute of Technology, Bhandu
2
Head, DCTD, Space Application Center, ISRO, Ahmedabad
3
Sci/Engg,DCT
,DCTD, Space Application Center, ISRO, Ahmedabad
4
Assistant Professor, L. C. Institute of Technology, Bhandu
nehal16.ranabhatt@gmail.com1, sudhir@sac.isro.gov.in 2, raghu@sac.isro.gov.in 3 priyesh.gandhi@lcit.org4


Abstract— This paper represents Design and
Implementation of Numerical Controlled Oscillator on
StratixIII FPGA. In this Design output frequency of Numerical
controlled Oscillator is User Controllable. This Design will
later used to implement Modulation and Demodulation on
StratixIII FPGA.

Index Terms— NCO, FPGA, Modulation, Demodulation, ROM

I. INTRODUCTION
A numerically controlled oscillator (NCO) is a
digital signal generator which creates a synchronous (i.e.
clocked), discrete-time, discrete-valued
valued representation of
a waveform, usually sinusoidal[1] .NCOs
NCOs are often used in
conjunction with a digital-to-analog
analog converter (DAC) at the
output to create a direct digital synthesizer (DDS)
Numerically Controlled Oscillators (NCO), also called
Direct Digital Synthesizers (DDS), offerr several advantages
over other types of oscillators in terms of accuracy, stability
and reliability. NCOs provide a flexible architecture that
enables easy programmability such as on frequency/phase.
NCOs are used in many communications systems
including digital up/down converters used in 3G wireless
and software radio systems, digital PLLs, radar
systems, drivers for optical or acoustic transmissions,
and multilevel FSK/PSK modulators/ demodulators [2].In
this design NCO worked at 120MHz clock rate which whi will
generate Positive Sine wave and Negative sine Wave.
Because this NCO design will use in BPSK Modulation, Fig.1. Design of Numerical Controlled Oscillator
works on 1200 Bits per second that will be implement on
StratixIII FPGA Provided By Altera. Divided 0 to 360 degrees in 10000 parts with each value
differing the previous by 360/10000.Then we took sine of
II. DESIGN OF NUMERICAL CONTROLLED OSCILLATOR ON
all these degrees to get 10000 sine values which are between
FPGA
and including -11 to 1 making one sinewave.
sinewave.Since our
In our design we have used two Altera Mega function.
samples of sine wave ave have to be given out to Digital to
They are PLL and rom_sine_samples.PLL (Phase Lock
Analog Converter which is of 14 bits and hhas positive
Loop) is used to convert the board clock of 125 MHz to 120
threshold level, we have to convert above 10000 values in
MHz.rom_sine_samples is a ROM which has 10 thousand
range hexadecimal 0000 to 3fff then we multiply all the
samples of 14 bits of a sine wave full cycle
cyc in between 0 to
10000 sine values
lues with hexadecimal 1fff. we get values in
360 degrees, stored in to it. The samples are generated and
range -1fff to +1fff.Then
Then threshold level was added to each
stored in following way.
sample and we finally get the range of 10000 sine wave

978-1-4673-5999-3/13/$31.00 ©2013 IEEE

samples in between 0000 to 3ffe, which we have stored in ROM block in a single MLAB. Depending on which
rom_sine_samples. TriMatrix memory block you target, the following modes
For one sine wave we have stored 10000 samples may be used: Single-port, Simple dualdual-port, True dual-port,
Shift-register, ROM, FIFO. When using the memory blocks
of 14 bits. A constant value phase_acc which holds the
in ROM, single-port,
port, simple dual
dual-port, or true dual-port
number of sine waves required per 1 lakh clock, it mode, you can corrupt the memory conte contents if you violate
determines the carrier frequency or output frequency and the setup or hold-time
time on any of the memory block input
number of samples per sine wave. In our design we have registers. This applies to both read and write operations.
another counter, counter_10 which is modulo 10 counters. ROM Mode: All Stratix III TriMatrix memory blocks
Whenever the counter_10 value is 10, sine wave sample support ROM mode. A .mif file initializes the ROM content
address generation logic increments ts the address to the of these blocks.
s. The address lines of the ROM are registered
on M9K and M144K blocks, but can be unregistered on
rom_sine_samples by constant phase_acc. Thus in 1 lakh
MLABs. The outputs can be registered or unregistered.
count, rom_sine_samples outputs 10000 samples (1lakh/10 Output registers can be asynchronously cleared. The ROM
= 10000).So if phase_acc = 1 then entire 10000 samples of read operation is identical to the read operati
operation in the single-
rom_sine_samples will be fetched and given out, so in this port RAM configuration [9].
case one sine wave generated. If phase_acc= 2 then alternate
samples will be fetched twice. To generate two sine wave
and so on. Output of Positive sine wave was take on dac1 III. SIMULATION RESULTS AND REAL-TIME
and output of 180 Phase shifted sine wave was taken on RESULTS
dac2.

MegaFuctions Used In Design

1. Phase Locked Loop .
The Phase-Locked
Locked Loop (PLL) is a closed-loop closed
frequency-control
control system that compares the phase difference
between the input signal and the output signal of a voltage-
voltage
controlled oscillator (VCO). The negative feedback loop of
the system forces the PLL to be phase-locked.
locked. The PLL can
be used to generate stable frequencies, recover signals from
a noisy communication channel, or distribute clock signals
throughout your design. PLL is working in normal mode
Fig.2 Simulation of Numerical Controlled Oscillator when fo=12kHZ
operation. The PLL feedback pathh source is a global or
regional clock network, minimizing clock delay to registers Fig.2 shows simulation results when output frequency is
for that clock type and specific PLL output. The PLL can equal to 12KHZ.This frequency can be obtained when
generate a number of clock output signals depending on the phase_acc=10 ,so 10000/10=1000 .It indicates 10 sine wave
PLL type and the device family that you select in the are generated and each sine wave contains 1000 samples.
ALTPLL
TPLL Mega Wizard interface. In PLL output clock Here 10000 samples taken in ROM aare divide by phase_acc
frequency can be obtained by multiplying input clock value and output value of this division is divided by
frequency with ratio of multiplication factor and division 120MHz clk. 120M/1000=12KHz frequency is obtained at
factor[9]. output. Here positive sine wave and 180 degree phase
2.ROM shifted negative sine wave taken in output.
TriMatrix embedded memory blocks provide three
different sizes of embedded SRAM to efficiently address the
needs of Stratix® III FPGA designs. TriMatrix memory
includes 640- (in ROM mode only) or 320-bit
320 memory logic
array blocks (MLABs), 9-Kbit Kbit M9K blocks, and 144-Kbit
144
M144K blocks. The MLABs have been optimized to
implement filter delay lines, small first-in
in first-out
first (FIFO)
buffers, and shift registers. we can use the M9K blocks for
general purpose memory applications, and the M144K
blocks are ideal for processor code storage, packet
buffering, While the M9K and M144K memory blocks bl are
dedicated resources, the MLABs are dual-purpose
dual blocks.
They can be configured as regular logic array blocks (LABs)
or as memory logic array blocks (MLABs). Ten adaptive
logic modules (ALMs) make up one MLAB. Each ALM in
an MLAB can be configured as a 16×2 block, resulting in a
Fig.3 Simulation of Numerical
cal Controlled Oscillator when fo=18kHZ
16×20 simple dual-port
port SRAM block in a single MLAB. In
ROM mode, each ALM in an MLAB can an be configured as Fig.3 shows simulation result when output frequency is
either a 64×1 or a 32×2 block, resulting in a 64×10 or 32×20
32× equal to 18KHZ.This frequency can be obtained at output
when phase_acc=15 so 10000/15=666.66.This value is Fig.6 shows Numerical controlled oscillator output on
divided by 12MHz clock.120M/666.66=18KHz frequency is Oscilloscope when fo=12KHZ.
obtained in output.

Fig.7 Experimental setup for NCO when fo=18kHZ

Fig.4 Simulation of Numerical Controlled Oscillator when fo=36kHZ Fig.7 shows Numerical controlled oscillator output on
Oscilloscope when fo=18KHZ.
Fig.4 shows simulation result when output frequency is
equal to 36KHZ.This
6KHZ.This frequency can be obtained at output
when phase_acc=15 so 10000/30=333.33.This value is
divided by 12MHz clock.120M/333.33=36KHz frequency is
obtained in output.

Fig.8 Experimental setup for NCO when fo=36kHZ

Fig.8 shows Numerical controlled oscillator output on

Oscilloscope when fo=36KHZ.

Fig.5 Simulation of Numerical Controlled Oscillator when fo=48kHZ

Fig.5 shows simulation

ulation result when output frequency is
equal to 36KHZ.This output frequency can be obtained in
output when phase_acc=40 so 10000/40=250.This value
was divided by 12MHz clock.120M/333.33=48KHz
frequency is obtained in output.

Fig.9 Experimental setup for NCO when fo=48kHZ

Fig.9 shows Numerical controlled oscillator output on

Oscilloscope when fo=48KHZ.

Fig.6 Experimental setup for NCO when fo=12kHZ

 IV. CONCLUSION
In this paper, Design and Implementation of NCO is
presented on straixIII DSP development board .This NCO
will use for generating carrier in Modulation and
Demodulation. Here output frequencies of NCO are user
variable. Here we put simulation results at variable output
frequency for Positive and Negative sine wave. Because this
NCO is Mainly Designed to Make BPSK Modulation and
Demodulation on StratixIII dsp development Board. So with
help of Positive and negative sine wave BPSK modulated
wave can be generated easily by using logic that if Bit “1”
Comes form input pattern then positive sine wave will
generate and if Bit “0” comes then negative sine wave will
generate on output side. so we get BPSK modulated wave in
output.

REFERENCES

[1]Jane Radatz, The IEEE Standard Dictionary of Electrical and

Electronics Terms, IEEE Standards Office, New York, NY, 1997
[2]"Numerically Controlled Oscillator". Lattice Semiconductor
Corporation. 2009.
[3]Miller, Brian M., "Numerically controlled oscillator and method of
operation", issued October 14, 2008.
[4]"The NCO as a Stable, Accurate Synthesizer". Intersil Corporation.
1998.
[5]McAllister, Ronald D. & Daniel Shearer III, "Numerically controlled
oscillator using quadrant replication and function decomposition",
published 12/04/1984
[6]C. Erdoğan, I. Myderrizi, and S. Minaei “FPGA Implementation of
BASK-BFSK-BPSK Digital Modulators” IEEE Antennas and Propagation
Magazine, Vol. 54, No. 2, April 2012.
[7]Mehmet Sonmez and Ayhan Akbal “FPGA-Based BASK and BPSK
Modulators Using VHDL: Design, Applications and Performance
Comparison for Different Modulator Algorithms” In March 2012,
International Journal of Computer Applications (0975 – 8887) Volume 42–
No.13, March 2012.
[8]S.O.Popescu and A.S. Gontean “Performance comparison of the
BPSK and QPSK Modulation Techniques on FPGA” 17th International
Symposium for Design and Technology in Electronic Packaging (SIITME)
2011 IEEE .
[9]http://www.altera.com/devices/fpga/stratix-fpgas/stratix-
iii/overview/st3-overview.html
[10]http://www.altera.com/devices/fpga/stratix-fpgas/stratix
iii/overview/architecture/st3- dsp.html
[11]http://www.altera.com/devices/fpga/stratix-fpgas/stratix-
iii/overview/power/st3-power.html-video

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