Department of Electronics and Communication Engg.
Faculty of Engineering and Technology
Jamia Millia Islamia
2020-21
VLSI LAB FILE
ECS 711
SUBMITTED BY:
Abuzar Shakeel 17BEC058
1
Table of Contents
Programs Page No.
1. AND gate………………………………………………………….…03
2. NAND gate…………………………………………………………..05
3. XOR gate………………………………………………………….…07
4. Full adder…………………………………………………………....09
5. Multiplexer…………………………………………………………...11
6. 4 bit parallel adder……………………………………………….....13
7. 4 bit parity generator…………………………………………….....15
8. SR Latch………………………………………………………….....16
9. SR flip flop……………………………………………………….…..18
10. 4 bit up counter……………………………………………....….20
2
Experiment 1
Aim: To write a program in VHDL for implementing an AND gate.
Program:
VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;
entity and1 is
port(x,y:in bit ; z:out bit);
end and1;
architecture ABC of and1 is
begin
z<=x and y;
end ABC;
Truth Table:
3
Waveform:
4
Experiment 2
Aim: To write a program in VHDL for implementing a NAND gate.
Program:
VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;
entity nand1 is
port(a,b:in bit ; c:out bit);
end nand1;
architecture ABC of nand1 is
begin
c<=a nand b;
end ABC;
Truth Table:
5
Waveform:
6
Experiment 3
Aim: To write a program in VHDL for implementing a XOR gate.
Program:
VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;
entity xor1 is
port(a,b:in bit; q:out bit);
end xor1;
architecture ABC of xor1 is
begin
q<=a xor b;
end ABC;
Truth Table:
7
Waveform:
8
Experiment 4
Aim: To write a program in VHDL for implementing a full adder.
Program:
VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port(a,b,c:in bit; sum,carry:out bit);
endfull_adder;
architecture data of full_adder is
begin
sum<= a xor b xor c;
carry<=((a and b)or(b and c)or(a and c));
end data;
Truth Table:
9
Waveform:
10
Experiment 5
Aim: To write a program in VHDL for implementing a 4x1 multiplexer.
Program:
VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;
entity mux is
port(S1,S0,D0,D1,D2,D3:in bit; Y:out bit);
end mux;
architecture data of mux is
begin
Y<=(notS0 and notS1 and D0)or
(S0 and notS1 and D1)or
(notS0 and S1 and D2)or
(S0 and S1 and D3);
end data;
Truth Table:
11
Waveform:
12
Experiment 6
Aim: To write a program in VHDL for implementing a 4 bit parallel
binary adder(or 4 bit ripple carry adder).
Program:
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity pa is
port(a :in STD_LOGIC_VECTOR(3 downto 0);
b :in STD_LOGIC_VECTOR(3 downto 0);
ca:out STD_LOGIC;
sum :out STD_LOGIC_VECTOR(3 downto 0)
);
end pa;
architecture ABC of pa is
component fa is
port(a :in STD_LOGIC;
b :in STD_LOGIC;
c :in STD_LOGIC;
sum :out STD_LOGIC;
ca:out STD_LOGIC
);
end component;
signal s :std_logic_vector(2 downto 0);
signal temp:std_logic;
begin
temp<='0';
u0 :fa port map (a(0),b(0),temp,sum(0),s(0));
u1 :fa port map (a(1),b(1),s(0),sum(1),s(1));
u2 :fa port map (a(2),b(2),s(1),sum(2),s(2));
ue :fa port map (a(3),b(3),s(2),sum(3),ca);
end ABC;
13
Waveform:
14
Experiment 7
Aim: To write a program in VHDL for implementing a 4 bit parity
generator.
Program:
VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;
entity paritygen is
port(a0, a1, a2, a3:in std_logic; p_odd,p_even:out std_logic);
end paritygen;
architecture ABC of paritygen is
begin
process(a0, a1, a2, a3)
if(a0 ='0'and a1 ='0'and a2 ='0'and a3 =’0’)
then odd_out<="0";
even_out<="0";
else
p_odd<=(((a0 xor a1)xor a2)xor a3);
p_even<=not(((a0 xor a1)xor a2)xor a3);
end ABC
Waveform:
15
Experiment 8
Aim: To write a program in VHDL for implementing an SR latch.
Program:
VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;
entity srl is
port(r,s:in bit; q,qbar:buffer bit);
end srl;
architecture behv of srl is
signal s1,r1:bit;
begin
q<= s nand qbar;
qbar<= r nand q;
end behv;
Truth Table:
16
Waveform:
17
Experiment 9
Aim: To write a program in VHDL for implementing an SR flip flop.
Program:
VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;
entity srflip is
port(r,s,clk:in bit;q,qbar:buffer bit);
end srflip;
architecture behv of srflip is
signal s1,r1:bit;
begin
s1<=s nand clk;
r1<=r nand clk;
q<= s1 nand qbar;
qbar<= r1 nand q;
end behv;
Truth Table:
18
Waveform:
19
Experiment 10
Aim: To write a program in VHDL for implementing a 4 bit up counter.
Program:
VHDL Code:
library IEEE;
use ieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entity counter is
port(Clock, CLR :instd_logic;
Q :outstd_logic_vector(3 downto 0)
);
end counter;
architecture behv of counter is
signaltmp:std_logic_vector(3 downto 0);
begin
process(Clock, CLR)
begin
if(CLR ='1')then
tmp<="0000";
elsif(Clock'event and Clock = '1') then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end behv;
20
Waveform:
21
