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HDL Exp4

The document outlines Experiment No. 4 conducted on August 22, 2019, with the aim of implementing VHDL programs for calculating the factorial of a number, creating an N bit full adder, and reversing an N bit vector. It includes the VHDL code for each implementation, along with waveforms and RTL views. The results confirm successful implementation and simulation of all three VHDL programs.

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Hrishikesh Ugle
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38 views5 pages

HDL Exp4

The document outlines Experiment No. 4 conducted on August 22, 2019, with the aim of implementing VHDL programs for calculating the factorial of a number, creating an N bit full adder, and reversing an N bit vector. It includes the VHDL code for each implementation, along with waveforms and RTL views. The results confirm successful implementation and simulation of all three VHDL programs.

Uploaded by

Hrishikesh Ugle
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Experiment no.

4
Experiment Date: 22nd August 2019 Submission Date: 5th Sept 2019

Aim :
1. To write a VHDL program for implementation of factorial of given number.
2. To write a VHDL program for implementation of a N bit full adder.
3. To write a VHDL program for reversing a N bit vector.

Software Used :
Intel Quartus II

Code :

A. Factorial of an Integer N
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

Entity facto is
port (a: In Integer range 0 to 10;
O: Out Integer);
end facto;

Architecture dataflow of facto is


Begin
process(a)
variable y, i : Integer;
begin
y:= 1;
i:= 1;

while i <= a loop


y := y * i;
i := i + 1;
end loop;
O <= y;
end process;
end dataflow;

B. N bit full adder


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

Entity Nfulladder is
Generic (N : Integer := 4);
port(A, B : In std_logic_vector(N-1 downto 0);
Cin: In std_logic ;
S: Out std_logic_vector(N-1 downto 0);
Cout:Out std_logic );
end Nfulladder;

Architecture Dataflow of Nfulladder is


Begin
process(A, B, Cin)
variable c1, c2, s1: std_logic;
variable i: Integer;
begin
c1 := Cin;
c2 := '0';
s1 := '0';
i := 0;

for i in 0 to N-1 loop


s1 := A(i) xor B(i) xor c1;
S(i) <= s1;
c2 := (A(i) and B(i)) or (c1 and (A(i) xor B(i)));
c1 := c2;
end loop;

2
Cout <= c2;
end process;
end Dataflow;

C. Reversal of N bit vector


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

Entity reverser is
Generic (N :Integer := 4);
port(I : In std_logic_vector(N-1 downto 0) ;
O : Out std_logic_vector (N-1 downto 0));
end reverser;

Architecture dataflow of reverser is


begin
process(I)
variable i1 : Integer;
begin
i1:= 0;

for i1 in I'range loop


O(N-i1-1) <= I(i1);
end loop;

end process;
end dataflow;

3
Waveforms :

A. Factorial of a number

B. N bit full adder

C. Reversal of bit vector of size N

4
RTL View :

B. N bit full adder

C. Reversal of bit vector

Results :
1. A VHDL program to find factorial of any generic integer N was implemented
and simulated.
2. N bit full adder was implemented with N being a any generic integer.
3. A VHDL program for reversal of any bit vector of size N was implemented
and simulated.

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