Name: Thrishanthi R
RegisterNo:3122223002088
Exp.No:01
Date:
DESIGN AND IMPLEMENTATION OF FULLADDER
AIM:
To design and implement the fulladder using structural/behavioural model and verify their
functionality using Nexys A7 FPGA Trainer Kit.
To design and model a 1-bit Full adder using structural/dataflow/behavioural modelling.
To compile, simulate and plot the results using Xilinx Vivado Tools.
To implement the proposed systems using Xilinx Tools and generate the synthesis report.
To demonstrate the working of the proposed systems using Nexys A7 FPGA Trainer Board.
EQUIPMENT/SOFTWARE REQUIRED:
Hardware: Nexys A7 ARTIX-7 100T FPGA with Device Type CSG324 based Trainer Kit
Software: Xilinx Vivado
THEORY:
A full adder is a fundamental digital circuit used for adding three binary numbers: two primary bits
and an additional carry-in bit from a previous stage. It outputs two results: the sum and the carry-
out. To determine the sum, the circuit uses an exclusive OR (XOR) operation on the two primary
bits and the carry-in bit, which produces a high result if an odd number of these inputs are high. The
carry-out, on the other hand, indicates whether there is an overflow that should be carried to the next
stage. It is calculated based on whether at least two out of the three inputs are high. Essentially, the
carry-out is high if both main bits are high or if one of the main bits and the carry-in bit are high.
Full adders are constructed using XOR gates for the sum, AND gates to identify potential carry
conditions, and an OR gate to combine these conditions and produce the final carry-out. These
circuits are essential in designing more complex arithmetic units in digital systems, enabling efficient
binary addition and processing.
Name: Thrishanthi R
RegisterNo:3122223002088
FUNCTIONAL DESCRIPTION:
LOGIC DIAGRAM:
BLOCK DIAGRAM:
TRUTH TABLE:
A B Carry-in Sum Carry-out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Name: Thrishanthi R
RegisterNo:3122223002088
BOOLEAN EQUATION:
Inputs: A, B &Cin:
Outputs: Sum: A ^ B ^ Cin
Carry: (A & B)|(B &Cin)|(Cin& A)
VERILOG HDL PROGRAM:
module fulladder ( A, B, Cin, Sum, Cout );
input A,B,Cin;
output Sum,Cout;
assign Sum = A ^ B ^ Cin;
assign Cout = (A & B) | (B & Cin) | (A & Cin);
endmodule
//TESTBENCH:
module fulladder_testbench;
reg A, B, Cin;
wire Sum, Cout;
fulladder L1 (Sum, Cout, A, B, Cin);
initial
begin
$monitor($time, " A=%b , B=%b , Cin=%b, Sum=%b, Cout=%b", A, B, Cin, Sum, Cout);
end
initial
begin
A = 1'b0; B = 1'b0; Cin = 1'b0;
#5 A = 1'b0; B = 1'b0; Cin = 1'b1;
Name: Thrishanthi R
RegisterNo:3122223002088
#10 A = 1'b0; B = 1'b1; Cin = 1'b0;
#15 A = 1'b0; B = 1'b1; Cin = 1'b1;
#20 A = 1'b1; B = 1'b0; Cin = 1'b0;
#25 A = 1'b1; B = 1'b0; Cin = 1'b1;
#30 A = 1'b1; B = 1'b1; Cin = 1'b0;
#35 A = 1'b1; B = 1'b1; Cin = 1'b1;
end
endmodule
SIMULATION RESULTS:
OUTPUT WAVEFORMS:
Name: Thrishanthi R
RegisterNo:3122223002088
UTILIZATION REPORT:
RTL SCHEMATIC DIAGRAM:
RESULT:
Thus, a model for full adder using dataflow modeling were compiled ,synthesized and
implemented.
Name: Thrishanthi R
Register No:3122223002088
Exp.No:02
Date:
DESIGN AND IMPLEMENTATION OF 4-BIT CARRY LOOKAHEAD
ADDER
AIM:
To design and implement the 4-bit carrylookahead adder using structural/behavioural model and
verify their functionality using Nexys A7 FPGA Trainer Kit
To design and model a 4-bit carrylookahead adder using structural/dataflow/behavioural
modelling.
To compile, simulate and plot the results using Xilinx Vivado Tools.
To implement the proposed systems using Xilinx Tools and generate the synthesis report.
To demonstrate the working of the proposed systems using Nexys A7 FPGA Trainer Board.
EQUIPMENT/SOFTWARE REQUIRED:
Hardware: Nexys A7 ARTIX-7 100T FPGA with Device Type CSG324 based Trainer Kit
Software: Xilinx Vivado
THEORY:
A Carry Look-Ahead Adder (CLA) improves binary addition speed by reducing the delay associated
with carry propagation. Unlike the Ripple Carry Adder, where each bit’s computation relies on the
carry from the previous bit, the CLA uses generate and propagate signals to predict carry outcomes
in advance. The generate signal indicates if a carry will be produced at a given bit position, while
the propagate signal shows if a carry-in will be passed to the next bit. By calculating carry-outs in
parallel rather than sequentially, the CLA significantly speeds up the addition process, especially for
large bit-widths.
This parallel computation minimizes the time required for carry signals to propagate through all
stages, making the CLA faster than traditional ripple carry adders. However, this enhanced speed
comes with increased circuit complexity and hardware requirements. Despite these trade-offs, the
CLA is widely used in high-performance computing systems where rapid arithmetic operations are
crucial.
Name: Thrishanthi R
Register No:3122223002088
FUNCTIONAL DESCRIPTION:
LOGIC DIAGRAM:
CARRY LOOK AHEAD GENERATOR:
Name: Thrishanthi R
Register No:3122223002088
CARRYLOOKAHEAD ADDER:
BLOCK DIAGRAM:
Name: Thrishanthi R
Register No:3122223002088
LOGIC TABLE:
VERILOG HDL PROGRAM:
module carrylookahead_adder (S, C4, A, B, C0);
input [3:0] A, B;
Output [3:0] S;
input C0;
Output C4;
Wire[3:0] P,G;
Wire C1, C2, C3;
assign C1 = G[0]| P[0]&C0, C2 = G[1]| P[1]&C1, C2 = G[1]| P[1]&C1, C3 = G[2]| P[2]&C2, C4 =
G[3]| P[3]&C3;
assign S[0] = P[0] ^C0, S[1] = P[1] ^C1, S[2] = P[2] ^C2,S[3] = P[3] ^C3;
module carrylookahead_adder_tb;
reg [3:0] A,B
reg C0;
wire [3:0] S;
Name: Thrishanthi R
Register No:3122223002088
Wire C4;
initial
begin
$monitor ($time, "A=%b, B=%b, C0=%b, S=%b, C4=%b, A, B, C0, S, C4);
end
initial
begin
A=4'b0000; B = 4’b0000; C0 = 1'bo;
#10 A=4'b0101; B = 1'b1010; C0 = 1'b1;
#10 A=4'b1101; B = 1'b1000; C0 = 1'b1;
#10 A=4'b0001; B = 1'b1110; C0 = 1'b1;
End
endmodule
SIMULATION RESULTS:
OUTPUT WAVEFORMS:
Name: Thrishanthi R
Register No:3122223002088
UTILIZATION REPORT:
RTL SCHEMATIC DIAGRAM:
Name: Thrishanthi R
Register No:3122223002088
TEST BENCH OUTPUT:
RESULT:
Thus, a model for 4-bit carrylookahead adder using dataflow modeling were compiled ,synthesized and
implemented.
Name: Thrishanthi R
Register No:3122223002088
Exp.No:03
Date:
DESIGN AND IMPLEMENTATION OF 4-BIT BOOTH MULTIPLIER
AIM:
To design and implement the 4-bit Booth Multiplier using structural/behavioural model and verify
their functionality using Nexys A7 FPGA Trainer Kit
To design and model a 4-bit Booth Multiplier using structural/dataflow/behavioural
modelling.
To compile, simulate and plot the results using Xilinx Vivado Tools.
To implement the proposed systems using Xilinx Tools and generate the synthesis report.
To demonstrate the working of the proposed systems using Nexys A7 FPGA Trainer Board.
EQUIPMENT/SOFTWARE REQUIRED:
Hardware: Nexys A7 100T FPGA with Device Type CSG324 based Trainer Kit
Software: Xilinx Vivado
THEORY:
Booth's algorithm is an efficient technique for multiplying binary numbers, particularly useful
for 4-bit multipliers in two's complement form. It reduces the number of addition operations by
encoding the multiplier into fewer operations based on patterns of bits. The algorithm examines the
multiplier two bits at a time, generating partial products that are added or subtracted based on the bit
patterns, and shifts the results to accumulate the final product. This approach handles both positive and
negative numbers effectively, making it suitable for digital hardware implementations. Booth's
algorithm reduces the number of arithmetic operations needed, making it efficient for hardware
implementation in digital systems, such as a 4-bit Booth multiplier.
Name: Thrishanthi R
Register No:3122223002088
FUNCTIONAL DESCRIPTION:
LOGIC DIAGRAM:
Name: Thrishanthi R
Register No:3122223002088
BLOCK DIAGRAM:
OPERATION TABLE:
VERILOG HDL PROGRAM:
module booth_mul(op, M, Q);
input [3:0] M, Q;
output reg[7:0] op;
reg Q1;
reg [3:0] A;
reg [8:0] K;
reg [3:0] Q_internal;
integer N;
always @(*)
begin
Q1 = 1'b0;
A = 4'b0000;
N = 4;
Name: Thrishanthi R
Register No:3122223002088
Q_internal = Q;
while (N > 0) begin
if (Q_internal[0] == 1'b0 && Q1 == 1'b1)
begin
A = A + M;
K = {A[3],A[3:0],Q_internal[3:0]};
Q1 = K[0];
A = K[8:5];
Q_internal = K[4:1];
end
else if (Q_internal[0] == 1'b1 && Q1 == 1'b0)
begin
A = A+(~M+1);
K = {A[3],A[3:0],Q_internal[3:0]};
Q1 = K[0];
A = K[8:5];
Q_internal = K[4:1];
end
else //if(Q_internal[0] == 1'b0 && Q1 == 1'b0||Q_internal[0] == 1'b1 && Q1 == 1'b1)
begin
K = {A[3],A[3:0],Q_internal[3:0]};
Q1 = K[0];
A = K[8:5];
Q_internal = K[4:1];
end
N = N - 1;
end
op= K[8:1];
end
endmodule
TEST BENCH CODE:
module BoothTB;
reg [3:0] M;
reg [3:0] Q;
wire [7:0] OP;
booth_mul M1(OP,M,Q);
initial begin
$monitor($time,"M=%b,Q=%b,OP=%b",M,Q,OP)end
initial begin
Name: Thrishanthi R
Register No:3122223002088
M = 4'b0101;Q = 4'b0100;
#10;
M=4'b1011;Q=4'b0100;
#10;
M=4'b0101;Q=4'b1100;
#10;
M=4'b1011;Q=4'b1100;
#10;
$finish;end
endmodule
SIMULATION RESULTS:
OUTPUT WAVEFORMS:
Name: Thrishanthi R
Register No:3122223002088
RTL SCHEMATIC DIAGRAM:
UTILIZATION REPORT:
Name: Thrishanthi R
Register No:3122223002088
TEST BENCH OUTPUT:
RESULT:
Thus, a model for 4-bit Booth Multiplier using dataflow modeling were compiled,synthesized
and implemented.
