DEPARTMENT OF ELECTRICAL AND
ELECTRONICS ENGINEERING
23E411 – DIGITAL ELECTRONICS AND LIC
LABORATORY
POST LAB REPORT ON
IMPLEMENTATION OF COMBINATIONAL &
SEQUENTIAL CIRCUITS USING VERILOG
SUBMITTED BY:
HARIVARSHA R G 24E403
KISHORE V A 24E404
MADHUMITHA C 24E405
NARMADHA S 24E407
RATHEESH M M 24E408
SHANMUGAM S 24E409
PRADEEP KUMAR S 24E501
SUBMITTED TO:
DR.A.GUNASUNDARI,
PROFESSOR,
DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING.
IMPLEMENTATION OF COMBINATIONAL & SEQUENTIAL
CIRCUITS USING VERILOG
AIM;
To design and simulate the simple combinational (Full Adder) and Sequential ( D and
T Flipflop circuits ) using Verilog.
TOOLS REQUIRED:
Vivado 16.2 Software.
THEORY:
A full-adder is a combinational circuit that forms the arithmetic sum of three input
bits. It consists of three inputs and two outputs. Two of the input variables, denoted by A and
B, represent the two significant bits to be added. The third input Cin, represents the carry
from the previous lower significant position. It produces two outputs Sum (S) and Carry(C).
FULL ADDER
Block Diagram:
Full Adder Truth Table:
INPUTS OUTPUTS
A B Cin Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Karnaugh Map Representation:
1. For Sum:
B, Cin
00 01 10 11
A
0 0 1 0 1
1 1 0 1 0
S = A ⊕ B ⊕ Cin
2. For Carry:
B, Cin
00 01 10 11
A
0 0 0 1 0
1 0 1 1 1
C == A B + Cin (A ⊕ B)
Logic Diagram:
W1
A ⊕ B ⊕ Cin
C- IN W1
W2
C- IN
C == A B + Cin(A ⊕ B)
W3
B
Logic Expression:-
Sum: Sum = A’B’Cin + ABC + A’BCin’ + AB’C
= A’(B’Cin + BCin’) + A(B’Cin + BCin)
=A Xor B Xor Cin
Carry: Carry = A'BCin + AB'Cin + ABCin’ + ABCin
= Cin(A'B + AB’) + AB(Cin + Cin’)
= Cin(A Xor B) + AB
VERILOG CODES:
1. GATE LEVEL MODELLING:
Module FULL_ADDER(
input A,
input B,
input C,
output S,
output cy,
inout W1,
inout W2,
inout W3);
Xor(W1,A,B);
Xor(S,W1,C);
and(W2,W1,C);
and(W3,A,B);
or(cy,W2,W3);
end module.
2. DATA FLOW MODELLING:
module FullAdder_df(a, b, Cin, S, Cy);
input a, b, Cin;
output S, Cy;
assign S = a ^ b ^ Cin;
assign Cy = (a & b) | (b & Cin) | (a & Cin);
endmodule
3. BEHAVIOURAL MODELLING:
Module full_adder (
input wire a,
input wire b,
input wire cin,
output reg sum,
output reg cout
);
always @(*) begin
sum = a ^ b ^ cin;
cout = (a & b) | (b & cin) | (a & cin);
end
endmodule
SEQUENTIAL CIRCUITS:
1. D FLIPFLOP:
Module dFF(
Input d,
Input dk,
Output q,
);
reg g;
always @ (posedge clk)
Begin
q <= d;
end
end module
2. T FLIPFLOP:
PRELAB QUESTIONS:
1. What Verilog statements is used to describe a design in data flow style?
2. What is Testbench in Verilog?
3. What is a Wire in Verilog?
4. What are the different types of modelling in Verilog?
5. What is the synthesis in VLSI CAD process?
POSTLAB QUESTIONS;
RESULT:
Thus, the simple combinational circuits of Full adder and Sequential circuits of D and
T Flipflop circuits using Verilog is designed and simulated
