INDIAN INSTITUTE OF INFORMATION TECHNOLOGY SENAPATI,

MANIPUR

Department of Electronics & Communication Engineering

VLSI DESIGN LAB

LAB REPORT SUBMITTED

by
Name: SAHILENDRA SHUKLA
Roll Number: 220102009
Section: C

Date of Submission: 30th of October, 2024

INDIAN INSTITUTE OF INFORMATION TECHNOLOGY MANIPUR
DEPARTMENT OF ELETRONICS AND COMMUNICATION
(ECE/ECE VLSI)
EC3152- VLSI DESIGN LAB- FINAL LAB REPORT
SHAILENDRA SHUKLA (220102009)

EXPERIMENT-01
Aim:
To simulate and synthesize all the logic gates using Verilog HDL
Software/Tools required:
Vivado 2024.1
Theory:
AND Gate
An AND gate is a digital logic gate that gives a high (1) output only when all of
its inputs are high (1). The output is low (0) if any input is low (0). The AND
gate implements logical conjunction.
OR Gate
The OR gate outputs a high signal (1) if one or more of its inputs are high (1). It
only produces a low signal (0) if all inputs are low (0). The OR gate performs
the logical disjunction function, meaning "at least one condition must be true."
It is used in circuits where any of several conditions can trigger the output.
NOT Gate
The NOT gate is a unary logic gate that inverts the input signal. If the input is
high (1), the output will be low (0), and if the input is low (0), the output will be
high (1). The NOT gate implements logical negation and is often referred to as
an inverter. It plays a key role in circuits where signal inversion is required.
NAND Gate
The NAND gate combines the functions of an AND gate followed by a NOT gate.
Its output is low (0) only when all inputs are high (1); otherwise, the output is
high (1). The NAND gate implements the negation of logical conjunction,
making it a universal gate. Any logic function can be implemented using only
NAND gates, which is why they are commonly used in digital circuit design.
NOR Gate
The NOR gate performs the OR operation followed by a NOT operation. It gives
a high signal (1) only when all inputs are low (0); otherwise, the output is low
(0). The NOR gate implements the negation of logical disjunction. Like the
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NAND gate, it is also considered a universal gate since any logical function can
be constructed using only NOR gates.
XOR Gate
The XOR (exclusive OR) gate outputs a high signal (1) when an odd number of
inputs are high (1). If both inputs are the same (both low or both high), the
output is low (0). The XOR gate implements logical exclusive disjunction and is
essential in arithmetic circuits, like binary addition, where it is used to detect
differences between inputs.
XNOR Gate
The XNOR (exclusive NOR) gate is the inverse of the XOR gate. It outputs a
high signal (1) when both inputs are the same, either both high (1) or both low
(0). If the inputs differ, the output is low (0). The XNOR gate implements logical
equivalence and is commonly used in circuits that need to check equality
between inputs, such as in digital comparators.
Logic Diagram & Truth table
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Verilog Code:
module logic_gate(a,b,c,d,e,f,g,h,i);
input a,b;
output c,d,e,f,g,h,i;
assign c = a&b;
assign d = a|b;
assign e = ~a;
assign f = ~(a&b);
assign g = a^b;
assign h = ~(a|b);
assign i = ~(a^b);
endmodule
Verilog Test bench:
module testbench();
reg a,b;
wire c,d,e,f,g,h,i;
logic_gate dut(.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g),.h(h),.i(i));
initial
begin
a=0;b=0;
#10 a=1;b=0;
#10 a=0; b=1;
#10 a=1; b=1;
#10 $finish;
end
endmodule
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Output Waveform:

Conclusion:
Output waveform is matched with the truth table.
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EXPERIMENT-02
Aim:
1. Design of Half adder & Full adder.
(a) To design full adder using half adder and simulate the design.
(b) To design full adder using different modeling styles and simulate the design.
Software/Tools required:
Xilinx Vivado 2024.1
Theory:
Adders are fundamental components in digital systems used for performing
arithmetic operations. In this experiment, we will design and simulate two types
of adders: Half Adder and Full Adder. These adders are used to add binary
numbers.
1. Half Adder

A Half Adder is a combinational circuit that adds two binary digits (A

and B) and produces two outputs: the Sum and the Carry. The half
adder does not account for carry input from the previous stage, which
limits its use in multi-bit binary addition.
Boolean Expressions:
• Sum = A ⊕ B (XOR operation)
• Carry = A ⋅ B (AND operation)
Circuit diagram:

Truth table:
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2. Full Adder

A Full Adder is an extension of the half adder. It adds three binary

digits: two inputs (A and B) and a Carry In from the previous addition.
It produces two outputs: the Sum and the Carry Out.
Boolean Expressions:
• Sum = A ⊕ B ⊕ Cin
• Carry Out = (A ⋅ B) + (Cin ⋅ (A ⊕ B))
Circuit diagram:

Truth table
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3. Full Adder using Half Adder

To construct a Full Adder using Half Adders:
• The first Half Adder takes the two significant bits as inputs. It
calculates an intermediate sum and a carry.
• The second Half Adder takes the intermediate sum from the
first Half Adder and the carry-in bit as inputs. It calculates the
final sum and an additional carry.
• The final Carry Out of the Full Adder is obtained by combining
the carry outputs from both Half Adders.
Circuit diagram

Verilog Code:
i. Half Adder
module half_adder(a,b,s,c);
input a,b;
output s,c;
assign s = a^b;
assign c = a&b;
endmodule
ii. Full Adder
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module fulladder1(a,b,Cin,S,Cout);
input a,b,Cin;
output S,Cout;
assign S = (a^b)^Cin;
assign Cout = ((a^b)&Cin)|(a&b);
endmodule
iii. Full Adder using Half Adder
module full_adder(A,B,cin,sum,cout); input A,B,cin;
output cout,sum;
half_adder HA1(.a(A),.b(B),.s(sum_HA1),.c(carry_HA1));
half_adder HA2(.a(sum_HA1),.b(cin),.s(sum),.c(carry_HA2));
assign
cout=carry_HA1&carry_HA2;
endmodule
Verilog Testbench:
i. Half Adder
module tb_halfadder();
reg a,b;
wire s,c;
half_adder dut(.a(a),.b(b),.s(s),.c(c));
initial
begin
a = 0; b = 0;
#10 a = 0; b = 1;

#10 a = 1; b = 0;
#10 a = 1; b = 1;
#10 $finish;
end
endmodule
ii. Full Adder
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module tb_fulladder();
regA,B,cin;
wiresum,cout;
full_adderdut(.A(A),.B(B),.cin(cin),.sum(sum),.cout(cout)); initial
begin
A = 0; B = 0; cin = 0;
#10 A = 0; B = 0; cin = 1;
#10 A = 0; B = 1; cin = 0;
#10 A = 0; B = 1; cin = 1;
#10 A = 1; B = 0; cin = 0;
#10 A = 1; B = 0; cin = 1;
#10 A = 1; B = 1; cin = 0;
#10 A = 1; B = 1; cin = 1;
#10 $finish;
end
endmodule
Output waveform:
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Conclusion:
Output waveform verified is verified with truth table.
INDIAN INSTITUTE OF INFORMATION TECHNOLOGY MANIPUR
DEPARTMENT OF ELETRONICS AND COMMUNICATION
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EC3152- VLSI DESIGN LAB- FINAL LAB REPORT

EXPERIMENT-03
Aim:
Design of 2x4 decoder and simulate the design.

a. To design 2 to 4 decoder using data flow model.

b. To design 2 to 4 decoder using case statement (behavior level)

Software/Tools required:
• Xilinx Vivado 2024.1
Theory:
A 2 to 4 decoder is a combinational logic circuit that converts 2 input lines
into 4 output lines. It enables the selection of one of four outputs based on the
binary value represented by the two inputs. Decoders are essential
components in digital systems, used for data routing, memory selection, and
various other applications where binary information needs to be interpreted .

Circuit diagram:

Truth Table:
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Verilog Code:

i. 2x4 Decoder
module
decoder2to4(a1,a0,d3,d2,d1,d0);
input a1,a0; output d3,d2,d1,d0;
assign d3 = a1&a0; assign d2 =
a1&~a0; assign d1 = ~a1&a0;
assign d0 = ~a1&~a0;
endmodule

Verilog Testbench:

i. 2x4 Decoder using data flow model.

module
tb_decoder2to4();
reg a1,a0; wire
d2,d2,d1,d0;
decoder2to4
dut(.a1(a1),.a0(a0),.d3(d3),.d2(d2),.d1(d1),.d0(d0))
;
initial
begin
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a1 = 0; a0 = 0;
#10 a1 = 0; a0 = 1;
#10 a1 = 1; a0 = 0;
#10 a1 = 1; a0 = 1;
#10 $finish;
end
endmodule

ii. 2x4 Decoder using behavioral model.

module tb_decoder2to4();
reg a1, a0;
wire d3, d2, d1, d0;
decoder2to4 dut(.a1(a1), .a0(a0), .d3(d3), .d2(d2), .d1(d1),
.d0(d0));
initial begin
for (integer i = 0; i < 4; i = i + 1) begin
case (i)
2'b00:
a1 = 0; a0 = 0;
end

2'b01: begin
a1 = 0; a0 = 1;
end
2'b10: begin
a1 = 1; a0 = 0;
end

2'b11: begin
a1 = 1; a0 = 1;
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end
endcase
#10;
end
$finish;
end endmodule
#10 A = 1; B = 1; cin = 1;
#10 $finish;
end endmodule
Output Waveform:

Conclusion:
Output waveform is matched with truth table.
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EXPERIMENT-04
Aim:
Design of 8x3 encoder and simulate the design.
Software/Tools required:
Vivado 2024.1
Theory:
An 8x3 encoder is a combinational logic circuit that compresses 8 input lines
into 3 output lines, reducing the amount of data while preserving the essential
information. Encoders are commonly used in digital systems for data
conversion, such as converting a larger set of signals into a smaller set for more
efficient data handling and processing.

Circuit Diagram:
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Truth table:

Verilog code:
module encoder_83(a,b );
input [7:0] a;
output [2:0] b;
reg [2:0] b;
always @(*) begin
case(a)
8'b00000001: b = 3'b000;
8'b00000010: b = 3'b001;
8'b00000100: b = 3'b010;
8'b00001000: b = 3'b011;
8'b00010000: b = 3'b100;
8'b00100000: b = 3'b101;
8'b01000000: b = 3'b110;
8'b10000000: b = 3'b111;
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default: b = 3'bxxx;
endcase
end
endmodule
Verilog test bench:
module testbench;
reg [7:0] a;
wire [2:0] b;
encoder_83 dut(.a(a),.b(b));
initial
begin

a=8'b00000001; #10;
a=8'b00000010; #10;
a=8'b00000100; #10;
a=8'b00001000; #10;
a=8'b00010000; #10;
a=8'b00100000; #10;
a=8'b01000000; #10;
a=8'b10000000; #10;
a=8'b00000000; #10;
$finish;
end
endmodule
Output Waveform:
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Conclusion:
Output waveform verified with the truth table of 8*3 encoder.
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EXPERIMENT-05
Aim:
Design of 2x1 & 4x1 Multiplexer & Demultiplexer and simulate the design
Software/Tools required:
Xilinx Vivado 2024.1
Theory:
A Multiplexer (MUX) is a combinational circuit that selects one input from
multiple input signals and directs it to a single output line based on the value
of the select lines. Multiplexers are widely used in digital systems to manage
data routing efficiently, as they reduce the need for multiple physical
connections by selecting which input to process or transmit. The number of
select lines determines how many input lines the multiplexer can handle, with
the output being the value of the selected input.
1. 2x1 MUX
A 2-to-1 Multiplexer (2x1 MUX) is a simple digital switch that selects one
of two input signals based on a single select line. It has two inputs (I₀ and I₁),
one select line (S), and one output (Y). Depending on the value of the select
line, the multiplexer routes one of the two inputs to the output.
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2. 4x1 MUX

A 4-to-1 Multiplexer (4x1 MUX) extends the concept of the 2x1 MUX,
allowing the selection of one input from four inputs (I₀, I₁, I₂, I₃) using two
select lines (S₁ and S₀). It has four inputs, two select lines, and one output.
The select lines control which input signal is routed to the output.

Verilog Code:
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i. 2x1 Mux
module mux2to1(a1,a0,s,out); input
a1,a0,s; output out; assign out =
(a1&s)|(a0&~s); endmodule

ii. 4x1 Mux

module mux4_1(a3,a2,a1,a0,s1,s0,out); input a3,a2,a1,a0,s1,s0;
output out; mux2to1 MU1(.a1(a3),.a0(a2),.s(s0),.out(mu1_out));
mux2to1 MU2(.a1(a1),.a0(a0),.s(s0),.out(mu2_out)); mux2to1
MU3(.a1(mu1_out),.a0(mu2_out),.s(s1),.out(out)); endmodule

Verilog Testbench:
i. 2x1 Mux

module tb_mux2to1(); reg a1,a0,s; wire out; mux2to1

dut(.a1(a1),.a0(a0),.s(s),.out(out)); initial begin s = 0;
a1 = 0; a0 = 0; #10 s = 0; a1 = 0; a0 = 1;
#10 s = 0; a1 = 1; a0 = 0;
#10 s = 0; a1 = 1; a0 = 1;
#10 s = 1; a1 = 0; a0 = 0;
#10 s = 1; a1 = 0; a0 = 1;

#10 s = 1; a1 = 1; a0 = 0;
#10 s = 1; a1 = 1; a0 = 1;
#10 $finish; end
endmodule
ii. 4x1 Mux

module tb_mux4_1(); reg

a3,a2,a1,a0,s1,s0; wire out;
mux4_1
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dut(.a3(a3),.a2(a2),.a1(a1),.a0(a0),.s1(s1),.s0(s0),.out(out)); initial begin
a3 = 1'b1; a2 = 1'b0; a1 = 1'b1; a0 = 1'b1; s1 = 0; s0 = 0;

#10 s1 = 0; s0 = 1;
#10 s1 = 1; s0 = 0;
#10 s1 = 1; s0 = 1; #10
$finish; end endmodule

Output Waveform:
i. 2x1 Mux

ii. 4x1 Mux

Conclusion:
Output waveform is verified with truth-table.
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EXPERIMENT-06
Aim:
Design of 8x1 Multiplexer & Demultiplexer.

a. To design and simulate Verilog coding for 8x1 multiplexer using 2x1
multiplexer
b. To design and simulate Verilog coding for 8x1 multiplexer using case/
if else statement (behavior level)
Software/Tools required:
Xilinx Vivado 2024.1
Theory:
1. 8x1 MUX
An 8-to-1 Multiplexer (8x1 MUX) is a digital circuit that selects one of
eight input signals and passes it to the output based on the values of three
select lines. It has eight inputs (I₀, I₁, I₂, I₃, I₄, I₅, I₆, I₇), three select lines
(S₂, S₁, S₀), and one output (Y). The select lines determine which of the eight
inputs will be routed to the output.

Logic Diagram:
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Truth Table:
Inputs Output

S2 S1 S0 Out
0 0 0 A0
0 0 1 A1
0 1 0 A2
0 1 1 A3
1 0 0 A4
1 0 1 A5
1 1 0 A6
1 1 1 A7

2. Demultipler
A Demultiplexer (DEMUX) is a combinational circuit that takes a single
input signal and routes it to one of the many output lines, based on the values
of select lines. The demultiplexer essentially performs the reverse function of
a multiplexer. A 1 to 8 demultiplexer has 1 input, 8 outputs, and 3 select
lines, which determine to which output line the input will be directed.
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Verilog Code:
i. 8x1 MUX
module mux8to1(s2,s1,s0,a7,a6,a5,a4,a3,a2,a1,a0,out); input
s2,s1,s0,a7,a6,a5,a4,a3,a2,a1,a0; output out; mux4_1
MU1(.a3(a0),.a2(a1),.a1(a2),.a0(a3),.s1(s0),.s0(s1),.out(mu1_out
));
mux4_1
MU2(.a3(a4),.a2(a5),.a1(a6),.a0(a7),.s1(s0),.s0(s1),.out(mu2_out
)); mux2to1 MU3(.a1(mu1_out),.a0(mu2_out),.s(s2),.out(out)); endmodule
ii. 1x8 DEMUX
module demux1to8(d,s2,s1,s0,y7,y6,y5,y4,y3,y2,y1,y0); input
d,s2,s1,s0; output y7,y6,y5,y4,y3,y2,y1,y0; demux1to2
DX1(.d(d),.s(s0),.out1(to1),.out2(to2)); demux1to4
DX2(.d(to1),.s1(s1),.s0(s2),.z1(y0),.z2(y1),.z3(y2),.z4(y3)); demux1to4
DX3(.d(to2),.s1(s1),.s0(s2),.z1(y4),.z2(y5),.z3(y6),.z4(y7)); endmodule

Verilog Testbench:
• 8x1 MUX
module tb_8to1(); reg
s2,s1,s0,a7,a6,a5,a4,a3,a2,a1,a0; wire out;

mux8to1
dut(.s2(s2),.s1(s1),.s0(s0),.a7(a7),.a6(a6),.a5(a5),.a4(a4),.a3(
a3),.a2(a2),.a1(a1),.a0(a0),.out(out)); initial begin a0=1'b1; a1=1'b0;
a2=1'b1; a3=1'b0; a4=1'b1; a5=1'b0; a6=1'b1; a7=1'b0; s2 = 0; s1 = 0; s0
= 0; #10 s2 = 0; s1 = 0; s0 = 1;
#10 s2 = 0; s1 = 1; s0 = 0;
#10 s2 = 0; s1 = 1; s0 = 1;
#10 s2 = 1; s1 = 0; s0 = 0;
#10 s2 = 1; s1 = 0; s0 = 1;
#10 s2 = 1; s1 = 1; s0 = 0;
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#10 s2 = 1; s1 = 1; s0 = 1;
#10 $finish; end
endmodule

• 1x8 DEMUX module

tb_1to8demux(); reg
d,s2,s1,s0; wire
y7,y6,y5,y4,y3,y2,y1,y0;
demux1to8
dut(.d(d),.s2(s2),.s1(s1),.s0(s0),.y7(y7),.y6(y6),.y5(y5),.y4(y4
),.y3(y3),.y2(y2),.y1(y1),.y0(y0)); initial
begin d = 1'b1; s2 = 0; s1 = 0; s0
= 0; #10 s2 = 0; s1 = 0; s0 = 1;
#10 s2 = 0; s1 = 1; s0 = 0;
#10 s2 = 0; s1 = 1; s0 = 1;
#10 s2 = 1; s1 = 0; s0 = 0;
#10 s2 = 1; s1 = 0; s0 = 1;
#10 s2 = 1; s1 = 1; s0 = 0;
#10 s2 = 1; s1 = 1; s0 = 1;
#10 $finish; end
endmodule

Output Waveform:

i. 8x1 MUX
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i. 8_1 DEMUX

Conclusion : Output
waveform verified.
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EXPERIMENT-07
Aim:
Design of 4 bit binary to gray converter & Gray to Binary Code Converter using
Verilog and simulate the design.
Software/Tools required:
Vivado 2024.1
Theory:
1. Binary to Gray Code Conversion:
Gray code is a binary numeral system where two successive values differ in only
one bit. A 4-bit Binary to Gray Code Converter is a combinational circuit that
converts 4-bit binary inputs into their corresponding 4-bit Gray code
equivalents.
Gray Code Conversion Rule: To convert a binary number to Gray code:
• The most significant bit (MSB) of the Gray code is the same as the MSB
of the binary number.
• Each subsequent bit of the Gray code is obtained by XORing the
corresponding binary bit and the preceding binary bit.

For a 4-bit binary number B3, B2, B1, B0, the corresponding Gray code G3, G2,
G1, G0 can be found using:

• G3=B3
• G2=B3⊕B2
• G1=B2⊕B1
• G0=B1⊕B0

Where ⊕ denotes the XOR operation.

2. Gray to Binary Code Conversion:

A Gray to Binary Code Converter does the reverse operation of the Binary to
Gray code converter. It converts a 4-bit Gray code into its corresponding 4-bit
binary number.

Binary Code Conversion Rule: To convert Gray code to binary:

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• The most significant bit (MSB) of the binary code is the same as the
MSB of the Gray code.
• Each subsequent binary bit is obtained by XORing the corresponding
Gray bit with the previous binary bit.

For a 4-bit Gray code G3, G2, G1, G0 the corresponding binary code B3, B2, B1,
B0 can be found using:

• B3=G3
• B2=B3⊕G2
• B1=B2⊕G1
• B0=B1⊕G0

Circuit Diagram:
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Truth table:
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Verilog code:
(binary to gray)
module binary_to_gray(a0,a1,a2,a3,g0,g1,g2,g3);
input a0,a1,a2,a3;
output g0,g1,g2,g3;
assign g0 = a0;
assign g1 = a0^a1;
assign g2 = a1^a2;
assign g3 = a2^a3;
endmodule
(gray to binary)
module gray_to_binary(g0,g1,g2,g3,a0,a1,a2,a3);
input g0,g1,g2,g3;
output a0,a1,a2,a3;
assign a0 = g0;

assign a1 = g0^g1;
assign a2 = a1^g2;
assign a3 = a2^g3;
endmodule
Verilog test bench:
(binary to gray)
module testbench();
reg a0,a1,a2,a3;
wire g0,g1,g2,g3;
binary_to_gray dut(.a0(a0),.a1(a1),.a2(a2),.a3(a3),.g0(g0),.g1(g1),.g2(g2),.g3(g3));
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initial
begin
a0=0;a1=0;a2=0;a3=0;
#10 a0=0;a1=0;a2=0;a3=1;
#10 a0=0;a1=0;a2=1;a3=0;
#10 a0=0;a1=0;a2=1;a3=1;
#10 a0=0;a1=1;a2=0;a3=0;
#10 a0=0;a1=1;a2=0;a3=1;
#10 a0=0;a1=1;a2=1;a3=0;
#10 a0=0;a1=1;a2=1;a3=1;
#10 a0=1;a1=0;a2=0;a3=0;
#10 a0=1;a1=0;a2=0;a3=1;
#10 a0=1;a1=0;a2=1;a3=0;
#10 a0=1;a1=0;a2=1;a3=1;
#10 a0=1;a1=1;a2=0;a3=0;
#10 a0=1;a1=1;a2=0;a3=1;
#10 a0=1;a1=1;a2=1;a3=0;
#10 a0=1;a1=1;a2=1;a3=1;
#10 $finish;
end
endmodule
(gray to binary)
module testbench();
reg g0,g1,g2,g3;
wire a0,a1,a2,a3;
gray_to_binary dut(.a0(a0),.a1(a1),.a2(a2),.a3(a3),.g0(g0),.g1(g1),.g2(g2),.g3(g3));
initial
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begin
g0=0;g1=0;g2=0;g3=0;
#10 g0=0;g1=0;g2=0;g3=1;
#10 g0=0;g1=0;g2=1;g3=0;
#10 g0=0;g1=0;g2=1;g3=1;
#10 g0=0;g1=1;g2=0;g3=0;
#10 g0=0;g1=1;g2=0;g3=1;
#10 g0=0;g1=1;g2=1;g3=0;
#10 g0=0;g1=1;g2=1;g3=1;
#10 g0=1;g1=0;g2=0;g3=0;
#10 g0=1;g1=0;g2=0;g3=1;
#10 g0=1;g1=0;g2=1;g3=0;
#10 g0=1;g1=0;g2=1;g3=1;
#10 g0=1;g1=1;g2=0;g3=0;

#10 g0=1;g1=1;g2=0;g3=1;
#10 g0=1;g1=1;g2=1;g3=0;
#10 g0=1;g1=1;g2=1;g3=1;
#10 $finish;
end
endmodule
Output:
(binary to gray)
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(gray to binary)

Conclusion:
Output waveform is verified with the truth table.
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EXPERIMENT-08
Aim:
To design and implement an 8-bit Arithmetic and Logical Unit (ALU) using Verilog.

Software/Tools required:
Xilinx Vivado 2024.1

Theory:
An Arithmetic and Logical Unit (ALU) is a fundamental component in digital systems and
computing devices. It performs arithmetic operations such as addition, subtraction, and
multiplication, as well as logical operations including AND, OR, and NOT. ALUs are
commonly used in processors to execute calculations and make logical decisions. In this
design, an 8-bit ALU takes two 8-bit inputs, A and B, and a 4-bit opcode to specify the
operation to be executed. The ALU produces an 8-bit output and a carry-out bit for
certain arithmetic operations.
Logic Diagram:

Truth Table:
Opcode (4-bit) Operation Description

0000 Addition Sum of A & B

0001 Subtraction Difference of A & B

0010 Multiplication Product of A & B

0011 Logical Shift Left Left Shift A by 1

0100 Logical Shift Right Right Shift A by 1

0101 Rotate Right Rotate A right
0110 Rotate Left Rotate A left
0111 Bitwise AND Bitwise AND of A & B
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1000 Bitwise OR Bitwise OR of A & B
1001 Bitwise NOR Bitwise NOR of A & B

1010 Bitwise NAND Bitwise NAND of A & B

1011 Bitwise XOR Bitwise XOR of A & B

1100 Bitwise XNOR Bitwise XNOR of A & B

1101 A == B Checks if A == B
1110 A<B Checks if A < B
1111 A>B Checks if A > B

Verilog Code:
module alu8b(A, B, y, carry, opcode); input
[7:0] A; input [7:0] B; input [3:0] opcode;
output reg [7:0] y; output reg carry;
always @(*) begin
carry = 0; y=
8'b00000000;
case(opcode)

4'b0000: {carry,y} = A + B;
4'b0001: {carry,y} = A - B;
4'b0010: y = A * B;
4'b0011: y = A << 1;
4'b0100: y = A >> 1;
4'b0101: y = {A[0],A[7:1]};
4'b0110: y = {A[6:0],A[7]};
4'b0111: y = A & B;

4'b1000: y = A | B;
4'b1001: y = A ^ B;
4'b1010: y = ~(A|B);
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4'b1011: y = ~(A&B);
4'b1100: y = ~(A^B);
4'b1101: y = A > B;
4'b1110: y = A == B ;
4'b1111: y = A < B; default: y =
8'b00000000; endcase end
endmodule

Verilog Testbench:

module tb_alu8b(); reg [7:0] A; reg [7:0] B; reg [3:0] opcode; wire
carry; wire [7:0] y; alu8b
dut(.A(A),.B(B),.opcode(opcode),.carry(carry),.y(y)); initial begin A=
8'b01000001; B = 8'b01001011; opcode = 4'b0000; #10 opcode =
4'b0001;
#10 opcode = 4'b0010;
#10 opcode = 4'b0100;
#10 opcode = 4'b0101;
#10 opcode = 4'b0110;
#10 opcode = 4'b0111;
#10 opcode = 4'b1000;
#10 opcode = 4'b1001;
#10 opcode = 4'b1010;
#10 opcode = 4'b1011;
#10 opcode = 4'b1100;
#10 opcode = 4'b1101;

#10 opcode = 4'b1110;

#10 opcode = 4'b1111;
#10 $finish; end
endmodule
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Conclusion:
Output waveform verified.
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EXPERIMENT-09
Aim:
To design, implement, and simulate the Verilog code for SR and D flipflops.
The objective is to understand the behavior and functionality of both flip-
flops, including their response to inputs and their use in storing binary
information based on clock signals.
Software/Tools required:
Xilinx Vivado 2024.1
Theory:
Flip-flops are fundamental sequential circuits in digital electronics, used to
store binary data. They are edge-triggered devices, meaning they capture
and hold input data only on specific clock edges. Among the various types of
flip-flops, the SR (Set-Reset) and D (Data) flip-flops are two of the most

commonly used. Each has unique characteristics, making them suitable for
specific applications in digital systems.

i. SR Flip Flop
The SR (Set-Reset) flip-flop is a basic flip-flop type with two primary inputs:
S (Set) and R (Reset). The SR flip-flop has two stable states (1 and 0) and is
used to store a single bit of data based on the conditions of the S and R
inputs.
Operations:
• When the S (Set) input is high and R is low, the output Q is set to 1.
• When the R (Reset) input is high and S is low, the output Q is reset
to 0.
• When both S and R are low, the output Q retains its previous state
(memory).
• When both S and R are high, the output state is undefined or invalid,
as it causes both Q and its complement Q‾\overline{Q}Q to be 0,
which conflicts with the flip-flop’s logical definition.

Logic Diagram:
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Truth Table:
S R Q (Next State) Qb
0 0 Q (Hold) Qb
0 1 0 1

1 0 1 0
1 1 Invalid Invalid

ii. D Flip Flop

The D (Data or Delay) flip-flop is a simpler and more widely used flip-flop
that has a single data input (D) and a clock input. It is designed to store the
value at the D input only on the rising or falling edge of the clock signal,
depending on its configuration.

Operation:
• The D flip-flop captures the value at the D input and transfers it to the
output Q on the specified clock edge.
• If D = 1 at the clock edge, the output Q is set to 1.
• If D = 0 at the clock edge, the output Q is reset to 0.
• The D flip-flop avoids the indeterminate state issue seen in SR
flipflops by having only one input signal.
Logic Diagram:
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Truth Table:
D CLK Q (Next State) Qb
0 Rising 0 (Reset) 1
1 Rising 1 (Set) 0

Verilog Code:
i. SR Flip Flop
module sr_flip_flop(S,R,CLK,Q,Qb);
input S,R,CLK; output Q,Qb;

assign Q = ~((R&CLK)|Qb); assign Qb =

~((S&CLK)|Q); endmodule
ii. D Flip Flop
module d_flip_flop(D,Db,CLK,Q,Qb); input
D,Db,CLK; output Q,Qb; sr_flip_flop
SR1(D,Db,CLK,Q,Qb); endmodule

Verilog Testbench:

i. SR Flip Flop
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module tb_srflipflop(); reg S,R,CLK; wire Q,Qb; sr_flip_flop
dut(.S(S),.R(R),.CLK(CLK),.Q(Q),.Qb(Qb)); initial begin CLK = 0;
forever #5 CLK = ~CLK; end initial begin S = 0; R = 0;
#10 S = 0; R = 1;
#10 S = 1; R = 0;
#10 S = 1; R = 1;
#10 $finish; end
endmodule

ii. D Flip Flop

module tb_dflipflop(); reg D,Db,CLK; wire Q,Qb; d_flip_flop
DUT(.D(D),.Db(Db),.CLK(CLK),.Q(Q),.Qb(Qb)); initial begin CLK = 0;
forever #5 CLK = ~CLK; end initial begin D = 0; Db = 1;
#10 D = 1; Db = 0;
#10 $finish; end endmodule

Output Waveform:
i. SR Flip Flop

ii. D Flip Flop

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Conclusion:
Output waveform verified with truth table.