Fault Modeling

Outline

l Single Stuck-At Fault Model

l Other Fault Models
l Redundancy and Untestable Faults
l Fault Equivalence and Fault Dominance
l Method of Boolean Difference

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 1 University of Illinois

Fault Modeling
Modeling the effects of physical defects on the logic function
and timing
l Physical Defects l Electrical Effects
♦ Silicon defects
♦ Shorts (0 resistance)
♦ Photolithographic defects
♦ Opens ( resistance)
8

♦ Mask contamination
♦ Transistor stuck-on,
♦ Process variations stuck-open
♦ Defective oxide ♦ Resistive shorts and
opens
♦ Change in threshold
l Logical Effects voltage
♦ Logic s-a-0 or 1
♦ Slower transition (delay faults)
♦ AND-bridging, OR-bridging

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 2 University of Illinois

 Fault Modeling
lPhysical Defect lElectrical
A B

VDD X
B
X
A Z
X
GND X X

lLogical
S-A-0
A
B X Z

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 3 University of Illinois

Causes of Physical Defects

l Manufacture
♦ Mask contamination, dust particles
♦ Fabrication area contamination
l Aging Effects
♦ Metal migration
♦ Oxide degradation due to trapped charge
l Handling
♦ Electrostatic discharge

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 4 University of Illinois

 Single Stuck-At Fault Model
l Why Use Single Stuck-At Fault (SSF) Model?
♦ Complexity is greatly reduced. Many different
physical defects may be modeled by the same
logical stuck-at fault.
♦ SSF is technology independent
s Has been successfully used on TTL, ECL, CMOS,
etc.
♦ Single stuck-at tests cover a large percentage of
multiple stuck-at faults.
♦ Single stuck-at tests cover a large percentage of
unmodeled physical defects.

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 5 University of Illinois

Relationship Between Single and

Multiple Faults
l Irredundant two-level circuit
♦ Complete test for SSF also detects all MSF
[Kohavi and Kohavi, 1972]
l Fanout-free circuit
♦ Any complete test for SSF detects all double
and triple faults [Hayes, 1971]
l Internal fanout-free circuit (fanout > 1 on
primary inputs only)
♦ Any complete test for SSF detects greater than
98% of MSF with 5 or fewer faults [Agarwal and
Fung, 1981]

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 6 University of Illinois

 CMOS Stuck Open Faults
V DD

B Faulty
F Good
Break

l The break in the gate input to transistor T causes it to

remain open

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 7 University of Illinois

CMOS Stuck Open Faults

A B Fgood Ffaulty
0 0 1 1
0 1 0 0
1 0 0 previous F
(floating F)
1 1 0 0

Test Sequence for T stuck-open: A,B = 0, 0 then 1, 0

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 8 University of Illinois

 CMOS Stuck On Faults
l Transistor T1 is always l Observations:
conducting – Correct logic function, but
degraded logic levels
V – Higher signal transition times,
DD
results in a Delay Fault.
Break
A T1 – When A=1, and B=0,
T2
transistors T1, T2, and T3 are
B all conducting resulting in an
F
T4
IDDQ Fault
T3 – If the open is resistive, IDDQ
fault will not happen, but
Delay Fault is very likely

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 9 University of Illinois

IDDQ Faults
l A path that draws current from Vdd to ground

Path from VDD

to GND

A=0
Stuck On
B=0

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 10 University of Illinois

 IDDQ Faults
l Advantages
♦ Covers most bridge faults
♦ Covers some open faults
♦ Higher defect coverage than stuck-at tests
l Disadvantages
♦ Circuit must be designed with low IDDQ
♦ Test application slow
♦ Some open faults escape IDDQ tests
♦ Some timing faults escape IDDQ tests
♦ Current threshold has to be empirically established

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 11 University of Illinois

Bridge Faults
Path from VDD
to GND
A=0
Bridge
D=1
B=0

C=1
E=0
l Simplified Models
n Wired-AND, Wired-OR
l More Realistic Models:
n Bridge resistance
n Vth of successor gates
ECE 443 © Copyright 1998 Elizabeth M. Rudnick 12 University of Illinois
 Transition Faults

l Slow-to-rise (0 to 1) transition l Slow-to-fall (1 to 0) transition

l Requires a two-pattern l Requires a two-pattern

sequence <V1, V2> for a sequence <V1, V2> for a
slow-to-rise fault on line k: slow-to-fall fault on line k:
♦ V1 sets line k to 0 ♦ V1 sets line k to 0
♦ V2 tests fault k stuck-at-0 ♦ V2 tests fault k stuck-at-0

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 13 University of Illinois

Delay Faults
l Model defects that affect the circuit timing (resistive shorts
and opens)
l Transition faults and Gate Delay faults
♦ Models slow-to-rise or slow-to-fall transition on logic gate

l Path Delay Faults (robust and non-robust testing):

♦ Models slow-to-rise or slow-to-fall transition on some
path(s) from primary input to primary outputs
s Advantage: covers transition and gate delay faults

s Disadvantages: test application in non-scan sequential

circuits cannot be done at-speed. Number of paths may be
(exponentially) large

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 14 University of Illinois

 Testing: Structured vs. Unstructured
l UNSTRUCTURED: functional vectors, ATPG vectors
♦ Takes time to get high fault coverage, especially for sequential
designs.
♦ Hard as today’s ASIC designs use embedded logic blocks,
memories etc
s “I did not design the whole chip”

s “With automated synthesis I do not know the details of my logic”

l STRUCTURED: DFT, BIST

♦ Adds additional hardware (increases area)
♦ Trade-off between area and test time

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 15 University of Illinois

Structured Testing: Stuck-at Faults

l Sensitized line for vector t: a line whose logic value is
not correct for vector t in presence of a fault
l Sensitized path for t: a path of sensitized lines

E
l A fault is detectable (testable) if vector t that:

♦ Excites the fault: produces complemented to correct

(faulty) logic value at fault location
AND
♦ Propagates the faulty effect: it produces a sensitized
path to some primary output from faulty location

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 16 University of Illinois

 Testing of Stuck-at Faults
A G/1
D X
F I
B
C H
E

l Fault Excitation: Applying a logic value

opposite to the stuck-at value at the fault site.
l Error Propagation: Applying appropriate logic
values in the circuit to make the error visible at
the primary outputs.
l ABC = 00x is a test vector for G/1 (G s-a-1).
ECE 443 © Copyright 1998 Elizabeth M. Rudnick 17 University of Illinois

Combinational Redundancy
line sensitized
to f

Primary X
Inputs f fault
Primary
Outputs

l Sometimes a fault f on line l cannot be excited or cannot be

propagated or both.
l Then the fault f is termed untestable.
l If the fault f is untestable, then the fault f is redundant, i.e.,
the line l or the associated gate can be removed from the
circuit without changing the logic function.
ECE 443 © Copyright 1998 Elizabeth M. Rudnick 18 University of Illinois
 Untestable Faults
l If a fault f on line l is untestable, then either
the line or the gate can be removed without
changing the function.
s-a-1 1

s-a-0 0 0

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 19 University of Illinois

Why Redundancy Exists

l Unintentional redundancies l Intentional Redundancies
occur due to poorly – Duplicated logic for increase in
optimized designs. This can drive, speed (carry logic)
happen for hand designed or
synthesized circuits – Duplicated logic for error
detection
l Interconnect of synthesized
individually non-redundant – Additional terms for hazard
logic blocks can create global removal
redundancies – Use of overover--designed library
cells, e.g., for a 3-
3-to
to--1 mux
mux,, use
a 4 - to-
to - 1 mux
c F
a
b 0 MUX 0 MUX
1 1
b 2 2
c 3 3

e.g. F = ac + ab + bc Vdd
ECE 443 © Copyright 1998 Elizabeth M. Rudnick 20 University of Illinois
 Other Untestable Fault Classes
s-a -0 1/0 (a) Unobservable
x 1/Z (b) Uncontrollable
1 b
1/? a x
0 x x
Z

TriState Untestable
S-a-0
D
x

D
Sequentially Redundant
Clk

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 21 University of Illinois

Fault Equivalence
l A fault 'a' is equivalent l Fault ‘a’ s-a-0 is
to fault 'b' in the logic equivalent to faults ‘b’
circuit F, if the logic s-a-0 and c s-a-0
function F(a) realized l Equivalence is useful
in the presence of fault in reducing the size of
'a' is identical to the a fault list
logic function F(b) in
presence of fault 'b'. a c
b

For n-input gates, need only to consider n+2 faults.

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 22 University of Illinois

 Method of Structural Equivalence
l Introduce fault f in the network N and reduce
the structure to S(Nf).
l Similarly obtain the structure S(Ng).
l If S(Nf) = S(Ng) then clearly function Nf = N g
and therefore f and g are equivalent faults.
l Structural equivalence implies functional
equivalence.

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 23 University of Illinois

Local Analysis for

Structural Equivalence
equivalent equivalent
s-a-1 s-a-0 s-a-0 not equivalent
X X X s-a-0
s-a-0 s-a-1 X s-a-0
X
equivalent s-a-0
s-a-0 X
s-a-1 equivalent
X
X s-a-0 s-a-0
X
X s-a-1 X X
s-a-1
s-a-1 s-a-1
equivalent
equivalent
l Equivalence classes obtained may not be maximal,
but they are obtained quickly.
ECE 443 © Copyright 1998 Elizabeth M. Rudnick 24 University of Illinois
 Fault Collapsing
l Fault collapsing is the process of retaining only one fault
from each group of equivalent faults
l In the 2-input multiplexer there are 18 single fault sites
l The collapsed list has 10 faults:
– {A1, B1, C0, C1, E1, F1, G0, H0, I0, I1}

A
F
G
I
D E
C
B H
ECE 443 © Copyright 1998 Elizabeth M. Rudnick 25 University of Illinois

Fault Collapsing

ALGORITHM:

♦ Insert all possible s-a-0 and s-a-1 faults on

every line in the circuit
♦ Traverse circuit gates and collapse faults
♦ Easy way: depth=1. Can do for higher depth
(but it can become exponential)

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 26 University of Illinois

 Fault Dominance
l Let TA be the set of all test vectors for fault A
and TB be the set of all test vectors for fault B.
⊃
l Then fault A dominates fault B (written B A)
iff f A = fB for all vectors in TB.
⊃
l It follows that TB TA
♦ A test for B is a test for A. TB TA
♦ If B is tested, then A is tested.
♦ A can be removed.
⊃
l If TB TA then it does not always mean that
the boolean functions fA = fB for vectors in TB.
ECE 443 © Copyright 1998 Elizabeth M. Rudnick 27 University of Illinois

Fault Dominance
{a/0, b/0, c/0, d/0}
a
b d Ta/1 = {011} Tb/1 = {101} Tc/1 = {110}
c
Td/1 = {0xx, x0x, xx0}
d/1 dominates a/1, b/1, and c/1

l No fault equivalence or dominance

relationship exists between a stem and its
fanout branches.
l Dominance does not hold in sequential
circuits.
ECE 443 © Copyright 1998 Elizabeth M. Rudnick 28 University of Illinois
 Boolean Difference
Fault-Free
A I = AC + BC
B
C
(AC + BC)
Faulty
A = (A+C)(B+C)
G/1
B
1 = AB + AC + BC
C
ABC ABC
All test 00X 000
vectors: 0X0 001
X01 010
101
ECE 443 © Copyright 1998 Elizabeth M. Rudnick 29 University of Illinois

Method of Boolean Difference

l Definition: Given a function Z(x1 , x2, ... xn), the
Boolean Difference of Z with respect to xi is
defined as Z(x1, x2, ... xn)x = 0 ⊕ Z(x1, x2 , ... xn)
i xi = 1
l It is often written DZ
dx i
x2
x3
x1
Z = x1(x2+x3) + x1 x4
x4
DZ = Z
dx4 x4 = 0 ⊕ Zx4 = 1 = [x1(x2+x3)] ⊕ [x1(x2+x3) + x1)] = x1

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 30 University of Illinois

 Method of Boolean Difference
l Now consider x4 stuck-at-0. Any test vector
for x4/0 must satisfy Zx4=0 ≠ Z x4=1
l In addition, the test must satisfy x4 = 1.
l Therefore, all test vectors satisfy
DZ x = 1 x1 x4 = 1
dx4 4
(x1, x2, x3 , x4) = (0,-,-,1)

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 31 University of Illinois

Internal Nodes
x2
x3
x1

x4 X
f
l Consider the fault f.
♦ Rewrite Z by cutting the wire at f as a 5-variable
function
s Z(x1, x2, x3, x4, f) = x1(x2+x3) + f

♦ DZ must be 1 for f to propagate to the output

df
♦ Also express f = F(x1, x2, x3, x4) = x1x4
♦ If f is stuck-at-0, the excitation requirement is
F(x1, x2, x3, x4) = 1
ECE 443 © Copyright 1998 Elizabeth M. Rudnick 32 University of Illinois
 Internal Nodes
♦ If f is stuck-at-1 then F(x1, x2, x3, x4) = 0.
♦ Therefore, all test vectors are expressed by the
equation
DZ f = 1 for f stuck-at-0
s
df
s DZ f = 1 for f stuck-at-1
df
DZ
♦ df = x1(x2+x3) ⊕ 1 = x1 + x2x3
♦ Tests for f stuck-at-0 are
s x1 x4 [x1+x2 x3)] = x1x4

ECE 443 © Copyright 1998 Elizabeth M. Rudnick 33 University of Illinois