PCI-XP DATA LINK LAYER TRANSMIT PROTOCAL

A
PROJECT REPORT
ON
PCI-XP DATA LINK LAYER TRANSMIT PROTOCAL

SUBMITTED BY

G.KISHORE REDDY

( 07J31A0433)

CONTENTS:

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 Abstract
 Introduction
 PCI-Express Layered Architecture
 Functions of the Data Link Layer
 Bus Topology
 PCI-Express Data Link Layer Transmit Protocol Architecture
 Features of PCI Express
 Applications
 Summary
 conclusion

ABSTRACT:

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 The project deals with the design of Data Link Layer Transmit Protocol, which acts as an intermediate stage between
the Transaction Layer and Physical Layer.

 Its primary responsibility is to provide a reliable mechanism for exchanging transaction packets between the two
components on a link.

 The whole PCI-Express Transmit system will be integrated and simulated using Active HDL

 The synthesis for PCI-Express Data Link Layer Transmit protocol architecture will be performed using Xilinx
Synthesis Tool.

 The various blocks will be simulated and the functionality of each block will be verified with the help of test benches.

INTRODUCTION:

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 PCI stands for “Peripheral Component Interconnect”

 Bus is a collection of wires through which data is transmitted from one part of a computer to another

 PCI Express is the third generation high performance I/O bus used to interconnect peripheral devices in applications such as
computing and communication platforms

 PCI Express supports chip-to-chip interconnect and board-to-board interconnect via cards and connectors

 PCI Express implements a serial, point-to-point type interconnects for communication between two devices

 PCI Express implements switch based technology to interconnect a large number of devices
 PCI Express provides Quality of service feature, which provides differentiated transmission performance for different
applications
 PCI devices are designed to detect address and data phase parity errors during transactions
 A PCI Express interconnect that connects two devices together is referred to as a link these signals are referred to as lanes

PCI-Express Layered Architecture:

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The PCI Express specification defines a layered architecture for device design as shown. The layer consists of a Transaction
layer, a Data link layer and a Physical layer. The layers can be further divided vertically into two, a transmit portion that processes
outbound traffic and a receive portion that processes inbound traffic.

PCI Express Device A PCI Express Device B

Device Core
Device Core

PCI Express Core PCI Express Core

Transaction Layer
Transaction Layer

Data Link Layer Data Link Layer

Physical Layer Physical Layer

Link

PCI Express Layered Architecture

Transmit portion of Device Layers:

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 The transmit portion of a device. Packet contents are formed in the Transaction layer with information obtained from
the device core and application. This packet is referred to as a Transaction layer packet (TLP).
 The Data link layer concatenates to the packet additional information required for error checking at a receiver device.
The packet is then encoded in the Physical layer and transmitted differentially on the link by the analog portion of this
layer.

Device Layers and their Associated Packets:

 PCI Express transactions employ TLP’s, which originate at the Transaction layer of a transmitter device and terminate
at the Transaction layer of a receiver device.

Device Core/Software Layer:

 The device core logic in conjunction with local software provides the necessary information required by the PCI
Express device to generate TLP’s. This information is sent via the transmit interface to the Transaction layer of the
device.
 The device core is also responsible to receive information sent by the transaction layer via the receive interface.
 This information includes: type of TLP received by the Transaction layer, address, amount of data received, data and
traffic class of received TLP, message index, error conditions etc.

Transaction Layer:
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 The Transaction Layer is responsible for generation of outbound TLP traffic and reception of inbound TLP traffic.
 The Transaction Layer contains virtual channel buffers to store outbound TLPs that await transmission and also to store
inbound TLPs received from the Link.
 The Transaction Layer on the transmit side receives information receives information from the Device Core and
generates outbound request and completion TLPs which it stores in virtual channel buffers.
 The major components of a TLP are: Header, Data Payload and an optional ECRC as shown in table.

Header Data Payload ECRC

3-4 DW 0-1024 DW 1DW

TLP Structure at the Transaction Layer

 The Header is 3 double or 4 double words in size and may include information such as; Address, TLP type, transfer size,
requester ID/completer ID, tag, traffic class, byte enables, completion codes and attributes.
 The address is a 32-bit memory address or an extended 64-bit address for memory requests. It is a 32-bit address for IO
requests.
 The transfer size or length field indicates the amount of data to transfer calculated in double words.
 The data transfer length can be between 1 to 1024DWs. A bit in the Header indicates whether this packet contains an
ECRC field also referred to as digest.
 This field is 32-bits wide and contains an End-to-End CRC.Th ECRC field is generated by Transaction Layer at time of
creation of the outbound TLP.
 The Transaction Layer on the receive side stores the inbound TLPs in receiver virtual channel buffers.

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 The receiver checks for CRC errors based on the ECRC field in the TLP. If there are no errors, the ECRC field is stripped
and the resultant information in the TLP headers as well as the data payload is sent to the Device Core.

Physical Layer:

 The Physical layer is divided in two portions, the Logical Physical Layer and Electrical Physical layer.
 The Logical Physical layer contains digital logic associated with processing packets before transmission on the Link, or
processing packets inbound from the link before sending to the data link layer.
 The Electrical Physical layer is the analog interface of the Physical layer that connects to the Link.
 Both TLP and DLLP type packets are sent from the Data Link Layer to the Physical layer for transmission over the
Link. On the transmit side the Physical layer frames the TLP or DLLP with a Start and End character .S

Start Sequence Header Data Payload ECRC LCRC End

1B 2B 3-4 DW 0-1024 DW 1 DW 1 DW 1B

TLP Structure at the Physical Layer

Star DLLP Type Misc CRC End

t

1B 1 DW 1 DW 2B 1B

DLLP Structure at the Physical Layer

 The Start symbol is a framing code byte, which a receiver device uses to detect the start and end of a packet. Each byte
of a packet is then scrambled with the aid of Linear Feedback Shift register type scrambler.
 The resultant bytes are encoded into a 10b code by the 8b/10b encoding logic.

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 The primary purpose of encoding 8b characters to 10bsymbols is to create sufficient 1-to-0 and 0-to1 transition density
in the bit stream to facilitate recreation of a receive clock with the aid of a PLL at the remote receiver device.
 On the receive side Electrical Physical Layer clocks in a packet arriving differentially on all lanes.
 The serial bit stream of the packet is converted into a 10b parallel stream using the serial-to-parallel converter. The 10b
symbol stream is decoded back to 8b representation of each symbol with the 8b/10b decoder.

Data Link Layer:

 The Data Link Layer on transmit side is responsible for TLP CRC generation and TLP error checking. For
outbound TLPs from transmit Device A, a Link CRC and a sequence ID is appended to the TLP. Device A’s Data
Link Layer preserves a copy of the TLP in a replay buffer and transmits the TLP to Device B.
 The Data Link Layer of the remote Device B receives the TLP and checks for CRC errors.

Functions of the Data Link Layer:

Data Exchange:

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Passing TLPs from the transaction layer to the physical layer in the transmit side and passing the TLPs from the physical
layer to the transaction layer as needed in the receive side.

Error Detection:

Calculates a Link to Link CRC for the TLPs coming from the transaction layer and appended to the TLP at the end on the
transmit side. While on the receive side checks for the LCRC error by detaching the LCRC field from the TLP coming from the
physical layer and reports the error condition to the transaction layer.

Maintaining order of TLPs:

Each TLP from the transaction layer is appended a packet number before passing to the physical layer at the transmit side and
at the receive side this number is detached while passing the TLP from the physical layer to the transaction layer. This numbering
mechanism preserves the order of the TLPs.

Power management and Interfacing:

Data link layer logic tracks the physical layer status and reports to the transaction layer whether the physical link connected,
disabled or Disconnected in the low power state so that the higher layer seize the transfer of TLPs until the data link layer reports the
normal active link status.

Flow Control Initialization:

Flow control mechanism is performed at the transaction layer to track the receive buffer size for proper buffering of TLPs.

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Data Link Layer Packet (DLLP) Formats:

To perform the above-mentioned functions, the data link layer logic at the transmit side of one device and at the receive side of
another device exchanged special type of packets called DLLPs which is local traffic and is not routed. There are broadly three types
of packets: Data Integrity DLLPs, Power management DLLPs and Flow control DLLPs.

All the DLLPs are 6 bytes or 48-bit in length, they have similar packet format and the general DLLP format is given and
explained below.

Byte0 Byte1 Byte2 Byte3 Byte4 Byte5

DLLP Data in these bytes varies by DLLP type 16 bit CRC

Type

General DLLP Format

Bus Topology:

PCI and PCI -X buses are multidrop parallel interconnect buses in which many devices share one bus. It consists of centralized bus
arbitration mechanism.

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Device A Device B Device C Device D

PCI Express implements a serial point-
to-point interconnect for communication between devices.

Bus Architecture:

PCI bus architecture consists of PCI master/initiator, PCI slave/target, and PCI arbiter. Whenever a PCI bus master requires the
use of PCI bus to perform the transaction it must request the PCI bus from PCI arbiter and when PCI arbiter grants the bus, the bus
master acquires ownership of the PCI bus and initiates the transactions. The PCI bus master/initiator has to wait until arbiter grants the
ownership.

Error handling and reporting:

PCI error detection and reporting is not robust, their exists two types of errors, address and data phase parity errors. PCI errors
are fatal uncorrectable errors that many times result in system shut down.

Interrupt handling:

PCI bus architecture has poor interrupt handling mechanism. Multiple devices share a common interrupts signal INTX.PCI
devices uses four-interrupt signal to trigger an interrupt request to the interrupt controller.

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Interrupt controller asserts INTR to CPU and then CPU determines the source of interrupt saves its state and services the
device that generated the interrupt.

Data Transfer:

In PCI, most of the data transfers are accomplished using burst transfers. A burst transfers consists of single address phase
followed by two or more data phases. PCI-Express follow a packet base protocol –address, data and control information framed in a
standard form called packet and passed on to the link bit by bit serially. The advantage with the packet-based protocol is data integrity.

PCI-Express Data Link Layer Transmit Protocol Architecture :

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Features of PCI Express:

1. The Link-A Point-to-Point Interconnect:

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A PCI Express consists of either a x1, x2, x4, x8, x12, x16 or x32 point-to-point Link. A PCI Express link is the physical
connection between two devices. A lane consists of signal pairs in each direction.

2. Switches are used to interconnect multiple devices:

Switches are implemented in systems requiring multiple devices to be interconnected. Switches can range from a 2-port device
to an n-port device, where each port connects to a PCI Express link.

3. Address Space:

PCI Express supports the same address space as PCI memory, I/O, and configuration address spaces. Maximum address space
per device function is extended from 256 bytes to 4 Kbytes.

4. Packet based protocol:

PCI Express encodes transactions using a packet-based protocol. Packets are transmitted and received serially and byte striped
across the available lanes of the Link.

5. Error handling and robustness of data transfer:

CRC fields are embedded within each packet transmitted. One of the CRC fields supports a link level CRC error checking
protocol whereby each receiver of a packet checks for link level CRC errors.

6. Quality of Service:

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The Quality of Service feature of PCI Express refers to the capability of routing of packets from different applications through
the fabric with differentiated priorities and deterministic latencies and bandwidth.

7. Interrupt handling:

PCI Express follows MSI Style of Interrupt handling.

8. Root Complex:

The root complex denotes the device that connects the CPU and memory subsystem to the PCI Express fabric. It may support
one or more PCI Express ports. Each port is connected to an endpoint device or a switch, which forms a sub-hierarchy. The root
complex generates transaction requests on the behalf of the CPU. It is capable of initiating configuration transaction requests on the
behalf the CPU.

9. Switches:

A Switch can be thought of as consisting of two or more logical PCI-to-PCI bridges, each bridge associated with a switch port.
A Switch forwards packet in a manner similar to PCI bridges using memory, I/O or configuration address based routing. Switches
must forward these packets based on one of three routing mechanisms: address routing, ID routing or implicit routing.

10. Endpoint devices:

Endpoints are devices other than root complex and switches that are requesters or completers PCI Express transactions. They are
peripheral devices such as Ethernet, USB or graphics devices.

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APPLICATIONS:
 Motherboard To peripherals data transmission

 Chip-to-chip interconnect

 Board-to-board interconnect via cards and connectors

 PCI Express provides RAS (Reliable, Available, and Serviceable) error handling features make PCI Express suitable for robust
high-end server applications.
 Hot plug, power management, error handling and interrupt signaling are accomplished in-band using packet based messaging
rather than side band signals. This keeps the device pin count low and reduces system cost.

SUMMARY:

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 PCI Express advances overall platform capabilities while preserving PCI architecture and software investments
 Layered approach and scaleable features provide a foundation for technology stability
 New capabilities enable important emerging applications
 Legacy software compatibility and transition strategy to PCI Express aware software environment must be considered at all
times
 MSI/MSI-X instead of MSI when multiple vectors are merited
 Firmware plays key role in enabling new PCI Express

CONCLUSION:

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 The PCI Express architects have carried forward the most beneficial features from previous generation bus architectures
and have also taken advantages of new developments in computer architecture.
 PCI Express employs the same usage model and load store communication model as PCI and PCI-X.
 The memory input and configuration address space model is the same as PCI and PCI-X address spaces. Like predecessor
buses, PCI Express supports chip-to-chip interconnect and board-to-board interconnect via cards and connectors.
 Hence the PCI-xp code is been simulated and verified by synthesis support .

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