FINAL

Am27C2048
2 Megabit (128 K x 16-Bit) CMOS EPROM

DISTINCTIVE CHARACTERISTICS
■ Fast access time ■ ±10% power supply tolerance standard
— Speed options as fast as 55 ns ■ 100% Flashrite programming
■ Low power consumption — Typical programming time of 16 seconds
— 100 µA maximum CMOS standby current ■ Latch-up protected to 100 mA from –1 V to
■ JEDEC-approved pinout VCC + 1 V
— Plug-in upgrade of 1 Mbit EPROM ■ Versatile features for simple interfacing
— 40-pin DIP/PDIP — Both CMOS and TTL input/output compatibility
— 44-pin PLCC — Two line control functions
■ Single +5 V power supply ■ High noise immunity

GENERAL DESCRIPTION
The Am27C2048 is a 2 Mbit, ultraviolet erasable pro- thus eliminating bus contention in a multiple bus micro-
grammable read-only memory. It is organized as 128 K processor system.
words, operates from a single +5 V supply, has a static
AMD’s CMOS process technology provides high
standby mode, and features fast single address loca-
speed, low power, and high noise immunity. Typical
tion programming. The Am27C2048 is ideal for use in
power consumption is only 125 mW in active mode,
16-bit microprocessor systems. The device is available
and 100 µW in standby mode.
in windowed ceramic DIP packages, and plastic one
time programmable (OTP) PDIP and PLCC packages. All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in
Data can be typically accessed in less than 55 ns, al-
blocks, or at random. The device supports AMD’s
lowing high-performance microprocessors to operate
Flashrite programming algorithm (100 µs pulses), re-
without any WAIT states. The device offers separate
sulting in a typical programming time of 16 seconds.
Output Enable (OE#) and Chip Enable (CE#) controls,

BLOCK DIAGRAM
VCC Data Outputs
DQ0–DQ15
VSS
VPP

OE# Output Enable

Chip Enable Output
CE# and Buffers
PGM# Prog Logic

Y Y
Decoder Gating

A0–A16
Address
Inputs X 2,097,152
Decoder Bit Cell
Matrix

11407G-1

Publication# 11407 Rev: G Amendment/0

Issue Date: May 1998
PRODUCT SELECTOR GUIDE
Family Part Number Am27C2048

VCC = 5.0 V ± 5% -55 -255

Speed Options
VCC = 5.0 V ± 10% -55 -70 -90 -120 -150 -200

Max Access Time (ns) 55 70 90 120 150 200 250

CE# (E#) Access (ns) 55 70 90 120 150 200 250

OE# (G#) Access (ns) 40 40 40 50 65 75 75

CONNECTION DIAGRAMS
Top View
DIP PLCC

DU (Note 2)

PGM# (P#)
VPP 1 40 VCC

CE (E)
DQ13
DQ14
DQ15
CE# (E#) 2 39 PGM# (P#)

VCC

A16
A15
A14
VPP
DQ15 3 38 A16
DQ14 4 37 A15 6 5 4 3 2 1 44 43 42 41 40
DQ13 5 36 A14
DQ12 7 39 A13
DQ12 6 35 A13
DQ11 8 38 A12
DQ11 7 34 A12
DQ10 9 37 A11
DQ10 8 33 A11
DQ9 10 36 A10
DQ9 9 32 A10
DQ8 11 35 A9
DQ8 10 31 A9
VSS 12 34 VSS
VSS 11 30 VSS
NC 13 33 NC
DQ7 12 29 A8
DQ7 14 32 A8
DQ6 13 28 A7
27
DQ6 15 31 A7
DQ5 14 A6
DQ4 15 26 A5
DQ5 16 30 A6

DQ3 16 25 A4 DQ4 17 29 A5
18 19 20 21 22 23 24 25 26 27 28
DQ2 17 24 A3
DQ3
DQ2
DQ1
DQ0
OE# (G#)
DU (Note 2)
A0
A1
A2
A3
A4
DQ1 18 23 A2
DQ0 19 22 A1
OE# (G#) 20 21 A0
11407G-2 11407G-3

Notes:
1. JEDEC nomenclature is in parenthesis.
2. Don’t use (DU) for PLCC.

PIN DESIGNATIONS LOGIC SYMBOL

A0–A16 = Address Inputs
CE# (E#) = Chip Enable Input
17
DQ0–DQ15 = Data Input/Outputs
A0–A16 16
OE# (G#) = Output Enable Input
DQ0–DQ15
PGM# (P#) = Program Enable Input
CE# (E#)
VCC = VCC Supply Voltage
PMG (P#)
VPP = Program Voltage Input OE# (G#)
VSS = Ground
11407G-4

2 Am27C2048
ORDERING INFORMATION
UV EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the following:

AM27C2048 -55 D C 5 B

OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-In

VOLTAGE TOLERANCE
5 = VCC ± 5%, 55 ns only
See Product Selector Guide and Valid Combinations

TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)

PACKAGE TYPE
D = 40-Pin Ceramic DIP (CDV040)

SPEED OPTION
See Product Selector Guide and
Valid Combinations

DEVICE NUMBER/DESCRIPTION
Am27C2048
2 Megabit (128 K x 16-Bit) CMOS UV EPROM

Valid Combinations Valid Combinations

Valid Combinations list configurations planned to be sup-
AM27C2048-55 ported in volume for this device. Consult the local AMD sales
DC5, DC5B, DI5, DI5B
VCC = 5.0 V ± 5% office to confirm availability of specific valid combinations and
AM27C2048-55 to check on newly released combinations.
VCC = 5.0 V ± 10%
DC, DCB, DI, DIB
AM27C2048-70

AM27C2048-90

AM27C2048-120

AM27C2048-150 DC, DCB, DE, DEB, DI, DIB

AM27C2048-200

AM27C2048-255
DC, DCB, DI, DIB
VCC = 5.0 V ± 5%

Am27C2048 3
ORDERING INFORMATION
OTP EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the following:

AM27C2048 -55 J C 5

OPTIONAL PROCESSING
Blank = Standard Processing

VOLTAGE TOLERANCE
5 = VCC ± 5%, -55 ns only
See Product Selector Guide and
Valid Combinations

TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)

PACKAGE TYPE
P = 40-Pin Plastic DIP (PD 040)
J = 44-Pin Square Plastic Leaded Chip Carrier (PL 044)

SPEED OPTION
See Product Selector Guide and
Valid Combinations

DEVICE NUMBER/DESCRIPTION
Am27C2048
2 Megabit (128 K x 16-Bit) CMOS OTP EPROM

Valid Combinations Valid Combinations

Valid Combinations list configurations planned to be sup-
AM27C2048-55 ported in volume for this device. Consult the local AMD sales
PC5, PI5, JC5, JI5
VCC = 5.0 V ± 5% office to confirm availability of specific valid combinations and
AM27C2048-55 to check on newly released combinations.
VCC = 5.0 V ± 10%

AM27C2048-70

AM27C2048-90

AM27C2048-120 PC, PI, JC, JI

AM27C2048-150

AM27C2048-200

AM27C2048-255
VCC = 5.0 V ± 5%

4 Am27C2048
FUNCTIONAL DESCRIPTION
Device Erasure that particular device. A high-level CE# input inhibits
the other devices from being programmed.
In order to clear all locations of their programmed con-
tents, the device must be exposed to an ultraviolet light Program Verify
source. A dosage of 15 W seconds/cm2 is required to
A verification should be performed on the programmed
completely erase the device. This dosage can be ob-
bits to determine that they were correctly programmed.
tained by exposure to an ultraviolet lamp—wavelength
The verify should be performed with OE# and CE#, at
of 2537 Å—with intensity of 12,000 µW/cm2 for 15 to 20
VIL, PGM# at VIH, and VPP between 12.5 V and 13.0 V.
minutes. The device should be directly under and about
one inch from the source, and all filters should be re- Autoselect Mode
moved from the UV light source prior to erasure.
The autoselect mode provides manufacturer and de-
Note that all UV erasable devices will erase with light vice identification through identifier codes on DQ0–
sources having wavelengths shorter than 4000 Å, such DQ7. This mode is primarily intended for programming
as fluorescent light and sunlight. Although the erasure equipment to automatically match a device to be pro-
process happens over a much longer time period, ex- grammed with its corresponding programming algo-
posure to any light source should be prevented for rithm. This mode is functional in the 25°C ± 5°C
maximum system reliability. Simply cover the package ambient temperature range that is required when pro-
window with an opaque label or substance. gramming the device.
Device Programming To activate this mode, the programming equipment
must force VH on address line A9. Two identifier bytes
Upon delivery, or after each erasure, the device has
may then be sequenced from the device outputs by tog-
all of its bits in the “ONE”, or HIGH state. “ZEROs” are
gling address line A0 from VIL to VIH (that is, changing
loaded into the device through the programming pro-
the address from 00h to 01h). All other address lines
cedure.
must be held at VIL during the autoselect mode.
The device enters the programming mode when 12.75
Byte 0 (A0 = VIL) represents the manufacturer code,
V ± 0.25 V is applied to the VPP pin, and CE# and
and Byte 1 (A0 = VIH), the device identifier code. Both
PGM# are at VIL.
codes have odd parity, with DQ7 as the parity bit.
For programming, the data to be programmed is ap-
plied 16 bits in parallel to the data pins. Read Mode
To obtain data at the device outputs, Chip Enable (CE#)
The flowchart in the Programming section (Section 5,
and Output Enable (OE#) must be driven low. CE# con-
Figure 5-1) shows AMD’s Flashrite algorithm. The
trols the power to the device and is typically used to se-
Flashrite algorithm reduces programming time by using
lect the device. OE# enables the device to output data,
a 100 µs programming pulse and by giving each address
independent of device selection. Addresses must be
only as many pulses to reliably program the data. After
stable for at least tACC –tOE. Refer to the Switching
each pulse is applied to a given address, the data in that
Waveforms section for the timing diagram.
address is verified. If the data does not verify, additional
pulses are given until it verifies or the maximum pulses Standby Mode
allowed is reached. This process is repeated while se-
The device enters the CMOS standby mode when CE#
quencing through each address of the device. This part
is at VCC ± 0.3 V. Maximum VCC current is reduced to
of the algorithm is done at VCC = 6.25 V to assure that
100 µA. The device enters the TTL-standby mode
each EPROM bit is programmed to a sufficiently high
when CE# is at VIH. Maximum VCC current is reduced
threshold voltage. After the final address is completed,
to 1.0 mA. When in either standby mode, the device
the entire EPROM memory is verified at VCC = VPP =
places its outputs in a high-impedance state, indepen-
5.25 V.
dent of the OE# input.
Please refer to Section 5 for additional programming in-
formation and specifications. Output OR-Tieing
To accommodate multiple memory connections, a
Program Inhibit two-line control function provides:
Programming different data to multiple devices in par-
■ low memory power dissipation, and
allel is easily accomplished. Except for CE#, all like in-
puts of the devices may be common. A TTL low-level ■ assurance that output bus contention will not occur.
program pulse applied to one device’s CE# input with CE# should be decoded and used as the primary de-
VPP = 12.75 V ± 0.25 V and PGM# LOW will program vice-selecting function, while OE# be made a common
connection to all devices in the array and connected to

Am27C2048 5
the READ line from the system control bus. This as- put capacitance loading of the device. At a minimum, a
sures that all deselected memory devices are in their 0.1 µF ceramic capacitor (high frequency, low inherent
low-power standby mode and that the output pins are inductance) should be used on each device between
only active when data is desired from a particular mem- VCC and VSS to minimize transient effects. In addition,
ory device. to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM ar-
System Applications rays, a 4.7 µF bulk electrolytic capacitor should be used
During the switch between active and standby condi- between VCC and VSS for each eight devices. The loca-
tions, transient current peaks are produced on the ris- tion of the capacitor should be close to where the
ing and falling edges of Chip Enable. The magnitude of power supply is connected to the array.
these transient current peaks is dependent on the out-

MODE SELECT TABLE

Mode CE# OE# PGM# A0 A9 VPP Outputs

Read VIL VIL X X X X DOUT

Output Disable VIL VIH X X X X High Z

Standby (TTL) VIH X X X X X High Z

Standby (CMOS) VCC ± 0.3 V X X X X X High Z

Program VIL X VIL X X VPP DIN

Program Verify VIL VIL VIH X X VPP DOUT

Program Inhibit VIH X X X X VPP High Z

Autoselect Manufacturer Code VIL VIL X VIL VH X 01h

(Note 3) Device Code VIL VIL X VIH VH X 98h

Notes:
1. VH = 12.0 V ± 0.5 V.
2. X = Either VIH or VIL.
3. A1–A8 and A10–16 = VIL.
4. See DC Programming Characteristics for VPP voltage during programming.

6 Am27C2048
ABSOLUTE MAXIMUM RATINGS OPERATING RANGES
Storage Temperature Commercial (C) Devices
OTP Products. . . . . . . . . . . . . . . . . . –65°C to +125°C Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°C
All Other Products . . . . . . . . . . . . . . –65°C to +150°C
Industrial (I) Devices
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C

Voltage with Respect to VSS Extended (E) Devices

All pins except A9, VPP, VCC . . –0.6 V to VCC + 0.6 V Ambient Temperature (TA) . . . . . . . .–55°C to +125°C
A9 and VPP (Note 2) . . . . . . . . . . . . . –0.6 V to 13.5 V Supply Read Voltages
VCC (Note 1). . . . . . . . . . . . . . . . . . . . . –0.6 V to 7.0 V VCC for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V
Notes: VCC for ± 10% devices . . . . . . . . . +4.50 V to +5.50 V
1. Minimum DC voltage on input or I/O pins –0.5 V. During Operating ranges define those limits between which the func-
voltage transitions, the input may overshoot VSS to –2.0 V tionality of the device is guaranteed.
for periods of up to 20 ns. Maximum DC voltage on input
and I/O pins is VCC + 5 V. During voltage transitions, input
and I/O pins may overshoot to VCC + 2.0 V for periods up
to 20 ns.
2. Minimum DC input voltage on A9 is –0.5 V. During voltage
transitions, A9 and VPP may overshoot VSS to –2.0 V for
periods of up to 20 ns. A9 and VPP must not exceed+13.5
V at any time.
Stresses above those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure of
the device to absolute maximum ratings for extended periods
may affect device reliability.

Am27C2048 7
DC CHARACTERISTICS OVER OPERATING RANGE
(unless otherwise specified)
Parameter
Symbol Parameter Description Test Conditions Min Max Unit

VOH Output HIGH Voltage IOH = –400 µA 2.4 V

VOL Output LOW Voltage IOL = 2.1 mA 0.45 V

VIH Input HIGH Voltage 2.0 VCC + 0.5 V

VIL Input LOW Voltage –0.5 +0.8 V

ILI Input Load Current VIN = 0 V to VCC C/I Devices 1.0 µA

E Devices 5.0

ILO Output Leakage Current VOUT = 0 V to VCC 5.0 µA

ICC1 VCC Active Current (Note 2) CE# = VIL, f = 5 MHz, C/I Devices 50
mA
IOUT = 0 mA E Devices 60

ICC2 VCC TTL Standby Current CE# = VIH 1.0 mA

ICC3 VCC CMOS Standby Current CE# = VCC ± 0.3 V 100 µA

IPP1 VPP Supply Current (Read) CE# = OE# = VIL, VPP = VCC 100 µA

Caution: The device must not be removed from (or inserted into) a socket when VCC or VPP is applied.
Notes:
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP..
2. ICC1 is tested with OE# = VIH to simulate open outputs.
3. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.
Maximum DC Voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns.

35 35

30 30
Supply Current

Supply Current
in mA

in mA

25 25

20 20

15 15
1 2 3 4 5 6 7 8 9 10 –75 –50 –55 0 25 50 75 100 125 150
Frequency in MHz Temperature in °C

11407G-5 11407G-6

Figure 1. Typical Supply Current vs. Frequency Figure 2. Typical Supply Current vs. Temperature
VCC = 5.5 V, T = 25°C VCC = 5.5 V, f = 5 MHz

8 Am27C2048
TEST CONDITIONS

5.0 V Table 1. Test Specifications

All
2.7 kΩ Test Condition -55 others Unit
Device
Under Output Load 1 TTL gate
Test
Output Load Capacitance, CL
CL 6.2 kΩ 30 100 pF
(including jig capacitance)

Input Rise and Fall Times ≤ 20 ns

Input Pulse Levels 0.0–3.0 0.45–2.4 V

Input timing measurement

Note: 1.5 0.8, 2.0 V
reference levels
Diodes are IN3064 or equivalents.
Output timing measurement
1.5 0.8, 2.0 V
11407G-7
reference levels

Figure 3. Test Setup

SWITCHING TEST WAVEFORM

3V 2.4 V
2.0 V 2.0 V

1.5 V Test Points 1.5 V Test Points

0.8 V 0.8 V
0V 0.45 V
Input Output Input Output

Note: For CL = 30 pF. Note: For CL = 100 pF.

11407G-8

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

KS000010-PAL

Am27C2048 9
AC CHARACTERISTICS
Parameter Symbols Am27C2048

JEDEC Standard Description Test Setup -55 -70 -90 -120 -150 -200 -255 Unit

CE#,
tAVQV tACC Address to Output Delay Max 55 70 90 120 150 200 250 ns
OE# = VIL

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 55 70 90 120 150 200 250 ns

tGLQV tOE Output Enable to Output Delay CE# = VIL Max 40 40 40 50 65 75 75 ns

Chip Enable High or Output

tEHQZ tDF
Enable High to Output High Z, Max 25 25 25 30 30 40 60 ns
tGHQZ (Note 2)
Whichever Occurs First

Output Hold Time from

tAXQX tOH Addresses, CE# or OE#, Min 0 0 0 0 0 0 0 ns
Whichever Occurs First

Caution: Do not remove the device from (or insert it into) a socket or board that has VPP or VCC applied.
Notes:
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.
2. This parameter is sampled and not 100% tested.
3. Switching characteristics are over operating range, unless otherwise specified.
4. See Figure 3 and Table 1 for test specifications.

SWITCHING WAVEFORMS
2.4
Addresses 2.0 2.0
Addresses Valid
0.8 0.8
0.45

CE#
tCE

OE#
tDF (Note 2)
tOE
tACC tOH
(Note 1)
High Z High Z
Output Valid Output
11407G-9

Notes:
1. OE# may be delayed up to tACC – tOE after the falling edge of the addresses without impact on tACC.
2. tDF is specified from OE# or CE#, whichever occurs first.

PACKAGE CAPACITANCE
CDV040 PD 040 PL 044
Parameter Parameter
Symbol Description Test Conditions Typ Max Typ Max Typ Max Unit

CIN Input Capacitance VIN = 0 10 12 10 12 7 10 pF

COUT Output Capacitance VOUT = 0 12 15 12 15 12 14 pF

Notes:
1. This parameter is only sampled and not 100% tested.
2. TA = +25°C, f = 1 MHz.

10 Am27C2048
PHYSICAL DIMENSIONS*
CDV040—40-Pin Ceramic Dual In-Line Package, UV Lens (measured in inches)

DATUM D
CENTER PLANE UV Lens
.565
.605
1
INDEX AND
TERMINAL NO. 1
I.D. AREA

TOP VIEW
DATUM D
CENTER PLANE .700
MAX
2.035
2.080
.160
BASE PLANE .220
SEATING PLANE 94°
.015 .125 105°
.060 .200

.005 MIN .300 BSC

.600
.045 BSC
.065 .008
.014 .100 BSC .018
.026

SIDE VIEW END VIEW

16-000038H-3
CDV040
DF11
3-30-95 ae

* For reference only. BSC is an ANSI standard for Basic Space Centering.

PD 040—40-Pin Plastic Dual In-Line Package (measured in inches)

2.040
2.080 .600
.625

40 21

.530 .008
.580 .015
Pin 1 I.D.
.630
20 .700
.045 0°
.065 .005 MIN 10°
.140
.225

SEATING PLANE 16-038-SC_AF

PD 040
.090 .015 DG76
.120 .110 .014 .060 2-28-95 ae
.160 .022

Am27C2048 11
PHYSICAL DIMENSIONS
PL 044—44-Pin Plastic Leaded Chip Carrier (measured in inches)
.062
.685 .042 .083
.695 .650 .056
.656

Pin 1 I.D.
.685 .500 .590
.695
REF .630
.650
.656
.013
.021

.009
.026 .015
.032 .050 REF .090
.120
.165
.180 SEATING PLANE 16-038-SQ
PL 044
EC80
TOP VIEW SIDE VIEW 11.3.97 lv

REVISION SUMMARY FOR AM27C2048

Revision G
Global
Changed formatting to match current data sheets.
Connection Diagrams
Corrected designation for pin 38 on PDIP connection
diagram to A16.

Trademarks

Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.

AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Flashrite is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

12 Am27C2048