512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
SST29SF/VF512 / 010 / 020 / 0405.0 & 2.7V 512Kb / 1Mb / 2Mb / 4Mb (x8) Byte-Program, Small Erase Sector flash memories Preliminary Specifications
FEATURES:
• Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8 • Fast Erase and Byte-Program:
• Single Voltage Read and Write Operations – Sector-Erase Time: 18 ms (typical)
– 5.0V-only for SST29SF512/010/020/040 – Chip-Erase Time: 70 ms (typical)
– 2.7-3.6V for SST29VF512/010/020/040 – Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time:
• Superior Reliability
1 second (typical) for SST29SF/VF512
– Endurance: 100,000 Cycles (typical) 2 seconds (typical) for SST29SF/VF010
– Greater than 100 years Data Retention 4 seconds (typical) for SST29SF/VF020
• Low Power Consumption: 8 seconds (typical) for SST29SF/VF040
– Active Current: 10 mA (typical) • Automatic Write Timing
– Standby Current: – Internal VPP Generation
30 µA (typical) for SST29SF512/010/020/040 • End-of-Write Detection
1 µA (typical) for SST29VF512/010/020/040
– Toggle Bit
• Sector-Erase Capability
– Data# Polling
– Uniform 128 Byte sectors • TTL I/O Compatibility for SST29SFxxx
• Fast Read Access Time:
• CMOS I/O Compatibility for SST29VFxxx
– 55 ns
• JEDEC Standard
– 70 ns
– Flash EEPROM Pinouts and command sets
• Latched Address and Data
• Packages Available
– 32-pin PLCC
– 32-pin TSOP (8mm x 14mm)
– 32-pin PDIP

PRODUCT DESCRIPTION
The SST29SF512/010/020/040 and SST29VF512/010/ and reliability, while lowering power consumption. They
020/040 are 64K x8 / 128K x8 / 256K x8 / 512K x8 CMOS inherently use less energy during Erase and Program than
Small-Sector Flash (SSF) manufactured with SST’s propri- alternative flash technologies. The total energy consumed
etary, high performance CMOS SuperFlash technology. is a function of the applied voltage, current, and time of
The split-gate cell design and thick oxide tunneling injector application. Since for any given voltage range, the Super-
attain better reliability and manufacturability compared with Flash technology uses less current to program and has a
alternate approaches. The SST29SFxxx devices write shorter erase time, the total energy consumed during any
(Program or Erase) with a 4.5-5.5V power supply. The Erase or Program operation is less than alternative flash
SST29VFxxx devices write (Program or Erase) with a 2.7- technologies. They also improve flexibility while lowering
3.6V power supply. These devices conform to JEDEC stan- the cost for program, data, and configuration storage appli-
dard pinouts for x8 memories. cations.
Featuring high performance Byte-Program, the The SuperFlash technology provides fixed Erase and Pro-
SST29SFxxx and SST29VFxxx devices provide a maxi- gram times, independent of the number of Erase/Program
mum Byte-Program time of 20 µsec. To protect against cycles that have occurred. Therefore the system software
inadvertent write, they have on-chip hardware and Soft- or hardware does not have to be modified or de-rated as is
ware Data Protection schemes. Designed, manufactured, necessary with alternative flash technologies, whose Erase
and tested for a wide spectrum of applications, these and Program times increase with accumulated Erase/Pro-
devices are offered with a guaranteed endurance of at least gram cycles.
10,000 cycles. Data retention is rated at greater than 100
To meet high density, surface mount requirements, the
years.
SST29SFxxx and SST29VFxxx devices are offered in 32-
The SST29SFxxx and SST29VFxxx devices are suited for pin PLCC and 32-pin TSOP packages. A 600 mil, 32-pin
applications that require convenient and economical updat- PDIP is also offered for SST29SFxxx devices. See Figures
ing of program, configuration, or data memory. For all sys- 1, 2, and 3 for pinouts.
tem applications, they significantly improve performance

©2001 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
S71160-05-000 5/01 505 SSF is a trademark of Silicon Storage Technology, Inc.
1 These specifications are subject to change without notice.
 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications

Device Operation edge of the sixth WE# pulse. The internal Erase operation
begins after the sixth WE# pulse. The End-of-Erase opera-
Commands are used to initiate the memory operation func-
tion can be determined using either Data# Polling or Toggle
tions of the device. Commands are written to the device
Bit methods. See Figure 9 for timing waveforms. Any com-
using standard microprocessor write sequences. A com-
mands issued during the Sector-Erase operation are
mand is written by asserting WE# low while keeping CE#
ignored.
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first. Chip-Erase Operation
The SST29SFxxx and SST29VFxxx devices provide a
Read Chip-Erase operation, which allows the user to erase the
entire memory array to the “1s” state. This is useful when
The Read operation of the SST29SFxxx and SST29VFxxx
the entire device must be quickly erased.
devices are controlled by CE# and OE#, both have to be
low for the system to obtain data from the outputs. CE# is The Chip-Erase operation is initiated by executing a six-
used for device selection. When CE# is high, the chip is byte Software Data Protection command sequence with
deselected and only standby power is consumed. OE# is Chip-Erase command (10H) with address 555H in the last
the output control and is used to gate data from the output byte sequence. The internal Erase operation begins with
pins. The data bus is in high impedance state when either the rising edge of the sixth WE# or CE#, whichever occurs
CE# or OE# is high. Refer to the Read cycle timing dia- first. During the internal Erase operation, the only valid read
gram for further details (Figure 4). is Toggle Bit or Data# Polling. See Table 4 for the command
sequence, Figure 10 for timing diagram, and Figure 19 for
Byte-Program Operation the flowchart. Any commands written during the Chip-
Erase operation will be ignored.
The SST29SFxxx and SST29VFxxx devices are pro-
grammed on a byte-by-byte basis. The Program operation
consists of three steps. The first step is the three-byte-load Write Operation Status Detection
sequence for Software Data Protection. The second step is The SST29SFxxx and SST29VFxxx devices provide two
to load byte address and byte data. During the Byte-Pro- software means to detect the completion of a Write (Pro-
gram operation, the addresses are latched on the falling gram or Erase) cycle, in order to optimize the system
edge of either CE# or WE#, whichever occurs last. The write cycle time. The software detection includes two sta-
data is latched on the rising edge of either CE# or WE#, tus bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The
whichever occurs first. The third step is the internal Pro- End-of-Write detection mode is enabled after the rising
gram operation which is initiated after the rising edge of the edge of WE# which initiates the internal Program or
fourth WE# or CE#, whichever occurs first. The Program Erase operation.
operation, once initiated, will be completed, within 20 µs.
The actual completion of the nonvolatile write is asynchro-
See Figures 5 and 6 for WE# and CE# controlled Program
nous with the system; therefore, either a Data# Polling or
operation timing diagrams and Figure 16 for flowcharts.
Toggle Bit read may be simultaneous with the completion
During the Program operation, the only valid reads are
of the Write cycle. If this occurs, the system may possibly
Data# Polling and Toggle Bit. During the internal Program
get an erroneous result, i.e., valid data may appear to con-
operation, the host is free to perform additional tasks. Any
flict with either DQ7 or DQ6. In order to prevent spurious
commands written during the internal Program operation
rejection, if an erroneous result occurs, the software routine
will be ignored.
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
Sector-Erase Operation device has completed the Write cycle, otherwise the rejec-
The Sector-Erase operation allows the system to erase the tion is valid.
device on a sector-by-sector basis. The SST29SFxxx and
SST29VFxxx offer Sector-Erase mode. The sector archi-
tecture is based on uniform sector size of 128 Bytes. The
Sector-Erase operation is initiated by executing a six-byte-
command sequence with Sector-Erase command (20H)
and sector address (SA) in the last bus cycle. The sector
address is latched on the falling edge of the sixth WE#
pulse, while the command (20H) is latched on the rising

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications

Data# Polling (DQ7) the Program operation, providing optimal protection from
inadvertent write operations, e.g., during the system power-
When the SST29SFxxx and SST29VFxxx devices are in
up or power-down. Any Erase operation requires the inclu-
the internal Program operation, any attempt to read DQ7
sion of six byte load sequence. These devices are shipped
will produce the complement of the true data. Once the
with the Software Data Protection permanently enabled.
Program operation is completed, DQ7 will produce true
See Table 4 for the specific software command codes. Dur-
data. The device is then ready for the next operation. Dur-
ing SDP command sequence, invalid commands will abort
ing internal Erase operation, any attempt to read DQ7 will
the device to read mode, within TRC.
produce a ‘0’. Once the internal Erase operation is com-
pleted, DQ7 will produce a ‘1’. The Data# Polling is valid
after the rising edge of fourth WE# (or CE#) pulse for Pro- Product Identification
gram operation. For Sector- or Chip-Erase, the Data# Poll- The Product Identification mode identifies the devices as
ing is valid after the rising edge of sixth WE# (or CE#) SST29SF512, SST29SF010, SST29SF020, SST29SF040
pulse. See Figure 7 for Data# Polling timing diagram and and SST29VF512, SST29VF010, SST29VF020,
Figure 17 for a flowchart. SST29VF040 and manufacturer as SST. This mode may
be accessed by software operations. Users may use the
Toggle Bit (DQ6) Software Product Identification operation to identify the part
(i.e., using the device ID) when using multiple manufactur-
During the internal Program or Erase operation, any con-
ers in the same socket. For details, see Table 4 for software
secutive attempts to read DQ6 will produce alternating 0s
operation, Figure 11 for the Software ID Entry and Read
and 1s, i.e., toggling between 0 and 1. When the internal
timing diagram and Figure 18 for the Software ID Entry
Program or Erase operation is completed, the toggling will
command sequence flowchart.
stop. The device is then ready for the next operation. The
Toggle Bit is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector or Chip- TABLE 1: PRODUCT IDENTIFICATION
Erase, the Toggle Bit is valid after the rising edge of sixth Address Data
WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing dia- Manufacturer’s ID 0000H BFH
gram and Figure 17 for a flowchart. Device ID
SST29SF512 0001H 20H
Data Protection SST29VF512 0001H 21H
The SST29SFxxx and SST29VFxxx devices provide both SST29SF010 0001H 22H
hardware and software features to protect nonvolatile data SST29VF010 0001H 23H
from inadvertent writes.
SST29SF020 0001H 24H
SST29VF020 0001H 25H
Hardware Data Protection
SST29SF040 0001H 13H
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 SST29VF040 0001H 14H
ns will not initiate a write cycle. T1.1 505

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 2.5V for SST29SFxxx. The Product Identification Mode Exit/Reset
Write operation is inhibited when VDD is less than 1.5V. for In order to return to the standard Read mode, the Software
SST29VFxxx. Product Identification mode must be exited. Exit is accom-
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# plished by issuing the Software ID Exit command
high will inhibit the Write operation. This prevents inadvert- sequence, which returns the device to the Read operation.
ent writes during power-up or power-down. Please note that the Software ID Exit command is ignored
during an internal Program or Erase operation. See Table 4
for software command codes, Figure 12 for timing wave-
Software Data Protection (SDP) form and Figure 18 for a flowchart.
The SST29SFxxx and SST29VFxxx provide the JEDEC
approved Software Data Protection scheme for all data
alteration operation, i.e., Program and Erase. Any Program
operation requires the inclusion of a series of three byte
sequence. The three byte-load sequence is used to initiate

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

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 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications

FUNCTIONAL BLOCK DIAGRAM

SuperFlash
X-Decoder Memory

Memory
Address Buffers & Latches
Address
Y-Decoder

CE#
OE# Control Logic I/O Buffers and Data Latches
WE#
DQ7 - DQ0
505 ILL B1.1
SST29SF/VF512 SST29SF/VF010 SST29SF/VF020 SST29SF/VF040

WE#
VDD
A12

A15

A16

A18

A17
WE#
VDD
A12

A15

A16

A17
NC

WE#
VDD
A12

A15

A16

NC

NC
WE#
VDD
A12

A15

NC

NC

NC

SST29SF/VF040 SST29SF/VF020 SST29SF/VF010 SST29SF/VF512 SST29SF/VF512 SST29SF/VF010 SST29SF/VF020 SST29SF/VF040

4 3 2 1 32 31 30
A7 A7 A7 A7 5 29 A14 A14 A14 A14
A6 A6 A6 A6 6 28 A13 A13 A13 A13
A5 A5 A5 A5 7 27 A8 A8 A8 A8
A4 A4 A4 A4 8 26 A9 A9 A9 A9
32-pin PLCC
A3 A3 A3 A3 9 25 A11 A11 A11 A11
10
Top View 24
A2 A2 A2 A2 OE# OE# OE# OE#
A1 A1 A1 A1 11 23 A10 A10 A10 A10
A0 A0 A0 A0 12 22 CE# CE# CE# CE#
DQ0 DQ0 DQ0 DQ0 13 21 DQ7 DQ7 DQ7 DQ7
14 15 16 17 18 19 20
SST29SF/VF040 SST29SF/VF020 SST29SF/VF010 SST29SF/VF512

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

505 ILL F02a.3

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6
DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6
DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN PLCC

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications

SST29SF/VF040 SST29SF/VF020 SST29SF/VF010 SST29SF/VF512 SST29SF/VF512 SST29SF/VF010 SST29SF/VF020 SST29SF/VF040

A11 A11 A11 A11 1 32 OE# OE# OE# OE#

A9 A9 A9 A9 2 31 A10 A10 A10 A10
A8 A8 A8 A8 3 30 CE# CE# CE# CE#
A13 A13 A13 A13 4 29 DQ7 DQ7 DQ7 DQ7
A14 A14 A14 A14 5 28 DQ6 DQ6 DQ6 DQ6
A17 A17 NC NC 6 Standard Pinout 27 DQ5 DQ5 DQ5 DQ5
WE# WE# WE# WE# 7 26 DQ4 DQ4 DQ4 DQ4
VDD VDD VDD VDD 8 Top View 25 DQ3 DQ3 DQ3 DQ3
A18 NC NC NC 9 24 VSS VSS VSS VSS
A16 A16 A16 NC 10 Die Up 23 DQ2 DQ2 DQ2 DQ2
A15 A15 A15 A15 11 22 DQ1 DQ1 DQ1 DQ1
A12 A12 A12 A12 12 21 DQ0 DQ0 DQ0 DQ0
A7 A7 A7 A7 13 20 A0 A0 A0 A0
A6 A6 A6 A6 14 19 A1 A1 A1 A1
A5 A5 A5 A5 15 18 A2 A2 A2 A2
A4 A4 A4 A4 16 17 A3 A3 A3 A3

505 ILL F01.2

FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN TSOP (8MM X 14MM)

SST29SF040 SST29SF020 SST29SF010 SST29SF512 SST29SF512 SST29SF010 SST29SF020 SST29SF040

A18 NC NC NC 1 32 VDD VDD VDD VDD

A16 A16 A16 NC 2 31 WE# WE# WE# WE#
A15 A15 A15 A15 3 30 NC NC A17 A17
A12 A12 A12 A12 4 29 A14 A14 A14 A14
A7 A7 A7 A7 5 28 A13 A13 A13 A13
A6 A6 A6 A6 6 32-pin 27 A8 A8 A8 A8
A5 A5 A5 A5 7 PDIP 26 A9 A9 A9 A9
A4 A4 A4 A4 8 Top View 25 A11 A11 A11 A11
A3 A3 A3 A3 9 24 OE# OE# OE# OE#
A2 A2 A2 A2 10 23 A10 A10 A10 A10
A1 A1 A1 A1 11 22 CE# CE# CE# CE#
A0 A0 A0 A0 12 21 DQ7 DQ7 DQ7 DQ7
DQ0 DQ0 DQ0 DQ0 13 20 DQ6 DQ6 DQ6 DQ6
DQ1 DQ1 DQ1 DQ1 14 19 DQ5 DQ5 DQ5 DQ5
DQ2 DQ2 DQ2 DQ2 15 18 DQ4 DQ4 DQ4 DQ4
VSS VSS VSS VSS 16 17 DQ3 DQ3 DQ3 DQ3

505 ILL F02b.4

FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

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 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
TABLE 2: PIN DESCRIPTION
Symbol Pin Name Functions
AMS1-A0 Address Inputs To provide memory addresses. During Sector-Erase AMS-A8 address lines will select the
sector.
DQ7-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.
VDD Power Supply To provide power supply voltage: 4.5-5.5V for SST29SF512/010/020/040
2.7-3.6V for SST29VF512/010/020/040
VSS Ground
NC No Connection Pin not connected internally
T2.3 505
1. AMS = Most significant address
AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020, and A18 for SST29SF/VF040

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address
Read VIL VIL VIH DOUT AIN
Program VIL VIH VIL DIN AIN
Erase VIL VIH VIL X1 Sector address,
XXH for Chip-Erase
Standby VIH X X High Z X
Write Inhibit X VIL X High Z/ DOUT X
X X VIH High Z/ DOUT X
Product Identification
Software Mode VIL VIL VIH See Table 4
T3.4 505
1. X can be VIL or VIH, but no other value.

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command 1st Bus 2nd Bus 3rd Bus 4th Bus 5th Bus 6th Bus
Sequence Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle
Addr1 Data Addr1 Data Addr1 Data Addr1 Data Addr1 Data Addr1 Data
Byte-Program 555H AAH 2AAH 55H 555H A0H BA2 Data
Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SAX3 20H
Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H
Software ID Entry4,5 555H AAH 2AAH 55H 555H 90H
Software ID Exit6 XXH F0H
Software ID Exit6 555H AAH 2AAH 55H 555H F0H
T4.4 505
1. Address format A14-A0 (Hex),
Address A15 can be VIL or VIH, but no other value, for the Command sequence for SST29SF/VF512.
Addresses A15 - A16 can be VIL or VIH, but no other value, for the Command sequence for SST29SF/VF010.
Addresses A15 - A17 can be VIL or VIH, but no other value, for the Command sequence for SST29SF/VF020.
Addresses A15 - A18 can be VIL or VIH, but no other value, for the Command sequence for SST29SF/VF040.
2. BA = Program Byte address
3. SAX for Sector-Erase; uses AMS-A7 address lines for SST29SF/VFxxx
AMS = Most significant address
AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020, and A18 for SST29SF/VF040
4. The device does not remain in Software Product ID Mode if powered down.
5. With AMS-A1 =0; SST Manufacturer’s ID= BFH, is read with A0 = 0,
SST29SF512 Device ID = 20H, is read with A0 = 1
SST29SF512 Device ID = 21H, is read with A0 = 1
SST29SF010 Device ID = 22H, is read with A0 = 1
SST29VF010 Device ID = 23H, is read with A0 = 1
SST29SF020 Device ID = 24H, is read with A0 = 1
SST29SF020 Device ID = 25H, is read with A0 = 1
SST29SF040 Device ID = 13H, is read with A0 = 1
SST29VF040 Device ID = 14H, is read with A0 = 1
6. Both Software ID Exit operations are equivalent

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

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 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD + 1.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE FOR SST29SF512/010/020/040 OPERATING RANGE FOR SST29VF512/010/020/040

Range Ambient Temp VDD Range Ambient Temp VDD
Commercial 0°C to +70°C 5V±10% Commercial 0°C to +70°C 2.7-3.6V
Industrial -40°C to +85°C 5V±10% Industrial -40°C to +85°C 2.7-3.6V

AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF for 55 ns
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF for 70 ns
See Figures 13, 14, and 15

TABLE 5: DC OPERATING CHARACTERISTICS VDD = 5.0V±10% FOR SST29SFXXX

Limits
Symbol Parameter Min Max Units Test Conditions
IDD Power Supply Current Address input=VIL/VIH, at f=1/TRC Min
VDD=VDD Max
Read 20 mA CE#=OE#=VIL, WE#=VIH, all I/Os open
Write 20 mA CE#=WE#=VIL, OE#=VIH
ISB1 Standby VDD Current (TTL input) 3 mA CE#=VIH, VDD=VDD Max
ISB2 Standby VDD Current (CMOS input) 100 µA CE#=VIHC, VDD=VDD Max
ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max
VIL Input Low Voltage 0.8 V VDD=VDD Min
VIH Input High Voltage 2.0 V VDD=VDD Max
VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max
VOL Output Low Voltage 0.4 V IOL=2.1 µA, VDD=VDD Min
VOH Output High Voltage 2.4 V IOH=-400 µA, VDD=VDD Min
T5.3 505

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
TABLE 6: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V FOR SST29VFXXX
Limits
Symbol Parameter Min Max Units Test Conditions
IDD Power Supply Current Address input=VIL/VIH, at f=1/TRC Min
VDD=VDD Max
Read 20 mA CE#=OE#=VIL, WE#=VIH, all I/Os open
Write 20 mA CE#=WE#=VIL, OE#=VIH
ISB Standby VDD Current 15 µA CE#=VIHC, VDD=VDD Max
ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max
VIL Input Low Voltage 0.8 V VDD=VDD Min
VIH Input High Voltage 0.7VDD V VDD=VDD Max
VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max
VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min
VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min
T6.5 505

TABLE 7: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units
TPU-READ 1 Power-up to Read Operation 100 µs
TPU-WRITE1 Power-up to Program/Erase Operation 100 µs
T7.1 505
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 8: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum
CI/O 1 I/O Pin Capacitance VI/O = 0V 12 pF
CIN1 Input Capacitance VIN = 0V 6 pF
T8.1 505
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 9: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method
NEND1 Endurance 10,000 Cycles JEDEC Standard A117
TDR1 Data Retention 100 Years JEDEC Standard A103
ILTH1 Latch Up 100 + IDD mA JEDEC Standard 78
T9.2 505
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

9
 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications

AC CHARACTERISTICS

TABLE 10: READ CYCLE TIMING PARAMETERS

VDD = 5V±10% FOR SST29SFXXX AND 2.7-3.6V FOR SST29VFXXX
SST29SF/VFxxx-55 SST29SF/VFxxx-70
Symbol Parameter Min Max Min Max Units
TRC Read Cycle Time 55 70 ns
TCE Chip Enable Access Time 55 70 ns
TAA Address Access Time 55 70 ns
TOE Output Enable Access Time 30 35 ns
TCLZ1 CE# Low to Active Output 0 0 ns
TOLZ1 OE# Low to Active Output 0 0 ns
TCHZ1 CE# High to High-Z Output 20 25 ns
TOHZ1 OE# High to High-Z Output 20 25 ns
TOH1 Output Hold from Address Change 0 0 ns
T10.5 505
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 11: PROGRAM/ERASE CYCLE TIMING PARAMETERS

VDD = 5V±10%V FOR SST29SFXXX AND 2.7-3.6V FOR SST29VFXXX
Symbol Parameter Min Max Units
TBP Byte-Program Time 20 µs
TAS Address Setup Time 0 ns
TAH Address Hold Time 30 ns
TCS WE# and CE# Setup Time 0 ns
TCH WE# and CE# Hold Time 0 ns
TOES OE# High Setup Time 0 ns
TOEH OE# High Hold Time 10 ns
TCP CE# Pulse Width 40 ns
TWP WE# Pulse Width 40 ns
TWPH 1 WE# Pulse Width High 30 ns
TCPH1 CE# Pulse Width High 30 ns
TDS Data Setup Time 40 ns
TDH 1 Data Hold Time 0 ns
TIDA1 Software ID Access and Exit Time 150 ns
TSE Sector-Erase 25 ms
TSCE Chip-Erase 100 ms
T11.6 505
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

10
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications

TRC TAA

ADDRESS AMS-0

TCE
CE#

TOE
OE#

VIH TOLZ TOHZ

WE#

TCHZ
TOH
HIGH-Z TCLZ HIGH-Z
DQ7-0
DATA VALID DATA VALID

505 ILL F03.1

Note: AMS = Most Significant Address
AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040

FIGURE 4: READ CYCLE TIMING DIAGRAM

INTERNAL PROGRAM OPERATION STARTS

TBP

ADDRESS AMS-0 555 2AA 555 ADDR

TAH
TDH
TWP
WE#
TAS TWPH TDS

OE#

TCH
CE#

TCS

DQ7-0 AA 55 A0 DATA

SW0 SW1 SW2 BYTE

(ADDR/DATA) 505 ILL F04.1
Note: AMS = Most Significant Address
AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040

FIGURE 5: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

11
 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications

INTERNAL PROGRAM OPERATION STARTS

TBP

ADDRESS AMS-0 555 2AA 555 ADDR

TAH
TDH
TCP
CE#
TAS TCPH TDS

OE#

TCH
WE#

TCS

DQ7-0 AA 55 A0 DATA

SW0 SW1 SW2 BYTE

(ADDR/DATA) 505 ILL F05.1
Note: AMS = Most Significant Address
AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040

FIGURE 6: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

ADDRESS AMS-0

TCE

CE#

TOEH TOES

OE#

TOE

WE#

DQ7 D D# D# D

505 ILL F06.1

Note: AMS = Most Significant Address
AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040

FIGURE 7: DATA# POLLING TIMING DIAGRAM

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications

ADDRESS AMS-0

TCE

CE#

TOE TOES
TOEH

OE#

WE#

DQ6

TWO READ CYCLES 505 ILL F07.1

WITH SAME OUTPUTS
Note: AMS = Most Significant Address
AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040

FIGURE 8: TOGGLE BIT TIMING DIAGRAM

SIX-BYTE CODE FOR SECTOR-ERASE TSE

555 2AA 555 555 2AA SAX

ADDRESS AMS-0

CE#

OE#

TWP
WE#

DQ7-0
AA 55 80 AA 55 20

SW0 SW1 SW2 SW3 SW4 SW5

505 ILL F10.2

Note: The device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 11)
AMS = Most significant address
AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040

FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

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 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications

TSCE
SIX-BYTE CODE FOR CHIP-ERASE

555 2AA 555 555 2AA 555

ADDRESS AMS-0

CE#

OE#

TWP
WE#

DQ7-0
AA 55 80 AA 55 10

SW0 SW1 SW2 SW3 SW4 SW5

505 ILL F17.2
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 11)
Note: AMS = Most Significant Address
AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040

FIGURE 10: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

Three-Byte Sequence for

Software ID Entry

ADDRESS A14-0 555 2AA 555 0000 0001

CE# TIDA

OE#

TWP
WE#

TWPH
TAA
DQ7-0
AA 55 90 BF Device ID

SW0 SW1 SW2 505 ILL F08.2

Note: Device ID = 20H for SST29SF512, 22H for SST29SF010, 24H for SST29SF020, 13H for SST29SF040
21H for SST29VF512, 23H for SST29VF010, 25H for SST29VF020, 14H for SST29VF040

FIGURE 11: SOFTWARE ID ENTRY AND READ

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

ADDRESS A14-0 555 2AA 555

DQ7-0 AA 55 F0

TIDA
CE#

OE#

TWP
WE#
T WHP

SW0 SW1 SW2 505 ILL F21.0

FIGURE 12: SOFTWARE ID EXIT AND RESET

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

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 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications

VIHT

INPUT VIT REFERENCE POINTS VOT OUTPUT

VILT

505 ILL F11.0

AC test inputs are driven at VIHT (3.0 V) for a logic “1” and VILT (0 V) for a logic “0”. Measurement reference points for
inputs and outputs are VIT (1.5 VDD) and VOT (1.5 VDD). Input rise and fall times (10% ↔ 90%) are <10 ns.

Note: VIT - VINPUT Test

VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test

FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS FOR SST29SFXXX

VIHT

INPUT VIT REFERENCE POINTS VOT OUTPUT

VILT

505 ILL F11.0

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Test

VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test

FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS FOR SST29VFXXX

TEST LOAD EXAMPLE FOR SST29SF512/010/020/040 TEST LOAD EXAMPLE FOR SST29VF512/010/020/040

VDD
TO TESTER
TO TESTER

RL HIGH TO DUT

CL

505 ILL F12b.2

TO DUT

CL RL LOW

505 ILL F12.2

FIGURE 15: TEST LOAD EXAMPLES

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications

Start

Load data: AAH

Address: 555H

Load data: 55H

Address: 2AAH

Load data: A0H

Address: 555H

Load Byte
Address/Byte
Data

Wait for end of

Program (TBP,
Data# Polling
bit, or Toggle bit
operation)

Program
Completed

505 ILL F13.1

FIGURE 16: BYTE-PROGRAM ALGORITHM

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

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 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications

Internal Timer Toggle Bit Data# Polling

Byte- Byte- Byte-

Program/Erase Program/Erase Program/Erase
Initiated Initiated Initiated

Read byte Read DQ7

Wait TBP,
TSCE, or TSE

Read same No Is DQ7 =

byte true data?
Program/Erase
Completed
Yes

No Does DQ6 Program/Erase

match? Completed

Yes

Program/Erase
Completed
505 ILL F14.0

FIGURE 17: WAIT OPTIONS

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications

Software ID Entry Software ID Exit &

Command Sequence Reset Command Sequence

Load data: AAH Load data: AAH Load data: F0H

Address: 555H Address: 555H Address: XXH

Load data: 55H Load data: 55H

Wait TIDA
Address: 2AAH Address: 2AAH

Load data: 90H Load data: F0H Return to normal

Address: 555H Address: 555H operation

Wait TIDA Wait TIDA

Read Software ID Return to normal

operation
505 ILL F15.1

FIGURE 18: SOFTWARE ID COMMAND FLOWCHARTS

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

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 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications

Chip-Erase Sector-Erase
Command Sequence Command Sequence

Load data: AAH Load data: AAH

Address: 555H Address: 555H

Load data: 55H Load data: 55H

Address: 2AAH Address: 2AAH

Load data: 80H Load data: 80H

Address: 555H Address: 555H

Load data: AAH Load data: AAH

Address: 555H Address: 555H

Load data: 55H Load data: 55H

Address: 2AAH Address: 2AAH

Load data: 10H Load data: 20H

Address: 555H Address: SAX

Wait TSCE Wait TSE

Chip erased Sector erased

to FFH to FFH

505 ILL F19.2

FIGURE 19: ERASE COMMAND SEQUENCE

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications

Device Speed Suffix1 Suffix2

SST29xFxxx - XXX - XX - XX
Package Modifier
H = 32 pins
Numeric = Die modifier
Package Type
N = PLCC
W = TSOP (die up) (8mm x 14mm)
P = PDIP
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
55 = 55 ns
70 = 70 ns
Device Density
512 = 512 Kilobit
010 = 1 Megabit
020 = 2 Megabit
040 = 4 Megabit
Voltage
S = 5V±10%
V = 2.7-3.6V

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

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 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
SST29SF512 Valid combinations
SST29SF512-55-4C-NH SST29SF512-55-4C-WH
SST29SF512-70-4C-NH SST29SF512-70-4C-WH SST29SF512-70-4C-PH
SST29SF512-55-4I-NH SST29SF512-55-4I-WH
SST29SF512-70-4I-NH SST29SF512-70-4I-WH

SST29VF512 Valid combinations

SST29VF512-55-4C-NH SST29VF512-55-4C-WH
SST29VF512-70-4C-NH SST29VF512-70-4C-WH
SST29VF512-55-4I-NH SST29VF512-55-4I-WH
SST29VF512-70-4I-NH SST29VF512-70-4I-WH

SST29SF010 Valid combinations

SST29SF010-55-4C-NH SST29SF010-55-4C-WH
SST29SF010-70-4C-NH SST29SF010-70-4C-WH SST29SF010-70-4C-PH
SST29SF010-55-4I-NH SST29SF010-55-4I-WH
SST29SF010-70-4I-NH SST29SF010-70-4I-WH

SST29VF010 Valid combinations

SST29VF010-55-4C-NH SST29VF010-55-4C-WH
SST29VF010-70-4C-NH SST29VF010-70-4C-WH
SST29VF010-55-4I-NH SST29VF010-55-4I-WH
SST29VF010-70-4I-NH SST29VF010-70-4I-WH

SST29SF020 Valid combinations

SST29SF020-55-4C-NH SST29SF020-55-4C-WH
SST29SF020-70-4C-NH SST29SF020-70-4C-WH SST29SF020-70-4C-PH
SST29SF020-55-4I-NH SST29SF020-55-4I-WH
SST29SF020-70-4I-NH SST29SF020-70-4I-WH

SST29VF020 Valid combinations

SST29VF020-55-4C-NH SST29VF020-55-4C-WH
SST29VF020-70-4C-NH SST29VF020-70-4C-WH
SST29VF020-55-4I-NH SST29VF020-55-4I-WH
SST29VF020-70-4I-NH SST29VF020-70-4I-WH

SST29SF040 Valid combinations

SST29SF040-55-4C-NH SST29SF040-55-4C-WH
SST29SF040-70-4C-NH SST29SF040-70-4C-WH SST29SF040-70-4C-PH
SST29SF040-55-4I-NH SST29SF040-55-4I-WH
SST29SF040-70-4I-NH SST29SF040-70-4I-WH

SST29VF040 Valid combinations

SST29VF040-55-4C-NH SST29VF040-55-4C-WH
SST29VF040-70-4C-NH SST29VF040-70-4C-WH
SST29VF040-55-4I-NH SST29VF040-55-4I-WH
SST29VF040-70-4I-NH SST29VF040-70-4I-WH
Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications

PACKAGING DIAGRAMS

TOP VIEW SIDE VIEW BOTTOM VIEW

.485
.495
.106
.447
Optional .112
.453
Pin #1 Identifier .042 .023
.020 R. .030
x 30˚ R.
.048 2 1 32 MAX. .029 .040

.042 .013
.048 .021
.585 .547 .026 .400 .490
.595 .553 .032 BSC .530

.050
BSC.

.015 Min.
.075
.050 .095
BSC. .026
.125 .032
.140

Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
4. Coplanarity: 4 mils. 32.PLCC.NH-ILL.2

32-PIN PLASTIC LEAD CHIP CARRIER (PLCC)

SST PACKAGE CODE: NH

1.05
Pin # 1 Identifier 0.95

.50
BSC

.270
8.10 .170
7.90

12.50 0.15
0.05
12.30

0.70
0.50
14.20
13.80
32.TSOP-WH-ILL.4

Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±.05) mm.
4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.

32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM

SST PACKAGE CODE: WH

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

23
 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications

32

CL

.600
.625
Pin #1 Identifier 1 .530
.550
.065 1.645 7˚
.075 1.655 4 PLCS.

.170
Base Plane .200
Seating Plane

.015 0˚
.050 15˚
.008
.012
.120
.150
.070 .045 .016 .100 BSC .600 BSC
.080 .065 .022

Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. 32.pdipPH-ILL.2

32-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP)

SST PACKAGE CODE: PH

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.ssti.com

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

24