1 Megabit (128K x 8) Page Mode EEPROM

SST29EE010, SST29LE010, SST29VE010

Data Sheet

FEATURES:
• Single Voltage Read and Write Operations • Fast Read Access Time
– 5.0V-only for the 29EE010 – 5.0V-only operation: 90 and 120 ns 1
– 3.0V-only for the 29LE010 – 3.0V-only operation: 150 and 200 ns
– 2.7V-only for the 29VE010 – 2.7V-only operation: 200 and 250 ns
• Superior Reliability • Latched Address and Data 2
– Endurance: 100,000 Cycles (typical) • Automatic Write Timing
– Greater than 100 years Data Retention
– Internal Vpp Generation
• Low Power Consumption 3
• End of Write Detection
– Active Current: 20 mA (typical) for 5V and
10 mA (typical) for 3.0/2.7V – Toggle Bit
– Standby Current: 10 µA (typical) – Data# Polling 4
• Fast Page-Write Operation • Hardware and Software Data Protection
– 128 Bytes per Page, 1024 Pages • TTL I/O Compatibility
– Page-Write Cycle: 5 ms (typical)
• JEDEC Standard Byte-wide EEPROM Pinouts
5
– Complete Memory Rewrite: 5 sec (typical)
– Effective Byte-write Cycle Time: 39 µs • Packages Available
(typical) – 32-Pin TSOP (8x20 & 8x14 mm) 6
– 32-Lead PLCC
– 32 Pin Plastic DIP
7
PRODUCT DESCRIPTION applications, the 29EE010/29LE010/29VE010 signifi-
cantly improve performance and reliability, while lower- 8
The 29EE010/29LE010/29VE010 are 128K x 8 CMOS ing power consumption, when compared with floppy disk
page mode EEPROMs manufactured with SST’s propri- or EPROM approaches. The 29EE010/29LE010/
etary, high performance CMOS SuperFlash technology. 29VE010 improve flexibility while lowering the cost for 9
The split gate cell design and thick oxide tunneling program, data, and configuration storage applications.
injector attain better reliability and manufacturability To meet high density, surface mount requirements, the
compared with alternate approaches. The 29EE010/ 29EE010/29LE010/29VE010 are offered in 32-pin 10
29LE010/29VE010 write with a single power supply. TSOP and 32-lead PLCC packages. A 600-mil, 32-pin
Internal Erase/Program is transparent to the user. The PDIP package is also available. See Figures 1 and 2 for
29EE010/29LE010/29VE010 conform to JEDEC stan- pinouts. 11
dard pinouts for byte-wide memories.
Featuring high performance page write, the 29EE010/ Device Operation
29LE010/29VE010 provide a typical byte-write time of The SST page mode EEPROM offers in-circuit electrical 12
39 µsec. The entire memory, i.e., 128K bytes, can be write capability. The 29EE010/29LE010/29VE010 does
written page by page in as little as 5 seconds, when using not require separate erase and program operations. The
interface features such as Toggle Bit or Data# Polling to internally timed write cycle executes both erase and 13
indicate the completion of a write cycle. To protect program transparently to the user. The 29EE010/
against inadvertent write, the 29EE010/29LE010/ 29LE010/29VE010 have industry standard optional
29VE010 have on-chip hardware and software data Software Data Protection, which SST recommends al- 14
protection schemes. Designed, manufactured, and ways to be enabled. The 29EE010/29LE010/29VE010
tested for a wide spectrum of applications, the 29EE010/ are compatible with industry standard EEPROM pinouts
29LE010/29VE010 are offered with a guaranteed page- and functionality. 15
write endurance of 104 or 103 cycles. Data retention is
rated at greater than 100 years. Read
The Read operations of the 29EE010/29LE010/ 16
The 29EE010/29LE010/29VE010 are suited for applica- 29VE010 are controlled by CE# and OE#, both have to
tions that require convenient and economical updating of be low for the system to obtain data from the outputs.
program, configuration, or data memory. For all system CE# is used for device selection. When CE# is high, the

© 1998 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
304-04 12/97 1
 1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

chip is deselected and only standby power is consumed. leave the 29EE010/29LE010/29VE010 protected at the
OE# is the output control and is used to gate data from end of the page write. The page load cycle consists of
the output pins. The data bus is in high impedance state loading 1 to 128 bytes of data into the page buffer. The
when either CE# or OE# is high. Refer to the read cycle internal write cycle consists of the TBLCO time-out and the
timing diagram for further details (Figure 3). write timer operation. During the Write operation, the only
valid reads are Data# Polling and Toggle Bit.
Write
The Page-Write operation allows the loading of up to 128
The Page Write to the SST29EE010/29LE010/29VE010
bytes of data into the page buffer of the 29EE010/
should always use the JEDEC Standard Software Data
29LE010/29VE010 before the initiation of the internal
Protection (SDP) 3-byte command sequence. The
write cycle. During the internal write cycle, all the data in
29EE010/29LE010/29VE010 contain the optional
the page buffer is written simultaneously into the memory
JEDEC approved Software Data Protection scheme.
array. Hence, the page-write feature of 29EE010/
SST recommends that SDP always be enabled, thus, the
29LE010/29VE010 allow the entire memory to be written
description of the Write operations will be given using the
in as little as 5 seconds. During the internal write cycle,
SDP enabled format. The 3-byte SDP Enable and SDP
the host is free to perform additional tasks, such as to
Write commands are identical; therefore, any time a
fetch data from other locations in the system to set up the
SDP Write command is issued, software data protec-
write to the next page. In each Page-Write operation, all
tion is automatically assured. The first time the 3-byte
the bytes that are loaded into the page buffer must have
SDP command is given, the device becomes SDP en-
the same page address, i.e. A7 through A16. Any byte not
abled. Subsequent issuance of the same command
loaded with user data will be written to FF.
bypasses the data protection for the page being written.
At the end of the desired page write, the entire device See Figures 4 and 5 for the page-write cycle timing
remains protected. For additional descriptions, please diagrams. If after the completion of the 3-byte SDP load
see the application notes on “The Proper Use of JEDEC sequence or the initial byte-load cycle, the host loads a
Standard Software Data Protection” and “Protecting second byte into the page buffer within a byte-load cycle
Against Unintentional Writes When Using Single Power time (TBLC) of 100 µs, the 29EE010/29LE010/29VE010
Supply Flash Memories” in this data book. will stay in the page load cycle. Additional bytes are then
loaded consecutively. The page load cycle will be termi-
The Write operation consists of three steps. Step 1 is the
nated if no additional byte is loaded into the page buffer
three byte load sequence for Software Data Protection.
within 200 µs (TBLCO) from the last byte-load cycle, i.e.,
Step 2 is the byte-load cycle to a page buffer of the
no subsequent WE# or CE# high-to-low transition after
29EE010/29LE010/29VE010. Steps 1 and 2 use the
the last rising edge of WE# or CE#. Data in the page
same timing for both operations. Step 3 is an internally
buffer can be changed by a subsequent byte-load cycle.
controlled write cycle for writing the data loaded in the
The page load period can continue indefinitely, as long
page buffer into the memory array for nonvolatile stor-
as the host continues to load the device within the byte-
age. During both the SDP 3-byte load sequence and the
load cycle time of 100 µs. The page to be loaded is
byte-load cycle, the addresses are latched by the falling
determined by the page address of the last byte loaded.
edge of either CE# or WE#, whichever occurs last. The
data is latched by the rising edge of either CE# or WE#,
Software Chip-Erase
whichever occurs first. The internal write cycle is initiated
The 29EE010/29LE010/29VE010 provide a Chip-Erase
by the TBLCO timer after the rising edge of WE# or CE#,
operation, which allows the user to simultaneously clear
whichever occurs first. The write cycle, once initiated, will
the entire memory array to the “1” state. This is useful
continue to completion, typically within 5 ms. See Fig-
when the entire device must be quickly erased.
ures 4 and 5 for WE# and CE# controlled page write cycle
timing diagrams and Figures 14 and 16 for flowcharts. The Software Chip-Erase operation is initiated by using
a specific six byte-load sequence. After the load se-
The Write operation has three functional cycles: the
quence, the device enters into an internally timed cycle
Software Data Protection load sequence, the page load
similar to the write cycle. During the erase operation, the
cycle, and the internal write cycle. The Software Data
only valid read is Toggle Bit. See Table 4 for the load
Protection consists of a specific three byte load se-
sequence, Figure 9 for timing diagram, and Figure 18 for
quence that allows writing to the selected page and will
the flowchart.

© 1998 Silicon Storage Technology, Inc. 304-04 12/97

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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

Write Operation Status Detection Hardware Data Protection

The 29EE010/29LE010/29VE010 provide two software Noise/Glitch Protection: A WE# or CE# pulse of less than
means to detect the completion of a write cycle, in order 5 ns will not initiate a write cycle.
to optimize the system write cycle time. The software 1
VCC Power Up/Down Detection: The write operation is
detection includes two status bits: Data# Polling (DQ7)
inhibited when VCC is less than 2.5V.
and Toggle Bit (DQ6). The end of write detection mode is
enabled after the rising WE# or CE# whichever occurs Write Inhibit Mode: Forcing OE# low, CE# high, or WE# 2
first, which initiates the internal write cycle. high will inhibit the write operation. This prevents inad-
vertent writes during power-up or power-down.
The actual completion of the nonvolatile write is asyn- 3
chronous with the system; therefore, either a Data#
Software Data Protection (SDP)
Polling or Toggle Bit read may be simultaneous with the
The 29EE010/29LE010/29VE010 provide the JEDEC
completion of the write cycle. If this occurs, the system 4
approved optional software data protection scheme for
may possibly get an erroneous result, i.e., valid data may
all data alteration operations, i.e., Write and Chip erase.
appear to conflict with either DQ7 or DQ6. In order to
With this scheme, any write operation requires the inclu-
prevent spurious rejection, if an erroneous result occurs,
the software routine should include a loop to read the
sion of a series of three byte-load operations to precede 5
the data loading operation. The three byte-load se-
accessed location an additional two (2) times. If both
quence is used to initiate the write cycle, providing
reads are valid, then the device has completed the write
cycle, otherwise the rejection is valid.
optimal protection from inadvertent write operations, 6
e.g., during the system power-up or power-down. The
29EE010/29LE010/29VE010 are shipped with the soft-
Data# Polling (DQ7)
When the 29EE010/29LE010/29VE010 are in the inter-
ware data protection disabled. 7
nal write cycle, any attempt to read DQ7 of the last byte The software protection scheme can be enabled by
loaded during the byte-load cycle will receive the com- applying a three-byte sequence to the device, during a
plement of the true data. Once the write cycle is com- page-load cycle (Figures 4 and 5). The device will then 8
pleted, DQ7 will show true data. The device is then ready be automatically set into the data protect mode. Any
for the next operation. See Figure 6 for Data# Polling subsequent write operation will require the preceding
timing diagram and Figure 15 for a flowchart. three-byte sequence. See Table 4 for the specific soft- 9
ware command codes and Figures 4 and 5 for the timing
Toggle Bit (DQ6) diagrams. To set the device into the unprotected mode,
During the internal write cycle, any consecutive attempts a six-byte sequence is required. See Table 4 for the 10
to read DQ6 will produce alternating 0’s and 1’s, i.e. specific codes and Figure 8 for the timing diagram. If a
toggling between 0 and 1. When the write cycle is write is attempted while SDP is enabled the device will be
completed, the toggling will stop. The device is then in a non-accessible state for ~ 300 µs. SST recommends 11
ready for the next operation. See Figure 7 for Toggle Bit Software Data Protection always be enabled. See Figure
timing diagram and Figure 15 for a flowchart. The initial 16 for flowcharts.
read of the Toggle Bit will typically be a “1”.
The 29EE010/29LE010/29VE010 Software Data Pro- 12
tection is a global command, protecting (or unprotecting)
Data Protection
all pages in the entire memory array once enabled (or
The 29EE010/29LE010/29VE010 provide both hard-
disabled). Therefore using SDP for a single page write 13
ware and software features to protect nonvolatile data
will enable SDP for the entire array. Single pages by
from inadvertent writes.
themselves cannot be SDP enabled or disabled.
14

15

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 1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

Single power supply reprogrammable nonvolatile multiple manufacturers in the same socket. For details,
memories may be unintentionally altered. SST strongly see Table 3 for hardware operation or Table 4 for
recommends that Software Data Protection (SDP) al- software operation, Figure 10 for the software ID entry
ways be enabled. The 29EE010/29LE010/29VE010 and read timing diagram and Figure 17 for the ID entry
should be programmed using the SDP command se- command sequence flowchart. The manufacturer and
quence. SST recommends the SDP Disable Command device codes are the same for both operations.
Sequence not be issued to the device prior to writing.
TABLE 1: PRODUCT IDENTIFICATION TABLE
Please refer to the following Application Notes located at Byte Data
the back of this databook for more information on using
Manufacturer’s Code 0000 H BF H
SDP:
29EE010 Device Code 0001 H 07 H
• Protecting Against Unintentional Writes When Using
29LE010 Device Code 0001 H 08 H
Single Power Supply Flash Memories
29VE010 Device Code 0001 H 08 H
• The Proper Use of JEDEC Standard Software Data 304 PGM T1.1
Protection
Product Identification Mode Exit
Product Identification
The product identification mode identifies the device as In order to return to the standard read mode, the Soft-
the 29EE010/29LE010/29VE010 and manufacturer as ware Product Identification mode must be exited. Exiting
SST. This mode may be accessed by hardware or is accomplished by issuing the Software ID Exit (reset)
software operations. The hardware operation is typically operation, which returns the device to the read operation.
used by a programmer to identify the correct algorithm The Reset operation may also be used to reset the
for the 29EE010/29LE010/29VE010. Users may wish to device to the read mode after an inadvertent transient
use the software product identification operation to iden- condition that apparently causes the device to behave
tify the part (i.e. using the device code) when using abnormally, e.g. not read correctly. See Table 4 for
software command codes, Figure 11 for timing wave-
form and Figure 17 for a flowchart.

FUNCTIONAL BLOCK DIAGRAM OF SST 29EE010/29LE010/29VE010

1,048,576 Bit
EEPROM
X-Decoder
Cell Array

A16 - A0 Address buffer & Latches

Y-Decoder and Page Latches

CE#
OE# Control Logic I/O Buffers and Data Latches
WE#

DQ7 - DQ0
304 MSW B1.0

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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

A11 1 32 OE#
A9 2 31 A10
A8
A13
3
4
30
29
CE#
DQ7
1
A14 5 Standard Pinout 28 DQ6
NC 6 27 DQ5
WE# 7 Top View 26 DQ4
Vcc
NC
8
9
25
24
DQ3
Vss
2
A16 10 23 DQ2
A15 11 22 DQ1
A12 12 Die up 21 DQ0
A7 13 20 A0 3
A6 14 19 A1
A5 15 18 A2
A4 16 17 A3
304 MSW F01.1 4
FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP PACKAGES
5

NC
A16
1
2
32
31
Vcc
WE# A12
A15
A16
NC
Vcc
WE#
NC 6
A15 3 30 NC
A12 4 29 A14 4 3 2 1 32 31 30
A7 5 A7 5 29 A14
A6 6
28
27
A13
A8 A6 6 28 A13 7
A5 7 26 A9 A5 7 27 A8
A4 8
32-Pin PDIP
25 A11 A4 8 26 A9
A3 9 Top View 24 OE#
A2 10 23 A10
A3 9 32-Lead PLCC 25 A11
OE#
8
A1 A2 10 Top View 24
11 22 CE#
A0 12 21 DQ7 A1 11 23 A10
DQ0 13 20 DQ6 A0 12 22 CE#
DQ1 14 19 DQ5 DQ0 13 21 DQ7 9
DQ2 15 18 DQ4 14 15 16 17 18 19 20
Vss 16 17 DQ3
DQ1
DQ2
Vss
DQ3
DQ4
DQ5
DQ6
304 MSW F02.1
10
FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PLASTIC DIPS AND 32-LEAD PLCCS
11
TABLE 2: PIN DESCRIPTION
Symbol Pin Name Functions
A16-A7 Row Address Inputs To provide memory addresses. Row addresses define a page for a
12
write cycle.
A6-A0 Column Address Column Addresses are toggled to load page data. 13
Inputs
DQ7-DQ0 Data Input/output To output data during read cycles and receive input data during write
cycles. Data is internally latched during a write cycle. The outputs are in
tri-state when OE# or CE# is high. 14
CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers. 15
WE# Write Enable To control the write operations
Vcc Power Supply To provide 5-volt supply (± 10%) for the 29EE010, 3-volt supply (3.0-3.6V)
for the 29LE010 and 2.7-volt supply (2.7-3.6V) for the 29VE010 16
Vss Ground
NC No Connection Unconnected pins.
304 PGM T2.0

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 1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address
Read VIL VIL VIH DOUT AIN
Page Write VIL VIH VIL DIN AIN
Standby VIH X X High Z X
Write Inhibit X VIL X High Z/ DOUT X
Write Inhibit X X VIH High Z/ DOUT X
Software Chip Erase VIL VIH VIL DIN AIN, See Table 4
Product Identification
Hardware Mode VIL VIL VIH Manufacturer Code (BF) A16 - A1 = VIL, A9 = VH, A0 = VIL
Device Code (see notes) A16 - A1 = VIL, A9 = VH, A0= VIH
Software Mode VIL VIH VIL See Table 4
SDP Enable Mode VIL VIH VIL See Table 4
SDP Disable Mode VIL VIH VIL See Table 4
304 PGM T3.0

TABLE 4: SOFTWARE COMMAND CODES

Command 1st Bus 2nd Bus 3rd Bus 4th Bus 5th Bus 6th Bus
Sequence Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle
Addr(1) Data Addr(1) Data Addr(1) Data Addr(1) Data Addr(1) Data Addr(1) Data
Software Data 5555H AAH 2AAAH 55H 5555H A0H Addr(2) Data
Protect Enable
& Page Write
Software Data 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 20H
Protect Disable
Software Chip 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Erase
Software ID Entry 5555H AAH 2AAAH 55H 5555H 90H

Software ID Exit 5555H AAH 2AAAH 55H 5555H F0H

Alternate Software 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 60H
ID Entry(3)
304 PGM T4.1

Notes: (1)
Address format A14-A0 (Hex), Addresses A15 and A16 are a “Don’t Care”.
(2)
Page Write consists of loading up to 128 bytes (A6 - A0).
(3) Alternate 6 byte software Product-ID Command Code
(4) The software chip erase function is not supported by the industrial temperature part.

Please contact SST, if you require this function for an industrial temperature part.
Notes for Software Product ID Command Code:
1. With A14 -A1 =0; SST Manufacturer Code = BFH, is read with A0 = 0,
29EE010 Device Code = 07H, is read with A0 = 1.
29LE010/29VE010 Device Code = 08H, is read with A0 = 1.
2. The device does not remain in Software Product ID Mode if powered down.

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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress
Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device
at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied.
Exposure to absolute maximum stress rating conditions may affect device reliability.)
1
Temperature Under Bias ................................................................................................................. -55°C to +125°C
Storage Temperature ...................................................................................................................... -65°C to +150°C 2
D. C. Voltage on Any Pin to Ground Potential ............................................................................. -0.5V to VCC+ 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential ......................................................... -1.0V to VCC+ 1.0V
Voltage on A9 Pin to Ground Potential ................................................................................................ -0.5V to 14.0V
3
Package Power Dissipation Capability (Ta = 25°C) ........................................................................................... 1.0W
Through Hole Lead Soldering Temperature (10 Seconds) .............................................................................. 300°C 4
Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240°C
Output Short Circuit Current(1) ....................................................................................................................... 100 mA
Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time. 5

6
29EE010 OPERATING RANGE AC CONDITIONS OF TEST
Range Ambient Temp VCC Input Rise/Fall Time ......... 10 ns
Commercial 0°C to +70°C 5V±10% Output Load ..................... 1 TTL Gate and CL = 100 pF 7
Industrial -40°C to +85°C 5V±10% See Figures 12 and 13
29LE010 OPERATING RANGE 8
Range Ambient Temp VCC
Commercial 0°C to +70°C 3.0V to 3.6V
Industrial -40°C to +85°C 3.0V to 3.6V
9
29VE010 OPERATING RANGE
10
Range Ambient Temp VCC
Commercial 0°C to +70°C 2.7V to 3.6V
Industrial -40°C to +85°C 2.7V to 3.6V 11

12

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 1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

TABLE 5: 29EE010 DC OPERATING CHARACTERISTICS VCC = 5V±10%

Limits
Symbol Parameter Min Max Units Test Conditions
ICC Power Supply Current CE#=OE#=VIL,WE#=VIH , all I/Os open,
Read 30 mA Address input = VIL/VIH, at f=1/TRC Min.,
VCC=VCC Max
Write 50 mA CE#=WE#=VIL, OE#=VIH, VCC =VCC Max.
ISB1 Standby VCC Current 3 mA CE#=OE#=WE#=VIH, VCC =VCC Max.
(TTL input)
ISB2 Standby VCC Current 50 µA CE#=OE#=WE#=VCC -0.3V.
(CMOS input) VCC = VCC Max.
ILI Input Leakage Current 1 µA VIN =GND to VCC, VCC = VCC Max.
ILO Output Leakage Current 10 µA VOUT =GND to VCC, VCC = VCC Max.
VIL Input Low Voltage 0.8 V VCC = VCC Max.
VIH Input High Voltage 2.0 V VCC = VCC Max.
VOL Output Low Voltage 0.4 V IOL = 2.1 mA, VCC = VCC Min.
VOH Output High Voltage 2.4 V IOH = -400µA, VCC = VCC Min.
VH Supervoltage for A9 11.6 12.4 V CE# = OE# =VIL, WE# = VIH
IH Supervoltage Current 100 µA CE# = OE# = VIL, WE# = VIH,
for A9 A9 = VH Max.
304 PGM T5.0

TABLE 6: 29LE010/29VE010 DC OPERATING CHARACTERISTICS VCC = 3.0-3.6 FOR 29LE010, VCC = 2.7-3.6 FOR 29VE010
Limits
Symbol Parameter Min Max Units Test Conditions
ICC Power Supply Current CE#=OE#=VIL,WE#=VIH , all I/Os open,
Read 12 mA Address input = VIL/VIH, at f=1/TRC Min.,
VCC=VCC Max
Write 15 mA CE#=WE#=VIL, OE#=VIH, VCC =VCC Max.
ISB1 Standby VCC Current 1 mA CE#=OE#=WE#=VIH, VCC =VCC Max.
(TTL input)
ISB2 Standby VCC Current 15 µA CE#=OE#=WE#=VCC -0.3V.
(CMOS input) VCC = VCC Max.
ILI Input Leakage Current 1 µA VIN =GND to VCC, VCC = VCC Max.
ILO Output Leakage Current 10 µA VOUT =GND to VCC, VCC = VCC Max.
VIL Input Low Voltage 0.8 V VCC = VCC Max.
VIH Input High Voltage 2.0 V VCC = VCC Max.
VOL Output Low Voltage 0.4 V IOL = 100 µA, VCC = VCC Min.
VOH Output High Voltage 2.4 V IOH = -100 µA, VCC = VCC Min.
VH Supervoltage for A9 11.6 12.4 V CE# = OE# =VIL, WE# = VIH
IH Supervoltage Current 100 µA CE# = OE# = VIL, WE# = VIH,
for A9 A9 = VH Max.
304 PGM T6.0

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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

TABLE 7: POWER-UP TIMINGS

Symbol Parameter Maximum Units
TPU-READ(1) Power-up to Read Operation 100 µs 1
TPU-WRITE (1) Power-up to Write Operation 5 ms
304 PGM T7.0
2
TABLE 8: CAPACITANCE (Ta = 25 °C, f=1 MHz, other pins open)
Parameter Description Test Condition Maximum
3
CI/O(1) I/O Pin Capacitance VI/O = 0V 12 pF
CIN(1) Input Capacitance VIN = 0V 6 pF
304 PGM T8.0 4
Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

5
TABLE 9: RELIABILITY CHARACTERISTICS
Symbol Parameter Minimum Specification Units Test Method 6
NEND Endurance 10,000(2) Cycles MIL-STD-883, Method 1033
TDR(1) Data Retention 100 Years JEDEC Standard A103
VZAP_HBM(1) ESD Susceptibility 1000 Volts JEDEC Standard A114
7
Human Body Model
VZAP_MM(1) ESD Susceptibility 200 Volts JEDEC Standard A115
Machine Model 8
ILTH(1) Latch Up 100 mA JEDEC Standard 78
304 PGM T9.1
9
Note: (1)Thisparameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(2)See Ordering Information for desired type.

10

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 1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

AC CHARACTERISTICS

TABLE 10: 29EE010 READ CYCLE TIMING PARAMETERS

29EE010-90 29EE010-120
Symbol Parameter Min Max Min Max Units
TRC Read Cycle time 90 120 ns
TCE Chip Enable Access Time 90 120 ns
TAA Address Access Time 90 120 ns
TOE Output Enable Access Time 40 50 ns
TCLZ(1) CE# Low to Active Output 0 0 ns
TOLZ(1) OE# Low to Active Output 0 0 ns
TCHZ (1) CE# High to High-Z Output 30 30 ns
TOHZ(1) OE# High to High-Z Output 30 30 ns
TOH(1) Output Hold from Address 0 0 ns
Change
304 PGM T10.1

TABLE 11: 29LE010 READ CYCLE TIMING PARAMETERS

29LE010-150 29LE010-200
Symbol Parameter Min Max Min Max Units
TRC Read Cycle time 150 200 ns
TCE Chip Enable Access Time 150 200 ns
TAA Address Access Time 150 200 ns
TOE Output Enable Access Time 60 100 ns
TCLZ(1) CE# Low to Active Output 0 0 ns
TOLZ(1) OE# Low to Active Output 0 0 ns
TCHZ(1) CE# High to High-Z Output 30 50 ns
TOHZ(1) OE# High to High-Z Output 30 50 ns
TOH(1) Output Hold from Address Change 0 0 ns
304 PGM T11.0

TABLE 12: 29VE010 READ CYCLE TIMING PARAMETERS

29VE010-200 29VE010-250
Symbol Parameter Min Max Min Max Units
TRC Read Cycle time 200 250 ns
TCE Chip Enable Access Time 200 250 ns
TAA Address Access Time 200 250 ns
TOE Output Enable Access Time 100 120 ns
TCLZ(1) CE# Low to Active Output 0 0 ns
TOLZ(1) OE# Low to Active Output 0 0 ns
TCHZ(1) CE# High to High-Z Output 50 50 ns
TOHZ(1) OE# High to High-Z Output 50 50 ns
TOH(1) Output Hold from Address Change 0 0 ns
304 PGM T12.0

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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

TABLE 13: PAGE-WRITE CYCLE TIMING PARAMETERS

29EE010 29LE/VE010
Symbol Parameter Min Max Min Max Units 1
TWC Write Cycle (erase and program) 10 10 ms
TAS Address Setup Time 0 0 ns
TAH Address Hold Time 50 70 ns 2
TCS WE# and CE# Setup Time 0 0 ns
TCH WE# and CE# Hold Time 0 0 ns 3
TOES OE# High Setup Time 0 0 ns
TOEH OE# High Hold Time 0 0 ns
TCP CE# Pulse Width 70 120 ns 4
TWP WE# Pulse Width 70 120 ns
TDS Data Setup Time 35 50 ns
5
TDH Data Hold Time 0 0 ns
TBLC(1) Byte Load Cycle Time 0.05 100 0.05 100 µs
TBLCO(1) Byte Load Cycle Time 200 200 µs 6
TIDA Software ID Access and Exit Time 10 10 µs
TSCE Software Chip Erase 20 20 ms
7
304 PGM T13.1
Note: (1)This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.

10

11

12

13

14

15

16

© 1998 Silicon Storage Technology, Inc. 304-04 12/97

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 1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

304 AC F03.0
FIGURE 3: READ CYCLE TIMING DIAGRAM

304 AC F04.0

FIGURE 4: WE# CONTROLLED PAGE WRITE CYCLE TIMING DIAGRAM

© 1998 Silicon Storage Technology, Inc. 304-04 12/97

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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

304 AC F05.0 7
FIGURE 5: CE# CONTROLLED PAGE WRITE CYCLE TIMING DIAGRAM

10

11

12

13

14

15
304 AC F06.0

16
FIGURE 6: DATA# POLLING TIMING DIAGRAM

© 1998 Silicon Storage Technology, Inc. 304-04 12/97

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 1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

304 AC F07.0

FIGURE 7: TOGGLE BIT TIMING DIAGRAM

304 AC F08.0

FIGURE 8: SOFTWARE DATA PROTECT DISABLE TIMING DIAGRAM

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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

304 AC F09.0 7
FIGURE 9: SOFTWARE CHIP ERASE TIMING DIAGRAM
8

10

DEVICE CODE 11

12

13

14

DEVICE CODE = 07 for 29EE010 15

= 08 for 29LE010/29VE010
304 AC F10.0

FIGURE 10: SOFTWARE ID ENTRY AND READ

16

© 1998 Silicon Storage Technology, Inc. 304-04 12/97

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 1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

304 AC F11.0

FIGURE 11: SOFTWARE ID EXIT AND RESET

© 1998 Silicon Storage Technology, Inc. 304-04 12/97

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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

2.4 1
2.0 2.0
INPUT REFERENCE POINTS OUTPUT

0.4
0.8 0.8
2
304 MSW F12.0

3
AC test inputs are driven at VOH (2.4 VTTL) for a logic “1” and VOL (0.4 VTTL) for a logic “0”. Measurement reference
points for inputs and outputs are VIH (2.0 VTTL) and VIL (0.8 VTTL). Inputs rise and fall times (10% ↔ 90%) are <10
ns. 4
FIGURE 12: AC INPUT/OUTPUT REFERENCE WAVEFORMS
5

7
TEST LOAD EXAMPLE
VCC 8
TO TESTER
9
RL HIGH

10
TO DUT
11
CL RL LOW
12

13
304 MSW F13.0

14
FIGURE 13: TEST LOAD EXAMPLE

15

16

© 1998 Silicon Storage Technology, Inc. 304-04 12/97

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 1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

Start

Software Data
Software Data
See Figure 16 ProtectWrite
Protect Write
Command
Command

Set Page
Address

Set Byte
Address = 0

Load Byte
Data

Increment
Byte Address
By 1

No Byte
Address =
128 ?

Yes

Wait TBLCO
Wait BLCO

Wait
Wait for endofof
for end
Write (TWC
Write (TWC, Data
,
#Toggle
Pollingbitbitoror
Toggle
Data bit bit
# Polling
operation)
operation)

Write
Completed
Figure 14: Write Algorithm
304 MSW F14.0

FIGURE 14: WRITE ALGORITHM

© 1998 Silicon Storage Technology, Inc. 304-04 12/97

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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

Internal Timer Toggle Bit Data# Polling 1

Page Write Page Write Page Write 2

Initiated Initiated Initiated

Read DQ7 4
Wait TWC Read a byte
from page (Data for last
byte loaded)
5

Write 6
Completed Read same No
byte Is DQ7 =
true data? 7

Yes
8
No Does DQ6 Write
match? Completed 9

Yes 10
Write
Completed 11

12
304 MSW F15.0

FIGURE 15: WAIT OPTIONS 13

14

15

16

© 1998 Silicon Storage Technology, Inc. 304-04 12/97

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 1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

Software Data Protect Enable Software Data Protect

Command Sequence Disable Command Sequence

Write data: AA Write data: AA

Address: 5555 Address: 5555

Write data: 55 Write data: 55

Address: 2AAA Address: 2AAA

Write data: A0 Write data: 80

Address: 5555 Address: 5555

Write data: AA
Load 0 to Optional Page Load Address: 5555
128 Bytes of Operation
page data

Write data: 55
Address: 2AAA
Wait TBLCO

Write data: 20
Address: 5555

Wait TWC

Wait TBLCO

SDP Enabled

Wait TWC

SDP Disabled

304 MSW F16.0

FIGURE 16: SOFTWARE DATA PROTECTION FLOWCHARTS

© 1998 Silicon Storage Technology, Inc. 304-04 12/97

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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

Software Product ID Entry Software Product ID Exit &

1
Command Sequence Reset Command Sequence
2
Write data: AA Write data: AA
Address: 5555 Address: 5555
3

Write data: 55
4
Write data: 55
Address: 2AAA Address: 2AAA
5

Write data: 90 Write data: F0 6

Address: 5555 Address: 5555

Pause 10 µs Pause 10 µs 8

9
Return to normal
Read Software ID operation 10

11
304 MSW F17.0

FIGURE 17: SOFTWARE PRODUCT COMMAND FLOWCHARTS

12

13

14

15

16

© 1998 Silicon Storage Technology, Inc. 304-04 12/97

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 1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

Software Chip-Erase
Command Sequence

Write data: AA
Address: 5555

Write data: 55
Address: 2AAA

Write data: 80
Address: 5555

Write data: AA
Address: 5555

Write data: 55
Address: 2AAA

Write data: 10
Address: 5555

Wait TSCE

Chip Erase
to FFH

304 MSW F18.0

FIGURE 18: SOFTWARE CHIP ERASE COMMAND CODES

© 1998 Silicon Storage Technology, Inc. 304-04 12/97

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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

PRODUCT ORDERING INFORMATION

Device Speed Suffix1 Suffix2

1

SST29XE010 - XXX - XX - XX 2
Package Modifier
H = 32 leads 3
Numeric = Die modifier

Package Type 4
P = PDIP
N = PLCC
E = TSOP (die up) 8x20 mm 5
W = TSOP (die up) 8x14 mm
U = Unencapsulated die

Operating Temperature
6
C = Commercial = 0° to 70°C
I = Industrial = -40° to 85°C
7
Minimum Endurance
3 = 1000 cycles
4 = 10,000 cycles 8

Read Access Speed 9

250 = 250 ns
200 = 200 ns
150 = 150 ns 10
120 = 120 ns
90 = 90 ns
11
Voltage
E = 5V-only
L = 3V-only 12
V = 2.7V-only

13

14

15

16

© 1998 Silicon Storage Technology, Inc. 304-04 12/97

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 1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

29EE010 Valid combinations

SST29EE010- 90-4C- EH SST29EE010- 90-4C- NH SST29EE010- 90-4C- PH
SST29EE010-120-4C- EH SST29EE010-120-4C- NH SST29EE010-120-4C- PH

SST29EE010- 90-4C- WH
SST29EE010-120-4C- WH

SST29EE010- 90-4I-EH SST29EE010- 90-4I-NH

SST29EE010-120-4I-EH SST29EE010-120-4I-NH

SST29EE010-120-4C-U2

29LE010 Valid combinations

SST29LE010-150-4C- EH SST29LE010-150-4C- NH SST29LE010-150-4C- PH
SST29LE010-200-4C- EH SST29LE010-200-4C- NH SST29LE010-200-4C- PH

SST29LE010-150-4C- WH
SST29LE010-200-4C- WH

SST29LE010-150-4I-EH SST29LE010-150-4I-NH

SST29LE010-200-4C-U2

29VE010 Valid combinations

SST29VE010-200-4C- EH SST29VE010-200-4C- NH SST29VE010-200-4C- PH
SST29VE010-250-4C- EH SST29VE010-250-4C- NH SST29VE010-250-4C- PH

SST29VE010-200-4C-WH
SST29VE010-250-4C-WH

SST29VE010-200-4I-EH SST29VE010-200-4I-NH

SST29VE010-250-4C-U2

Example:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.

Note: The software chip erase function is not supported by the industrial temperature part.
Please contact SST, if you require this function for an industrial temperature part.

© 1998 Silicon Storage Technology, Inc. 304-04 12/97

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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

PACKAGING DIAGRAMS

6
32pn PDIP PH AC.2

Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (min/max). 7
3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.

32-LEAD PLASTIC DUAL-IN-LINE PACKAGE (PDIP)

SST PACKAGE CODE: PH
8

10

11

12

13

14

32pn PLCC NH AC.2 15

Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
16
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)
SST PACKAGE CODE: NH

© 1998 Silicon Storage Technology, Inc. 304-04 12/97

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 1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010

Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in metric (min/max).
3. Coplanarity: 0.1 (±.05) mm.
32pn TSOP WH AC.3

32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP)

SST PACKAGE CODE: WH

Note: 1. Complies with JEDEC publication 95 MO-142 BD dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in metric (min/max).
3. Coplanarity: 0.1 (±.05) mm. 32pn TSOP EH AC.4

32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP)

SST PACKAGE CODE: EH

© 1998 Silicon Storage Technology, Inc. 304-04 12/97

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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
SST Area Offices
U.S.A. - California (408) 523-7722 Canada - Toronto
U.S.A. - Florida (813) 771-8819 Kaltron Components Inc. (905) 405-6276
U.S.A. - Florida (941) 505-8893 Canada - Ottawa
U.S.A. - Massachusetts (978) 356-3845 Kaltron Components Inc.
Canada - Montreal
(819) 457-1225 1
Japan - Yokohama (81) 45-471-1851
Europe - UK (44) 1784-490455 Kaltron Components Inc. (514) 696-6589
Canada - B.C.
North American Sales Representatives Thorson Pacific, Inc.
Puerto Rico
(604) 294-3999
2
Alabama MEC/Caribe (787) 746-9897
Elcom, Inc. (205) 830-4001
International Sales Representatives & Distributors
Arizona
QuadRep, Inc. (602) 839-2102
3
Australia
California
ACD (61) 3-762 7644
Northern
Belgium
Premier Technical Sales
Southern
(408) 736-2260
Memec Brussels (32) 2778-9850 4
QuadRep, Inc., San Diego (619) 775-1188 China
QuadRep, Inc., Irvine (714) 727-4222 Actron Technology Co., Ltd. (86) 21-6482-8021
Colorado Denmark
QuadRep, Inc. (303) 771-6886 Berendsen Components A/S (45) 39-57-71-10 5
Florida Ireland
MEC Corporation - Central/East Coast (904) 427-7236 Memec Ireland LTD (353) 61 411842
MEC Corporation - South/East Coast (954) 426-8944 Finland
MEC Corporation - West Coast (813) 393-5011
France
OXXO OY AB (358) 9-5842 600 6
Georgia
Elcom, Inc. (770) 447-8200 RepDesign (33) 1 46 23 7990
Iowa A2M (33) 1 46 23 7900

Idaho
Oasis Sales Corporation (319) 377-8738 Germany
Endrich Bauelemente
7
QuadRep, Inc. (208) 939-9626 Vertriebs GMBH (49) 7452-60070
Illinois Metronik GmbH (49) 89-61108-0
Hong Kong
Oasis Sales Corporation - Northern
Rush & West Associates - Southern
(847) 640-1850
(314) 965-3322 Actron Technology Co., Ltd. (852) 2727-3978 8
Kansas Serial System (HK) Ltd. (852) 2950-0820
Rush & West Associates (913) 764-2700 Israel
Elina Electronics (972) 3-649 8543
Massachusetts
S-J Associates (978) 670-8899 Italy 9
Minnesota Carla Gavazzi Cefra SpA (39) 2-4801.2355
Cahill, Schmitz & Cahill (612) 646-7217 Japan
Missouri Asahi Electronics Co., Ltd. (81) 3-3350-5418
Rush & West Associates (314) 965-3322
Asahi Electronics Co., Ltd. (81) 93-511-6471 10
Hakuto Co., Ltd. (81) 3-3355-7615
North Carolina MICROTEK Inc. (81) 3-5300-5525
Elcom, Inc. - Charlotte (704) 543-1229 Ryoden Trading Co., Ltd. (81) 3-5396-6206
Elcom, Inc. - Raleigh (919) 743-5200
New Jersey Korea
Silicon Technology Co., Ltd. (81) 3-3795-6461
11
S-J Associates (609) 866-1234 Bigshine Korea Co., Ltd. (82) 2-832-8881
New Mexico Netherlands
QuadRep, Inc. (505) 332-2417 Memec Benelux (31) 40-265-9399
New York Singapore
12
S-J Associates - NYC (516) 536-4242 Serial System Ltd. (65) 286-1812
S-J Associates - Upstate (716) 924-1720
South Africa
Ohio KH Distributors (27) 11 845-5011
Great Lakes - Columbus
Great Lakes - Cleveland
(614) 885-6700
(216) 349-2700
Spain 13
Tekelec Espana S.A. (34) 13 20 41 60
Oregon
Sweden
Thorson Pacific, Inc. (503) 293-9001
Pelcon Electronics AB (46) 8.795 98 70
Texas
Tech. Mktg, Inc. - Carrollton (972) 387-3601
Switzerland 14
Leading Technology (41) 277-21 7-446
Tech. Mktg, Inc. - Houston (713) 783-4497
Tech. Mktg, Inc. - Austin (512) 343-6976 Taiwan, R.O.C.
Award Software (886) 22-555-0880
Utah
QuadRep, Inc. (801) 521-4717
PCT Limited
Tonsam Corporation
(886) 22-698-0098
(886) 22-651-0011
15
Virginia
United Kingdom
S-J Associates (703) 533-2233
Ambar Components, Ltd. (44) 1844-261144
Washington
Thorson Pacific, Inc. (425) 603-9393 16
Wisconsin
Oasis Sales Corporation (414) 782-6660
Revised 3-12-98

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873
© 1998 Silicon Storage Technology, Inc. 304-04 12/97
27